1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /**************************************************************************
3  * Copyright (c) 2007-2011, Intel Corporation.
4  * All Rights Reserved.
5  *
6  **************************************************************************/
7 
8 struct psb_intel_mode_device;
9 
10 /* MID device specific descriptors */
11 
12 struct oaktrail_timing_info {
13 	u16 pixel_clock;
14 	u8 hactive_lo;
15 	u8 hblank_lo;
16 	u8 hblank_hi:4;
17 	u8 hactive_hi:4;
18 	u8 vactive_lo;
19 	u8 vblank_lo;
20 	u8 vblank_hi:4;
21 	u8 vactive_hi:4;
22 	u8 hsync_offset_lo;
23 	u8 hsync_pulse_width_lo;
24 	u8 vsync_pulse_width_lo:4;
25 	u8 vsync_offset_lo:4;
26 	u8 vsync_pulse_width_hi:2;
27 	u8 vsync_offset_hi:2;
28 	u8 hsync_pulse_width_hi:2;
29 	u8 hsync_offset_hi:2;
30 	u8 width_mm_lo;
31 	u8 height_mm_lo;
32 	u8 height_mm_hi:4;
33 	u8 width_mm_hi:4;
34 	u8 hborder;
35 	u8 vborder;
36 	u8 unknown0:1;
37 	u8 hsync_positive:1;
38 	u8 vsync_positive:1;
39 	u8 separate_sync:2;
40 	u8 stereo:1;
41 	u8 unknown6:1;
42 	u8 interlaced:1;
43 } __packed;
44 
45 struct gct_r10_timing_info {
46 	u16 pixel_clock;
47 	u32 hactive_lo:8;
48 	u32 hactive_hi:4;
49 	u32 hblank_lo:8;
50 	u32 hblank_hi:4;
51 	u32 hsync_offset_lo:8;
52 	u16 hsync_offset_hi:2;
53 	u16 hsync_pulse_width_lo:8;
54 	u16 hsync_pulse_width_hi:2;
55 	u16 hsync_positive:1;
56 	u16 rsvd_1:3;
57 	u8  vactive_lo:8;
58 	u16 vactive_hi:4;
59 	u16 vblank_lo:8;
60 	u16 vblank_hi:4;
61 	u16 vsync_offset_lo:4;
62 	u16 vsync_offset_hi:2;
63 	u16 vsync_pulse_width_lo:4;
64 	u16 vsync_pulse_width_hi:2;
65 	u16 vsync_positive:1;
66 	u16 rsvd_2:3;
67 } __packed;
68 
69 struct oaktrail_panel_descriptor_v1 {
70 	u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
71 				/* 0x61190 if MIPI */
72 	u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
73 	u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
74 	u32 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */
75 						/* Register 0x61210 */
76 	struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
77 	u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
78 				/* Bit 0, Frequency, 15 bits,0 - 32767Hz */
79 			/* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */
80 	u16 Panel_MIPI_Display_Descriptor;
81 			/*16 bits, Defined as follows: */
82 			/* if MIPI, 0x0000 if LVDS */
83 			/* Bit 0, Type, 2 bits, */
84 			/* 0: Type-1, */
85 			/* 1: Type-2, */
86 			/* 2: Type-3, */
87 			/* 3: Type-4 */
88 			/* Bit 2, Pixel Format, 4 bits */
89 			/* Bit0: 16bpp (not supported in LNC), */
90 			/* Bit1: 18bpp loosely packed, */
91 			/* Bit2: 18bpp packed, */
92 			/* Bit3: 24bpp */
93 			/* Bit 6, Reserved, 2 bits, 00b */
94 			/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
95 			/* Bit 14, Reserved, 2 bits, 00b */
96 } __packed;
97 
98 struct oaktrail_panel_descriptor_v2 {
99 	u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
100 				/* 0x61190 if MIPI */
101 	u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
102 	u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
103 	u8 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */
104 						/* Register 0x61210 */
105 	struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
106 	u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
107 				/*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
108 	u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */
109 			/*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/
110 	u16 Panel_MIPI_Display_Descriptor;
111 			/*16 bits, Defined as follows: */
112 			/* if MIPI, 0x0000 if LVDS */
113 			/* Bit 0, Type, 2 bits, */
114 			/* 0: Type-1, */
115 			/* 1: Type-2, */
116 			/* 2: Type-3, */
117 			/* 3: Type-4 */
118 			/* Bit 2, Pixel Format, 4 bits */
119 			/* Bit0: 16bpp (not supported in LNC), */
120 			/* Bit1: 18bpp loosely packed, */
121 			/* Bit2: 18bpp packed, */
122 			/* Bit3: 24bpp */
123 			/* Bit 6, Reserved, 2 bits, 00b */
124 			/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
125 			/* Bit 14, Reserved, 2 bits, 00b */
126 } __packed;
127 
128 union oaktrail_panel_rx {
129 	struct {
130 		u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
131 			/* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
132 		u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
133 		/*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
134 		u16 SupportedVideoTransferMode:2; /*0: Non-burst only */
135 					/* 1: Burst and non-burst */
136 					/* 2/3: Reserved */
137 		u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/
138 		u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/
139 		u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/
140 		u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */
141 		u16 Rsvd:5;/*5 bits,00000b */
142 	} panelrx;
143 	u16 panel_receiver;
144 } __packed;
145 
146 struct gct_r0 {
147 	union { /*8 bits,Defined as follows: */
148 		struct {
149 			u8 PanelType:4; /*4 bits, Bit field for panels*/
150 					/* 0 - 3: 0 = LVDS, 1 = MIPI*/
151 					/*2 bits,Specifies which of the*/
152 			u8 BootPanelIndex:2;
153 					/* 4 panels to use by default*/
154 			u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
155 					/* the 4 MIPI DSI receivers to use*/
156 		} PD;
157 		u8 PanelDescriptor;
158 	};
159 	struct oaktrail_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
160 	union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
161 } __packed;
162 
163 struct gct_r1 {
164 	union { /*8 bits,Defined as follows: */
165 		struct {
166 			u8 PanelType:4; /*4 bits, Bit field for panels*/
167 					/* 0 - 3: 0 = LVDS, 1 = MIPI*/
168 					/*2 bits,Specifies which of the*/
169 			u8 BootPanelIndex:2;
170 					/* 4 panels to use by default*/
171 			u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
172 					/* the 4 MIPI DSI receivers to use*/
173 		} PD;
174 		u8 PanelDescriptor;
175 	};
176 	struct oaktrail_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
177 	union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
178 } __packed;
179 
180 struct gct_r10 {
181 	struct gct_r10_timing_info DTD;
182 	u16 Panel_MIPI_Display_Descriptor;
183 	u16 Panel_MIPI_Receiver_Descriptor;
184 	u16 Panel_Backlight_Inverter_Descriptor;
185 	u8 Panel_Initial_Brightness;
186 	u32 MIPI_Ctlr_Init_ptr;
187 	u32 MIPI_Panel_Init_ptr;
188 } __packed;
189 
190 struct oaktrail_gct_data {
191 	u8 bpi; /* boot panel index, number of panel used during boot */
192 	u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */
193 	struct oaktrail_timing_info DTD; /* timing info for the selected panel */
194 	u32 Panel_Port_Control;
195 	u32 PP_On_Sequencing;/*1 dword,Register 0x61208,*/
196 	u32 PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/
197 	u32 PP_Cycle_Delay;
198 	u16 Panel_Backlight_Inverter_Descriptor;
199 	u16 Panel_MIPI_Display_Descriptor;
200 } __packed;
201 
202 #define MODE_SETTING_IN_CRTC		0x1
203 #define MODE_SETTING_IN_ENCODER		0x2
204 #define MODE_SETTING_ON_GOING		0x3
205 #define MODE_SETTING_IN_DSR		0x4
206 #define MODE_SETTING_ENCODER_DONE	0x8
207 
208 /*
209  *	Moorestown HDMI interfaces
210  */
211 
212 struct oaktrail_hdmi_dev {
213 	struct pci_dev *dev;
214 	void __iomem *regs;
215 	unsigned int mmio, mmio_len;
216 	int dpms_mode;
217 	struct hdmi_i2c_dev *i2c_dev;
218 
219 	/* register state */
220 	u32 saveDPLL_CTRL;
221 	u32 saveDPLL_DIV_CTRL;
222 	u32 saveDPLL_ADJUST;
223 	u32 saveDPLL_UPDATE;
224 	u32 saveDPLL_CLK_ENABLE;
225 	u32 savePCH_HTOTAL_B;
226 	u32 savePCH_HBLANK_B;
227 	u32 savePCH_HSYNC_B;
228 	u32 savePCH_VTOTAL_B;
229 	u32 savePCH_VBLANK_B;
230 	u32 savePCH_VSYNC_B;
231 	u32 savePCH_PIPEBCONF;
232 	u32 savePCH_PIPEBSRC;
233 };
234 
235 extern void oaktrail_hdmi_setup(struct drm_device *dev);
236 extern void oaktrail_hdmi_teardown(struct drm_device *dev);
237 extern int  oaktrail_hdmi_i2c_init(struct pci_dev *dev);
238 extern void oaktrail_hdmi_i2c_exit(struct pci_dev *dev);
239 extern void oaktrail_hdmi_save(struct drm_device *dev);
240 extern void oaktrail_hdmi_restore(struct drm_device *dev);
241 extern void oaktrail_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev);
242 extern int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
243 						struct drm_display_mode *adjusted_mode, int x, int y,
244 						struct drm_framebuffer *old_fb);
245 extern void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode);
246 
247 
248