1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "include/logger_interface.h"
29
30 #include "irq_service_dce80.h"
31 #include "../dce110/irq_service_dce110.h"
32
33 #include "dce/dce_8_0_d.h"
34 #include "dce/dce_8_0_sh_mask.h"
35
36 #include "ivsrcid/ivsrcid_vislands30.h"
37
38 #include "dc_types.h"
39
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)40 static bool hpd_ack(
41 struct irq_service *irq_service,
42 const struct irq_source_info *info)
43 {
44 uint32_t addr = info->status_reg;
45 uint32_t value = dm_read_reg(irq_service->ctx, addr);
46 uint32_t current_status =
47 get_reg_field_value(
48 value,
49 DC_HPD1_INT_STATUS,
50 DC_HPD1_SENSE_DELAYED);
51
52 dal_irq_service_ack_generic(irq_service, info);
53
54 value = dm_read_reg(irq_service->ctx, info->enable_reg);
55
56 set_reg_field_value(
57 value,
58 current_status ? 0 : 1,
59 DC_HPD1_INT_CONTROL,
60 DC_HPD1_INT_POLARITY);
61
62 dm_write_reg(irq_service->ctx, info->enable_reg, value);
63
64 return true;
65 }
66
67 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
68 .set = NULL,
69 .ack = hpd_ack
70 };
71
72 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
73 .set = NULL,
74 .ack = NULL
75 };
76
77 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
78 .set = NULL,
79 .ack = NULL
80 };
81
82 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
83 .set = dce110_vblank_set,
84 .ack = NULL
85 };
86
87 static const struct irq_source_info_funcs vupdate_irq_info_funcs = {
88 .set = NULL,
89 .ack = NULL
90 };
91
92 #define hpd_int_entry(reg_num)\
93 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
94 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
95 .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
96 .enable_value = {\
97 DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
98 ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
99 },\
100 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
101 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
102 .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
103 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
104 .funcs = &hpd_irq_info_funcs\
105 }
106
107 #define hpd_rx_int_entry(reg_num)\
108 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
109 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
110 .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
111 .enable_value = {\
112 DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
113 ~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
114 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
115 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
116 .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
117 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
118 .funcs = &hpd_rx_irq_info_funcs\
119 }
120
121 #define pflip_int_entry(reg_num)\
122 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
123 .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
124 .enable_mask =\
125 GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
126 .enable_value = {\
127 GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
128 ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
129 .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
130 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
131 .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
132 .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
133 .funcs = &pflip_irq_info_funcs\
134 }
135
136 #define vupdate_int_entry(reg_num)\
137 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
138 .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
139 .enable_mask =\
140 CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
141 .enable_value = {\
142 CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
143 ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
144 .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
145 .ack_mask =\
146 CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
147 .ack_value =\
148 CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
149 .funcs = &vupdate_irq_info_funcs\
150 }
151
152 #define vblank_int_entry(reg_num)\
153 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
154 .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
155 .enable_mask =\
156 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
157 .enable_value = {\
158 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
159 ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
160 .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
161 .ack_mask =\
162 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
163 .ack_value =\
164 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
165 .funcs = &vblank_irq_info_funcs,\
166 .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
167 }
168
169 #define dummy_irq_entry() \
170 {\
171 .funcs = &dummy_irq_info_funcs\
172 }
173
174 #define i2c_int_entry(reg_num) \
175 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
176
177 #define dp_sink_int_entry(reg_num) \
178 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
179
180 #define gpio_pad_int_entry(reg_num) \
181 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
182
183 #define dc_underflow_int_entry(reg_num) \
184 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
185
186
187 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
188 .set = dal_irq_service_dummy_set,
189 .ack = dal_irq_service_dummy_ack
190 };
191
192 static const struct irq_source_info
193 irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = {
194 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
195 hpd_int_entry(1),
196 hpd_int_entry(2),
197 hpd_int_entry(3),
198 hpd_int_entry(4),
199 hpd_int_entry(5),
200 hpd_int_entry(6),
201 hpd_rx_int_entry(1),
202 hpd_rx_int_entry(2),
203 hpd_rx_int_entry(3),
204 hpd_rx_int_entry(4),
205 hpd_rx_int_entry(5),
206 hpd_rx_int_entry(6),
207 i2c_int_entry(1),
208 i2c_int_entry(2),
209 i2c_int_entry(3),
210 i2c_int_entry(4),
211 i2c_int_entry(5),
212 i2c_int_entry(6),
213 dp_sink_int_entry(1),
214 dp_sink_int_entry(2),
215 dp_sink_int_entry(3),
216 dp_sink_int_entry(4),
217 dp_sink_int_entry(5),
218 dp_sink_int_entry(6),
219 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
220 pflip_int_entry(0),
221 pflip_int_entry(1),
222 pflip_int_entry(2),
223 pflip_int_entry(3),
224 pflip_int_entry(4),
225 pflip_int_entry(5),
226 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
227 gpio_pad_int_entry(0),
228 gpio_pad_int_entry(1),
229 gpio_pad_int_entry(2),
230 gpio_pad_int_entry(3),
231 gpio_pad_int_entry(4),
232 gpio_pad_int_entry(5),
233 gpio_pad_int_entry(6),
234 gpio_pad_int_entry(7),
235 gpio_pad_int_entry(8),
236 gpio_pad_int_entry(9),
237 gpio_pad_int_entry(10),
238 gpio_pad_int_entry(11),
239 gpio_pad_int_entry(12),
240 gpio_pad_int_entry(13),
241 gpio_pad_int_entry(14),
242 gpio_pad_int_entry(15),
243 gpio_pad_int_entry(16),
244 gpio_pad_int_entry(17),
245 gpio_pad_int_entry(18),
246 gpio_pad_int_entry(19),
247 gpio_pad_int_entry(20),
248 gpio_pad_int_entry(21),
249 gpio_pad_int_entry(22),
250 gpio_pad_int_entry(23),
251 gpio_pad_int_entry(24),
252 gpio_pad_int_entry(25),
253 gpio_pad_int_entry(26),
254 gpio_pad_int_entry(27),
255 gpio_pad_int_entry(28),
256 gpio_pad_int_entry(29),
257 gpio_pad_int_entry(30),
258 dc_underflow_int_entry(1),
259 dc_underflow_int_entry(2),
260 dc_underflow_int_entry(3),
261 dc_underflow_int_entry(4),
262 dc_underflow_int_entry(5),
263 dc_underflow_int_entry(6),
264 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
265 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
266 vupdate_int_entry(0),
267 vupdate_int_entry(1),
268 vupdate_int_entry(2),
269 vupdate_int_entry(3),
270 vupdate_int_entry(4),
271 vupdate_int_entry(5),
272 vblank_int_entry(0),
273 vblank_int_entry(1),
274 vblank_int_entry(2),
275 vblank_int_entry(3),
276 vblank_int_entry(4),
277 vblank_int_entry(5),
278 };
279
280 static const struct irq_service_funcs irq_service_funcs_dce80 = {
281 .to_dal_irq_source = to_dal_irq_source_dce110
282 };
283
dce80_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)284 static void dce80_irq_construct(
285 struct irq_service *irq_service,
286 struct irq_service_init_data *init_data)
287 {
288 dal_irq_service_construct(irq_service, init_data);
289
290 irq_service->info = irq_source_info_dce80;
291 irq_service->funcs = &irq_service_funcs_dce80;
292 }
293
dal_irq_service_dce80_create(struct irq_service_init_data * init_data)294 struct irq_service *dal_irq_service_dce80_create(
295 struct irq_service_init_data *init_data)
296 {
297 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
298 GFP_KERNEL);
299
300 if (!irq_service)
301 return NULL;
302
303 dce80_irq_construct(irq_service, init_data);
304 return irq_service;
305 }
306
307
308