1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3  * Copyright 2014-2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include <linux/device.h>
25 #include <linux/export.h>
26 #include <linux/err.h>
27 #include <linux/fs.h>
28 #include <linux/file.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/compat.h>
33 #include <uapi/linux/kfd_ioctl.h>
34 #include <linux/time.h>
35 #include <linux/mm.h>
36 #include <linux/mman.h>
37 #include <linux/ptrace.h>
38 #include <linux/dma-buf.h>
39 #include <linux/fdtable.h>
40 #include <linux/processor.h>
41 #include "kfd_priv.h"
42 #include "kfd_device_queue_manager.h"
43 #include "kfd_svm.h"
44 #include "amdgpu_amdkfd.h"
45 #include "kfd_smi_events.h"
46 #include "amdgpu_dma_buf.h"
47 #include "kfd_debug.h"
48 
49 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
50 static int kfd_open(struct inode *, struct file *);
51 static int kfd_release(struct inode *, struct file *);
52 static int kfd_mmap(struct file *, struct vm_area_struct *);
53 
54 static const char kfd_dev_name[] = "kfd";
55 
56 static const struct file_operations kfd_fops = {
57 	.owner = THIS_MODULE,
58 	.unlocked_ioctl = kfd_ioctl,
59 	.compat_ioctl = compat_ptr_ioctl,
60 	.open = kfd_open,
61 	.release = kfd_release,
62 	.mmap = kfd_mmap,
63 };
64 
65 static int kfd_char_dev_major = -1;
66 static struct class *kfd_class;
67 struct device *kfd_device;
68 
kfd_lock_pdd_by_id(struct kfd_process * p,__u32 gpu_id)69 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id)
70 {
71 	struct kfd_process_device *pdd;
72 
73 	mutex_lock(&p->mutex);
74 	pdd = kfd_process_device_data_by_id(p, gpu_id);
75 
76 	if (pdd)
77 		return pdd;
78 
79 	mutex_unlock(&p->mutex);
80 	return NULL;
81 }
82 
kfd_unlock_pdd(struct kfd_process_device * pdd)83 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd)
84 {
85 	mutex_unlock(&pdd->process->mutex);
86 }
87 
kfd_chardev_init(void)88 int kfd_chardev_init(void)
89 {
90 	int err = 0;
91 
92 	kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
93 	err = kfd_char_dev_major;
94 	if (err < 0)
95 		goto err_register_chrdev;
96 
97 	kfd_class = class_create(kfd_dev_name);
98 	err = PTR_ERR(kfd_class);
99 	if (IS_ERR(kfd_class))
100 		goto err_class_create;
101 
102 	kfd_device = device_create(kfd_class, NULL,
103 					MKDEV(kfd_char_dev_major, 0),
104 					NULL, kfd_dev_name);
105 	err = PTR_ERR(kfd_device);
106 	if (IS_ERR(kfd_device))
107 		goto err_device_create;
108 
109 	return 0;
110 
111 err_device_create:
112 	class_destroy(kfd_class);
113 err_class_create:
114 	unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
115 err_register_chrdev:
116 	return err;
117 }
118 
kfd_chardev_exit(void)119 void kfd_chardev_exit(void)
120 {
121 	device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
122 	class_destroy(kfd_class);
123 	unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
124 	kfd_device = NULL;
125 }
126 
127 
kfd_open(struct inode * inode,struct file * filep)128 static int kfd_open(struct inode *inode, struct file *filep)
129 {
130 	struct kfd_process *process;
131 	bool is_32bit_user_mode;
132 
133 	if (iminor(inode) != 0)
134 		return -ENODEV;
135 
136 	is_32bit_user_mode = in_compat_syscall();
137 
138 	if (is_32bit_user_mode) {
139 		dev_warn(kfd_device,
140 			"Process %d (32-bit) failed to open /dev/kfd\n"
141 			"32-bit processes are not supported by amdkfd\n",
142 			current->pid);
143 		return -EPERM;
144 	}
145 
146 	process = kfd_create_process(current);
147 	if (IS_ERR(process))
148 		return PTR_ERR(process);
149 
150 	if (kfd_process_init_cwsr_apu(process, filep)) {
151 		kfd_unref_process(process);
152 		return -EFAULT;
153 	}
154 
155 	/* filep now owns the reference returned by kfd_create_process */
156 	filep->private_data = process;
157 
158 	dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
159 		process->pasid, process->is_32bit_user_mode);
160 
161 	return 0;
162 }
163 
kfd_release(struct inode * inode,struct file * filep)164 static int kfd_release(struct inode *inode, struct file *filep)
165 {
166 	struct kfd_process *process = filep->private_data;
167 
168 	if (process)
169 		kfd_unref_process(process);
170 
171 	return 0;
172 }
173 
kfd_ioctl_get_version(struct file * filep,struct kfd_process * p,void * data)174 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
175 					void *data)
176 {
177 	struct kfd_ioctl_get_version_args *args = data;
178 
179 	args->major_version = KFD_IOCTL_MAJOR_VERSION;
180 	args->minor_version = KFD_IOCTL_MINOR_VERSION;
181 
182 	return 0;
183 }
184 
set_queue_properties_from_user(struct queue_properties * q_properties,struct kfd_ioctl_create_queue_args * args)185 static int set_queue_properties_from_user(struct queue_properties *q_properties,
186 				struct kfd_ioctl_create_queue_args *args)
187 {
188 	/*
189 	 * Repurpose queue percentage to accommodate new features:
190 	 * bit 0-7: queue percentage
191 	 * bit 8-15: pm4_target_xcc
192 	 */
193 	if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
194 		pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
195 		return -EINVAL;
196 	}
197 
198 	if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
199 		pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
200 		return -EINVAL;
201 	}
202 
203 	if ((args->ring_base_address) &&
204 		(!access_ok((const void __user *) args->ring_base_address,
205 			sizeof(uint64_t)))) {
206 		pr_err("Can't access ring base address\n");
207 		return -EFAULT;
208 	}
209 
210 	if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
211 		pr_err("Ring size must be a power of 2 or 0\n");
212 		return -EINVAL;
213 	}
214 
215 	if (!access_ok((const void __user *) args->read_pointer_address,
216 			sizeof(uint32_t))) {
217 		pr_err("Can't access read pointer\n");
218 		return -EFAULT;
219 	}
220 
221 	if (!access_ok((const void __user *) args->write_pointer_address,
222 			sizeof(uint32_t))) {
223 		pr_err("Can't access write pointer\n");
224 		return -EFAULT;
225 	}
226 
227 	if (args->eop_buffer_address &&
228 		!access_ok((const void __user *) args->eop_buffer_address,
229 			sizeof(uint32_t))) {
230 		pr_debug("Can't access eop buffer");
231 		return -EFAULT;
232 	}
233 
234 	if (args->ctx_save_restore_address &&
235 		!access_ok((const void __user *) args->ctx_save_restore_address,
236 			sizeof(uint32_t))) {
237 		pr_debug("Can't access ctx save restore buffer");
238 		return -EFAULT;
239 	}
240 
241 	q_properties->is_interop = false;
242 	q_properties->is_gws = false;
243 	q_properties->queue_percent = args->queue_percentage & 0xFF;
244 	/* bit 8-15 are repurposed to be PM4 target XCC */
245 	q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
246 	q_properties->priority = args->queue_priority;
247 	q_properties->queue_address = args->ring_base_address;
248 	q_properties->queue_size = args->ring_size;
249 	q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
250 	q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
251 	q_properties->eop_ring_buffer_address = args->eop_buffer_address;
252 	q_properties->eop_ring_buffer_size = args->eop_buffer_size;
253 	q_properties->ctx_save_restore_area_address =
254 			args->ctx_save_restore_address;
255 	q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
256 	q_properties->ctl_stack_size = args->ctl_stack_size;
257 	if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
258 		args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
259 		q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
260 	else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
261 		q_properties->type = KFD_QUEUE_TYPE_SDMA;
262 	else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)
263 		q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI;
264 	else
265 		return -ENOTSUPP;
266 
267 	if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
268 		q_properties->format = KFD_QUEUE_FORMAT_AQL;
269 	else
270 		q_properties->format = KFD_QUEUE_FORMAT_PM4;
271 
272 	pr_debug("Queue Percentage: %d, %d\n",
273 			q_properties->queue_percent, args->queue_percentage);
274 
275 	pr_debug("Queue Priority: %d, %d\n",
276 			q_properties->priority, args->queue_priority);
277 
278 	pr_debug("Queue Address: 0x%llX, 0x%llX\n",
279 			q_properties->queue_address, args->ring_base_address);
280 
281 	pr_debug("Queue Size: 0x%llX, %u\n",
282 			q_properties->queue_size, args->ring_size);
283 
284 	pr_debug("Queue r/w Pointers: %px, %px\n",
285 			q_properties->read_ptr,
286 			q_properties->write_ptr);
287 
288 	pr_debug("Queue Format: %d\n", q_properties->format);
289 
290 	pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
291 
292 	pr_debug("Queue CTX save area: 0x%llX\n",
293 			q_properties->ctx_save_restore_area_address);
294 
295 	return 0;
296 }
297 
kfd_ioctl_create_queue(struct file * filep,struct kfd_process * p,void * data)298 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
299 					void *data)
300 {
301 	struct kfd_ioctl_create_queue_args *args = data;
302 	struct kfd_node *dev;
303 	int err = 0;
304 	unsigned int queue_id;
305 	struct kfd_process_device *pdd;
306 	struct queue_properties q_properties;
307 	uint32_t doorbell_offset_in_process = 0;
308 	struct amdgpu_bo *wptr_bo = NULL;
309 
310 	memset(&q_properties, 0, sizeof(struct queue_properties));
311 
312 	pr_debug("Creating queue ioctl\n");
313 
314 	err = set_queue_properties_from_user(&q_properties, args);
315 	if (err)
316 		return err;
317 
318 	pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
319 
320 	mutex_lock(&p->mutex);
321 
322 	pdd = kfd_process_device_data_by_id(p, args->gpu_id);
323 	if (!pdd) {
324 		pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
325 		err = -EINVAL;
326 		goto err_pdd;
327 	}
328 	dev = pdd->dev;
329 
330 	pdd = kfd_bind_process_to_device(dev, p);
331 	if (IS_ERR(pdd)) {
332 		err = -ESRCH;
333 		goto err_bind_process;
334 	}
335 
336 	if (!pdd->qpd.proc_doorbells) {
337 		err = kfd_alloc_process_doorbells(dev->kfd, pdd);
338 		if (err) {
339 			pr_debug("failed to allocate process doorbells\n");
340 			goto err_bind_process;
341 		}
342 	}
343 
344 	/* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
345 	 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
346 	 */
347 	if (dev->kfd->shared_resources.enable_mes &&
348 			((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK)
349 			>> AMDGPU_MES_API_VERSION_SHIFT) >= 2) {
350 		struct amdgpu_bo_va_mapping *wptr_mapping;
351 		struct amdgpu_vm *wptr_vm;
352 
353 		wptr_vm = drm_priv_to_vm(pdd->drm_priv);
354 		err = amdgpu_bo_reserve(wptr_vm->root.bo, false);
355 		if (err)
356 			goto err_wptr_map_gart;
357 
358 		wptr_mapping = amdgpu_vm_bo_lookup_mapping(
359 				wptr_vm, args->write_pointer_address >> PAGE_SHIFT);
360 		amdgpu_bo_unreserve(wptr_vm->root.bo);
361 		if (!wptr_mapping) {
362 			pr_err("Failed to lookup wptr bo\n");
363 			err = -EINVAL;
364 			goto err_wptr_map_gart;
365 		}
366 
367 		wptr_bo = wptr_mapping->bo_va->base.bo;
368 		if (wptr_bo->tbo.base.size > PAGE_SIZE) {
369 			pr_err("Requested GART mapping for wptr bo larger than one page\n");
370 			err = -EINVAL;
371 			goto err_wptr_map_gart;
372 		}
373 
374 		err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo);
375 		if (err) {
376 			pr_err("Failed to map wptr bo to GART\n");
377 			goto err_wptr_map_gart;
378 		}
379 	}
380 
381 	pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",
382 			p->pasid,
383 			dev->id);
384 
385 	err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, wptr_bo,
386 			NULL, NULL, NULL, &doorbell_offset_in_process);
387 	if (err != 0)
388 		goto err_create_queue;
389 
390 	args->queue_id = queue_id;
391 
392 
393 	/* Return gpu_id as doorbell offset for mmap usage */
394 	args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
395 	args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
396 	if (KFD_IS_SOC15(dev))
397 		/* On SOC15 ASICs, include the doorbell offset within the
398 		 * process doorbell frame, which is 2 pages.
399 		 */
400 		args->doorbell_offset |= doorbell_offset_in_process;
401 
402 	mutex_unlock(&p->mutex);
403 
404 	pr_debug("Queue id %d was created successfully\n", args->queue_id);
405 
406 	pr_debug("Ring buffer address == 0x%016llX\n",
407 			args->ring_base_address);
408 
409 	pr_debug("Read ptr address    == 0x%016llX\n",
410 			args->read_pointer_address);
411 
412 	pr_debug("Write ptr address   == 0x%016llX\n",
413 			args->write_pointer_address);
414 
415 	kfd_dbg_ev_raise(KFD_EC_MASK(EC_QUEUE_NEW), p, dev, queue_id, false, NULL, 0);
416 	return 0;
417 
418 err_create_queue:
419 	if (wptr_bo)
420 		amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo);
421 err_wptr_map_gart:
422 err_bind_process:
423 err_pdd:
424 	mutex_unlock(&p->mutex);
425 	return err;
426 }
427 
kfd_ioctl_destroy_queue(struct file * filp,struct kfd_process * p,void * data)428 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
429 					void *data)
430 {
431 	int retval;
432 	struct kfd_ioctl_destroy_queue_args *args = data;
433 
434 	pr_debug("Destroying queue id %d for pasid 0x%x\n",
435 				args->queue_id,
436 				p->pasid);
437 
438 	mutex_lock(&p->mutex);
439 
440 	retval = pqm_destroy_queue(&p->pqm, args->queue_id);
441 
442 	mutex_unlock(&p->mutex);
443 	return retval;
444 }
445 
kfd_ioctl_update_queue(struct file * filp,struct kfd_process * p,void * data)446 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
447 					void *data)
448 {
449 	int retval;
450 	struct kfd_ioctl_update_queue_args *args = data;
451 	struct queue_properties properties;
452 
453 	/*
454 	 * Repurpose queue percentage to accommodate new features:
455 	 * bit 0-7: queue percentage
456 	 * bit 8-15: pm4_target_xcc
457 	 */
458 	if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
459 		pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
460 		return -EINVAL;
461 	}
462 
463 	if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
464 		pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
465 		return -EINVAL;
466 	}
467 
468 	if ((args->ring_base_address) &&
469 		(!access_ok((const void __user *) args->ring_base_address,
470 			sizeof(uint64_t)))) {
471 		pr_err("Can't access ring base address\n");
472 		return -EFAULT;
473 	}
474 
475 	if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
476 		pr_err("Ring size must be a power of 2 or 0\n");
477 		return -EINVAL;
478 	}
479 
480 	properties.queue_address = args->ring_base_address;
481 	properties.queue_size = args->ring_size;
482 	properties.queue_percent = args->queue_percentage & 0xFF;
483 	/* bit 8-15 are repurposed to be PM4 target XCC */
484 	properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
485 	properties.priority = args->queue_priority;
486 
487 	pr_debug("Updating queue id %d for pasid 0x%x\n",
488 			args->queue_id, p->pasid);
489 
490 	mutex_lock(&p->mutex);
491 
492 	retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties);
493 
494 	mutex_unlock(&p->mutex);
495 
496 	return retval;
497 }
498 
kfd_ioctl_set_cu_mask(struct file * filp,struct kfd_process * p,void * data)499 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,
500 					void *data)
501 {
502 	int retval;
503 	const int max_num_cus = 1024;
504 	struct kfd_ioctl_set_cu_mask_args *args = data;
505 	struct mqd_update_info minfo = {0};
506 	uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
507 	size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
508 
509 	if ((args->num_cu_mask % 32) != 0) {
510 		pr_debug("num_cu_mask 0x%x must be a multiple of 32",
511 				args->num_cu_mask);
512 		return -EINVAL;
513 	}
514 
515 	minfo.cu_mask.count = args->num_cu_mask;
516 	if (minfo.cu_mask.count == 0) {
517 		pr_debug("CU mask cannot be 0");
518 		return -EINVAL;
519 	}
520 
521 	/* To prevent an unreasonably large CU mask size, set an arbitrary
522 	 * limit of max_num_cus bits.  We can then just drop any CU mask bits
523 	 * past max_num_cus bits and just use the first max_num_cus bits.
524 	 */
525 	if (minfo.cu_mask.count > max_num_cus) {
526 		pr_debug("CU mask cannot be greater than 1024 bits");
527 		minfo.cu_mask.count = max_num_cus;
528 		cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);
529 	}
530 
531 	minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL);
532 	if (!minfo.cu_mask.ptr)
533 		return -ENOMEM;
534 
535 	retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size);
536 	if (retval) {
537 		pr_debug("Could not copy CU mask from userspace");
538 		retval = -EFAULT;
539 		goto out;
540 	}
541 
542 	mutex_lock(&p->mutex);
543 
544 	retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo);
545 
546 	mutex_unlock(&p->mutex);
547 
548 out:
549 	kfree(minfo.cu_mask.ptr);
550 	return retval;
551 }
552 
kfd_ioctl_get_queue_wave_state(struct file * filep,struct kfd_process * p,void * data)553 static int kfd_ioctl_get_queue_wave_state(struct file *filep,
554 					  struct kfd_process *p, void *data)
555 {
556 	struct kfd_ioctl_get_queue_wave_state_args *args = data;
557 	int r;
558 
559 	mutex_lock(&p->mutex);
560 
561 	r = pqm_get_wave_state(&p->pqm, args->queue_id,
562 			       (void __user *)args->ctl_stack_address,
563 			       &args->ctl_stack_used_size,
564 			       &args->save_area_used_size);
565 
566 	mutex_unlock(&p->mutex);
567 
568 	return r;
569 }
570 
kfd_ioctl_set_memory_policy(struct file * filep,struct kfd_process * p,void * data)571 static int kfd_ioctl_set_memory_policy(struct file *filep,
572 					struct kfd_process *p, void *data)
573 {
574 	struct kfd_ioctl_set_memory_policy_args *args = data;
575 	int err = 0;
576 	struct kfd_process_device *pdd;
577 	enum cache_policy default_policy, alternate_policy;
578 
579 	if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
580 	    && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
581 		return -EINVAL;
582 	}
583 
584 	if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
585 	    && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
586 		return -EINVAL;
587 	}
588 
589 	mutex_lock(&p->mutex);
590 	pdd = kfd_process_device_data_by_id(p, args->gpu_id);
591 	if (!pdd) {
592 		pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
593 		err = -EINVAL;
594 		goto err_pdd;
595 	}
596 
597 	pdd = kfd_bind_process_to_device(pdd->dev, p);
598 	if (IS_ERR(pdd)) {
599 		err = -ESRCH;
600 		goto out;
601 	}
602 
603 	default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
604 			 ? cache_policy_coherent : cache_policy_noncoherent;
605 
606 	alternate_policy =
607 		(args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
608 		   ? cache_policy_coherent : cache_policy_noncoherent;
609 
610 	if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm,
611 				&pdd->qpd,
612 				default_policy,
613 				alternate_policy,
614 				(void __user *)args->alternate_aperture_base,
615 				args->alternate_aperture_size))
616 		err = -EINVAL;
617 
618 out:
619 err_pdd:
620 	mutex_unlock(&p->mutex);
621 
622 	return err;
623 }
624 
kfd_ioctl_set_trap_handler(struct file * filep,struct kfd_process * p,void * data)625 static int kfd_ioctl_set_trap_handler(struct file *filep,
626 					struct kfd_process *p, void *data)
627 {
628 	struct kfd_ioctl_set_trap_handler_args *args = data;
629 	int err = 0;
630 	struct kfd_process_device *pdd;
631 
632 	mutex_lock(&p->mutex);
633 
634 	pdd = kfd_process_device_data_by_id(p, args->gpu_id);
635 	if (!pdd) {
636 		err = -EINVAL;
637 		goto err_pdd;
638 	}
639 
640 	pdd = kfd_bind_process_to_device(pdd->dev, p);
641 	if (IS_ERR(pdd)) {
642 		err = -ESRCH;
643 		goto out;
644 	}
645 
646 	kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr);
647 
648 out:
649 err_pdd:
650 	mutex_unlock(&p->mutex);
651 
652 	return err;
653 }
654 
kfd_ioctl_dbg_register(struct file * filep,struct kfd_process * p,void * data)655 static int kfd_ioctl_dbg_register(struct file *filep,
656 				struct kfd_process *p, void *data)
657 {
658 	return -EPERM;
659 }
660 
kfd_ioctl_dbg_unregister(struct file * filep,struct kfd_process * p,void * data)661 static int kfd_ioctl_dbg_unregister(struct file *filep,
662 				struct kfd_process *p, void *data)
663 {
664 	return -EPERM;
665 }
666 
kfd_ioctl_dbg_address_watch(struct file * filep,struct kfd_process * p,void * data)667 static int kfd_ioctl_dbg_address_watch(struct file *filep,
668 					struct kfd_process *p, void *data)
669 {
670 	return -EPERM;
671 }
672 
673 /* Parse and generate fixed size data structure for wave control */
kfd_ioctl_dbg_wave_control(struct file * filep,struct kfd_process * p,void * data)674 static int kfd_ioctl_dbg_wave_control(struct file *filep,
675 					struct kfd_process *p, void *data)
676 {
677 	return -EPERM;
678 }
679 
kfd_ioctl_get_clock_counters(struct file * filep,struct kfd_process * p,void * data)680 static int kfd_ioctl_get_clock_counters(struct file *filep,
681 				struct kfd_process *p, void *data)
682 {
683 	struct kfd_ioctl_get_clock_counters_args *args = data;
684 	struct kfd_process_device *pdd;
685 
686 	mutex_lock(&p->mutex);
687 	pdd = kfd_process_device_data_by_id(p, args->gpu_id);
688 	mutex_unlock(&p->mutex);
689 	if (pdd)
690 		/* Reading GPU clock counter from KGD */
691 		args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev);
692 	else
693 		/* Node without GPU resource */
694 		args->gpu_clock_counter = 0;
695 
696 	/* No access to rdtsc. Using raw monotonic time */
697 	args->cpu_clock_counter = ktime_get_raw_ns();
698 	args->system_clock_counter = ktime_get_boottime_ns();
699 
700 	/* Since the counter is in nano-seconds we use 1GHz frequency */
701 	args->system_clock_freq = 1000000000;
702 
703 	return 0;
704 }
705 
706 
kfd_ioctl_get_process_apertures(struct file * filp,struct kfd_process * p,void * data)707 static int kfd_ioctl_get_process_apertures(struct file *filp,
708 				struct kfd_process *p, void *data)
709 {
710 	struct kfd_ioctl_get_process_apertures_args *args = data;
711 	struct kfd_process_device_apertures *pAperture;
712 	int i;
713 
714 	dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
715 
716 	args->num_of_nodes = 0;
717 
718 	mutex_lock(&p->mutex);
719 	/* Run over all pdd of the process */
720 	for (i = 0; i < p->n_pdds; i++) {
721 		struct kfd_process_device *pdd = p->pdds[i];
722 
723 		pAperture =
724 			&args->process_apertures[args->num_of_nodes];
725 		pAperture->gpu_id = pdd->dev->id;
726 		pAperture->lds_base = pdd->lds_base;
727 		pAperture->lds_limit = pdd->lds_limit;
728 		pAperture->gpuvm_base = pdd->gpuvm_base;
729 		pAperture->gpuvm_limit = pdd->gpuvm_limit;
730 		pAperture->scratch_base = pdd->scratch_base;
731 		pAperture->scratch_limit = pdd->scratch_limit;
732 
733 		dev_dbg(kfd_device,
734 			"node id %u\n", args->num_of_nodes);
735 		dev_dbg(kfd_device,
736 			"gpu id %u\n", pdd->dev->id);
737 		dev_dbg(kfd_device,
738 			"lds_base %llX\n", pdd->lds_base);
739 		dev_dbg(kfd_device,
740 			"lds_limit %llX\n", pdd->lds_limit);
741 		dev_dbg(kfd_device,
742 			"gpuvm_base %llX\n", pdd->gpuvm_base);
743 		dev_dbg(kfd_device,
744 			"gpuvm_limit %llX\n", pdd->gpuvm_limit);
745 		dev_dbg(kfd_device,
746 			"scratch_base %llX\n", pdd->scratch_base);
747 		dev_dbg(kfd_device,
748 			"scratch_limit %llX\n", pdd->scratch_limit);
749 
750 		if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS)
751 			break;
752 	}
753 	mutex_unlock(&p->mutex);
754 
755 	return 0;
756 }
757 
kfd_ioctl_get_process_apertures_new(struct file * filp,struct kfd_process * p,void * data)758 static int kfd_ioctl_get_process_apertures_new(struct file *filp,
759 				struct kfd_process *p, void *data)
760 {
761 	struct kfd_ioctl_get_process_apertures_new_args *args = data;
762 	struct kfd_process_device_apertures *pa;
763 	int ret;
764 	int i;
765 
766 	dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
767 
768 	if (args->num_of_nodes == 0) {
769 		/* Return number of nodes, so that user space can alloacate
770 		 * sufficient memory
771 		 */
772 		mutex_lock(&p->mutex);
773 		args->num_of_nodes = p->n_pdds;
774 		goto out_unlock;
775 	}
776 
777 	/* Fill in process-aperture information for all available
778 	 * nodes, but not more than args->num_of_nodes as that is
779 	 * the amount of memory allocated by user
780 	 */
781 	pa = kzalloc((sizeof(struct kfd_process_device_apertures) *
782 				args->num_of_nodes), GFP_KERNEL);
783 	if (!pa)
784 		return -ENOMEM;
785 
786 	mutex_lock(&p->mutex);
787 
788 	if (!p->n_pdds) {
789 		args->num_of_nodes = 0;
790 		kfree(pa);
791 		goto out_unlock;
792 	}
793 
794 	/* Run over all pdd of the process */
795 	for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) {
796 		struct kfd_process_device *pdd = p->pdds[i];
797 
798 		pa[i].gpu_id = pdd->dev->id;
799 		pa[i].lds_base = pdd->lds_base;
800 		pa[i].lds_limit = pdd->lds_limit;
801 		pa[i].gpuvm_base = pdd->gpuvm_base;
802 		pa[i].gpuvm_limit = pdd->gpuvm_limit;
803 		pa[i].scratch_base = pdd->scratch_base;
804 		pa[i].scratch_limit = pdd->scratch_limit;
805 
806 		dev_dbg(kfd_device,
807 			"gpu id %u\n", pdd->dev->id);
808 		dev_dbg(kfd_device,
809 			"lds_base %llX\n", pdd->lds_base);
810 		dev_dbg(kfd_device,
811 			"lds_limit %llX\n", pdd->lds_limit);
812 		dev_dbg(kfd_device,
813 			"gpuvm_base %llX\n", pdd->gpuvm_base);
814 		dev_dbg(kfd_device,
815 			"gpuvm_limit %llX\n", pdd->gpuvm_limit);
816 		dev_dbg(kfd_device,
817 			"scratch_base %llX\n", pdd->scratch_base);
818 		dev_dbg(kfd_device,
819 			"scratch_limit %llX\n", pdd->scratch_limit);
820 	}
821 	mutex_unlock(&p->mutex);
822 
823 	args->num_of_nodes = i;
824 	ret = copy_to_user(
825 			(void __user *)args->kfd_process_device_apertures_ptr,
826 			pa,
827 			(i * sizeof(struct kfd_process_device_apertures)));
828 	kfree(pa);
829 	return ret ? -EFAULT : 0;
830 
831 out_unlock:
832 	mutex_unlock(&p->mutex);
833 	return 0;
834 }
835 
kfd_ioctl_create_event(struct file * filp,struct kfd_process * p,void * data)836 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
837 					void *data)
838 {
839 	struct kfd_ioctl_create_event_args *args = data;
840 	int err;
841 
842 	/* For dGPUs the event page is allocated in user mode. The
843 	 * handle is passed to KFD with the first call to this IOCTL
844 	 * through the event_page_offset field.
845 	 */
846 	if (args->event_page_offset) {
847 		mutex_lock(&p->mutex);
848 		err = kfd_kmap_event_page(p, args->event_page_offset);
849 		mutex_unlock(&p->mutex);
850 		if (err)
851 			return err;
852 	}
853 
854 	err = kfd_event_create(filp, p, args->event_type,
855 				args->auto_reset != 0, args->node_id,
856 				&args->event_id, &args->event_trigger_data,
857 				&args->event_page_offset,
858 				&args->event_slot_index);
859 
860 	pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__);
861 	return err;
862 }
863 
kfd_ioctl_destroy_event(struct file * filp,struct kfd_process * p,void * data)864 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
865 					void *data)
866 {
867 	struct kfd_ioctl_destroy_event_args *args = data;
868 
869 	return kfd_event_destroy(p, args->event_id);
870 }
871 
kfd_ioctl_set_event(struct file * filp,struct kfd_process * p,void * data)872 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
873 				void *data)
874 {
875 	struct kfd_ioctl_set_event_args *args = data;
876 
877 	return kfd_set_event(p, args->event_id);
878 }
879 
kfd_ioctl_reset_event(struct file * filp,struct kfd_process * p,void * data)880 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
881 				void *data)
882 {
883 	struct kfd_ioctl_reset_event_args *args = data;
884 
885 	return kfd_reset_event(p, args->event_id);
886 }
887 
kfd_ioctl_wait_events(struct file * filp,struct kfd_process * p,void * data)888 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
889 				void *data)
890 {
891 	struct kfd_ioctl_wait_events_args *args = data;
892 
893 	return kfd_wait_on_events(p, args->num_events,
894 			(void __user *)args->events_ptr,
895 			(args->wait_for_all != 0),
896 			&args->timeout, &args->wait_result);
897 }
kfd_ioctl_set_scratch_backing_va(struct file * filep,struct kfd_process * p,void * data)898 static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
899 					struct kfd_process *p, void *data)
900 {
901 	struct kfd_ioctl_set_scratch_backing_va_args *args = data;
902 	struct kfd_process_device *pdd;
903 	struct kfd_node *dev;
904 	long err;
905 
906 	mutex_lock(&p->mutex);
907 	pdd = kfd_process_device_data_by_id(p, args->gpu_id);
908 	if (!pdd) {
909 		err = -EINVAL;
910 		goto err_pdd;
911 	}
912 	dev = pdd->dev;
913 
914 	pdd = kfd_bind_process_to_device(dev, p);
915 	if (IS_ERR(pdd)) {
916 		err = PTR_ERR(pdd);
917 		goto bind_process_to_device_fail;
918 	}
919 
920 	pdd->qpd.sh_hidden_private_base = args->va_addr;
921 
922 	mutex_unlock(&p->mutex);
923 
924 	if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
925 	    pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va)
926 		dev->kfd2kgd->set_scratch_backing_va(
927 			dev->adev, args->va_addr, pdd->qpd.vmid);
928 
929 	return 0;
930 
931 bind_process_to_device_fail:
932 err_pdd:
933 	mutex_unlock(&p->mutex);
934 	return err;
935 }
936 
kfd_ioctl_get_tile_config(struct file * filep,struct kfd_process * p,void * data)937 static int kfd_ioctl_get_tile_config(struct file *filep,
938 		struct kfd_process *p, void *data)
939 {
940 	struct kfd_ioctl_get_tile_config_args *args = data;
941 	struct kfd_process_device *pdd;
942 	struct tile_config config;
943 	int err = 0;
944 
945 	mutex_lock(&p->mutex);
946 	pdd = kfd_process_device_data_by_id(p, args->gpu_id);
947 	mutex_unlock(&p->mutex);
948 	if (!pdd)
949 		return -EINVAL;
950 
951 	amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config);
952 
953 	args->gb_addr_config = config.gb_addr_config;
954 	args->num_banks = config.num_banks;
955 	args->num_ranks = config.num_ranks;
956 
957 	if (args->num_tile_configs > config.num_tile_configs)
958 		args->num_tile_configs = config.num_tile_configs;
959 	err = copy_to_user((void __user *)args->tile_config_ptr,
960 			config.tile_config_ptr,
961 			args->num_tile_configs * sizeof(uint32_t));
962 	if (err) {
963 		args->num_tile_configs = 0;
964 		return -EFAULT;
965 	}
966 
967 	if (args->num_macro_tile_configs > config.num_macro_tile_configs)
968 		args->num_macro_tile_configs =
969 				config.num_macro_tile_configs;
970 	err = copy_to_user((void __user *)args->macro_tile_config_ptr,
971 			config.macro_tile_config_ptr,
972 			args->num_macro_tile_configs * sizeof(uint32_t));
973 	if (err) {
974 		args->num_macro_tile_configs = 0;
975 		return -EFAULT;
976 	}
977 
978 	return 0;
979 }
980 
kfd_ioctl_acquire_vm(struct file * filep,struct kfd_process * p,void * data)981 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
982 				void *data)
983 {
984 	struct kfd_ioctl_acquire_vm_args *args = data;
985 	struct kfd_process_device *pdd;
986 	struct file *drm_file;
987 	int ret;
988 
989 	drm_file = fget(args->drm_fd);
990 	if (!drm_file)
991 		return -EINVAL;
992 
993 	mutex_lock(&p->mutex);
994 	pdd = kfd_process_device_data_by_id(p, args->gpu_id);
995 	if (!pdd) {
996 		ret = -EINVAL;
997 		goto err_pdd;
998 	}
999 
1000 	if (pdd->drm_file) {
1001 		ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
1002 		goto err_drm_file;
1003 	}
1004 
1005 	ret = kfd_process_device_init_vm(pdd, drm_file);
1006 	if (ret)
1007 		goto err_unlock;
1008 
1009 	/* On success, the PDD keeps the drm_file reference */
1010 	mutex_unlock(&p->mutex);
1011 
1012 	return 0;
1013 
1014 err_unlock:
1015 err_pdd:
1016 err_drm_file:
1017 	mutex_unlock(&p->mutex);
1018 	fput(drm_file);
1019 	return ret;
1020 }
1021 
kfd_dev_is_large_bar(struct kfd_node * dev)1022 bool kfd_dev_is_large_bar(struct kfd_node *dev)
1023 {
1024 	if (debug_largebar) {
1025 		pr_debug("Simulate large-bar allocation on non large-bar machine\n");
1026 		return true;
1027 	}
1028 
1029 	if (dev->local_mem_info.local_mem_size_private == 0 &&
1030 	    dev->local_mem_info.local_mem_size_public > 0)
1031 		return true;
1032 
1033 	if (dev->local_mem_info.local_mem_size_public == 0 &&
1034 	    dev->kfd->adev->gmc.is_app_apu) {
1035 		pr_debug("APP APU, Consider like a large bar system\n");
1036 		return true;
1037 	}
1038 
1039 	return false;
1040 }
1041 
kfd_ioctl_get_available_memory(struct file * filep,struct kfd_process * p,void * data)1042 static int kfd_ioctl_get_available_memory(struct file *filep,
1043 					  struct kfd_process *p, void *data)
1044 {
1045 	struct kfd_ioctl_get_available_memory_args *args = data;
1046 	struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id);
1047 
1048 	if (!pdd)
1049 		return -EINVAL;
1050 	args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev,
1051 							pdd->dev->node_id);
1052 	kfd_unlock_pdd(pdd);
1053 	return 0;
1054 }
1055 
kfd_ioctl_alloc_memory_of_gpu(struct file * filep,struct kfd_process * p,void * data)1056 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
1057 					struct kfd_process *p, void *data)
1058 {
1059 	struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1060 	struct kfd_process_device *pdd;
1061 	void *mem;
1062 	struct kfd_node *dev;
1063 	int idr_handle;
1064 	long err;
1065 	uint64_t offset = args->mmap_offset;
1066 	uint32_t flags = args->flags;
1067 
1068 	if (args->size == 0)
1069 		return -EINVAL;
1070 
1071 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1072 	/* Flush pending deferred work to avoid racing with deferred actions
1073 	 * from previous memory map changes (e.g. munmap).
1074 	 */
1075 	svm_range_list_lock_and_flush_work(&p->svms, current->mm);
1076 	mutex_lock(&p->svms.lock);
1077 	mmap_write_unlock(current->mm);
1078 	if (interval_tree_iter_first(&p->svms.objects,
1079 				     args->va_addr >> PAGE_SHIFT,
1080 				     (args->va_addr + args->size - 1) >> PAGE_SHIFT)) {
1081 		pr_err("Address: 0x%llx already allocated by SVM\n",
1082 			args->va_addr);
1083 		mutex_unlock(&p->svms.lock);
1084 		return -EADDRINUSE;
1085 	}
1086 
1087 	/* When register user buffer check if it has been registered by svm by
1088 	 * buffer cpu virtual address.
1089 	 */
1090 	if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) &&
1091 	    interval_tree_iter_first(&p->svms.objects,
1092 				     args->mmap_offset >> PAGE_SHIFT,
1093 				     (args->mmap_offset  + args->size - 1) >> PAGE_SHIFT)) {
1094 		pr_err("User Buffer Address: 0x%llx already allocated by SVM\n",
1095 			args->mmap_offset);
1096 		mutex_unlock(&p->svms.lock);
1097 		return -EADDRINUSE;
1098 	}
1099 
1100 	mutex_unlock(&p->svms.lock);
1101 #endif
1102 	mutex_lock(&p->mutex);
1103 	pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1104 	if (!pdd) {
1105 		err = -EINVAL;
1106 		goto err_pdd;
1107 	}
1108 
1109 	dev = pdd->dev;
1110 
1111 	if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
1112 		(flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
1113 		!kfd_dev_is_large_bar(dev)) {
1114 		pr_err("Alloc host visible vram on small bar is not allowed\n");
1115 		err = -EINVAL;
1116 		goto err_large_bar;
1117 	}
1118 
1119 	pdd = kfd_bind_process_to_device(dev, p);
1120 	if (IS_ERR(pdd)) {
1121 		err = PTR_ERR(pdd);
1122 		goto err_unlock;
1123 	}
1124 
1125 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
1126 		if (args->size != kfd_doorbell_process_slice(dev->kfd)) {
1127 			err = -EINVAL;
1128 			goto err_unlock;
1129 		}
1130 		offset = kfd_get_process_doorbells(pdd);
1131 		if (!offset) {
1132 			err = -ENOMEM;
1133 			goto err_unlock;
1134 		}
1135 	} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1136 		if (args->size != PAGE_SIZE) {
1137 			err = -EINVAL;
1138 			goto err_unlock;
1139 		}
1140 		offset = dev->adev->rmmio_remap.bus_addr;
1141 		if (!offset) {
1142 			err = -ENOMEM;
1143 			goto err_unlock;
1144 		}
1145 	}
1146 
1147 	err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1148 		dev->adev, args->va_addr, args->size,
1149 		pdd->drm_priv, (struct kgd_mem **) &mem, &offset,
1150 		flags, false);
1151 
1152 	if (err)
1153 		goto err_unlock;
1154 
1155 	idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1156 	if (idr_handle < 0) {
1157 		err = -EFAULT;
1158 		goto err_free;
1159 	}
1160 
1161 	/* Update the VRAM usage count */
1162 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1163 		uint64_t size = args->size;
1164 
1165 		if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM)
1166 			size >>= 1;
1167 		WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + PAGE_ALIGN(size));
1168 	}
1169 
1170 	mutex_unlock(&p->mutex);
1171 
1172 	args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1173 	args->mmap_offset = offset;
1174 
1175 	/* MMIO is mapped through kfd device
1176 	 * Generate a kfd mmap offset
1177 	 */
1178 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1179 		args->mmap_offset = KFD_MMAP_TYPE_MMIO
1180 					| KFD_MMAP_GPU_ID(args->gpu_id);
1181 
1182 	return 0;
1183 
1184 err_free:
1185 	amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem,
1186 					       pdd->drm_priv, NULL);
1187 err_unlock:
1188 err_pdd:
1189 err_large_bar:
1190 	mutex_unlock(&p->mutex);
1191 	return err;
1192 }
1193 
kfd_ioctl_free_memory_of_gpu(struct file * filep,struct kfd_process * p,void * data)1194 static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
1195 					struct kfd_process *p, void *data)
1196 {
1197 	struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1198 	struct kfd_process_device *pdd;
1199 	void *mem;
1200 	int ret;
1201 	uint64_t size = 0;
1202 
1203 	mutex_lock(&p->mutex);
1204 	/*
1205 	 * Safeguard to prevent user space from freeing signal BO.
1206 	 * It will be freed at process termination.
1207 	 */
1208 	if (p->signal_handle && (p->signal_handle == args->handle)) {
1209 		pr_err("Free signal BO is not allowed\n");
1210 		ret = -EPERM;
1211 		goto err_unlock;
1212 	}
1213 
1214 	pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1215 	if (!pdd) {
1216 		pr_err("Process device data doesn't exist\n");
1217 		ret = -EINVAL;
1218 		goto err_pdd;
1219 	}
1220 
1221 	mem = kfd_process_device_translate_handle(
1222 		pdd, GET_IDR_HANDLE(args->handle));
1223 	if (!mem) {
1224 		ret = -EINVAL;
1225 		goto err_unlock;
1226 	}
1227 
1228 	ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev,
1229 				(struct kgd_mem *)mem, pdd->drm_priv, &size);
1230 
1231 	/* If freeing the buffer failed, leave the handle in place for
1232 	 * clean-up during process tear-down.
1233 	 */
1234 	if (!ret)
1235 		kfd_process_device_remove_obj_handle(
1236 			pdd, GET_IDR_HANDLE(args->handle));
1237 
1238 	WRITE_ONCE(pdd->vram_usage, pdd->vram_usage - size);
1239 
1240 err_unlock:
1241 err_pdd:
1242 	mutex_unlock(&p->mutex);
1243 	return ret;
1244 }
1245 
kfd_ioctl_map_memory_to_gpu(struct file * filep,struct kfd_process * p,void * data)1246 static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
1247 					struct kfd_process *p, void *data)
1248 {
1249 	struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1250 	struct kfd_process_device *pdd, *peer_pdd;
1251 	void *mem;
1252 	struct kfd_node *dev;
1253 	long err = 0;
1254 	int i;
1255 	uint32_t *devices_arr = NULL;
1256 
1257 	if (!args->n_devices) {
1258 		pr_debug("Device IDs array empty\n");
1259 		return -EINVAL;
1260 	}
1261 	if (args->n_success > args->n_devices) {
1262 		pr_debug("n_success exceeds n_devices\n");
1263 		return -EINVAL;
1264 	}
1265 
1266 	devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1267 				    GFP_KERNEL);
1268 	if (!devices_arr)
1269 		return -ENOMEM;
1270 
1271 	err = copy_from_user(devices_arr,
1272 			     (void __user *)args->device_ids_array_ptr,
1273 			     args->n_devices * sizeof(*devices_arr));
1274 	if (err != 0) {
1275 		err = -EFAULT;
1276 		goto copy_from_user_failed;
1277 	}
1278 
1279 	mutex_lock(&p->mutex);
1280 	pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1281 	if (!pdd) {
1282 		err = -EINVAL;
1283 		goto get_process_device_data_failed;
1284 	}
1285 	dev = pdd->dev;
1286 
1287 	pdd = kfd_bind_process_to_device(dev, p);
1288 	if (IS_ERR(pdd)) {
1289 		err = PTR_ERR(pdd);
1290 		goto bind_process_to_device_failed;
1291 	}
1292 
1293 	mem = kfd_process_device_translate_handle(pdd,
1294 						GET_IDR_HANDLE(args->handle));
1295 	if (!mem) {
1296 		err = -ENOMEM;
1297 		goto get_mem_obj_from_handle_failed;
1298 	}
1299 
1300 	for (i = args->n_success; i < args->n_devices; i++) {
1301 		peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1302 		if (!peer_pdd) {
1303 			pr_debug("Getting device by id failed for 0x%x\n",
1304 				 devices_arr[i]);
1305 			err = -EINVAL;
1306 			goto get_mem_obj_from_handle_failed;
1307 		}
1308 
1309 		peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p);
1310 		if (IS_ERR(peer_pdd)) {
1311 			err = PTR_ERR(peer_pdd);
1312 			goto get_mem_obj_from_handle_failed;
1313 		}
1314 
1315 		err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1316 			peer_pdd->dev->adev, (struct kgd_mem *)mem,
1317 			peer_pdd->drm_priv);
1318 		if (err) {
1319 			struct pci_dev *pdev = peer_pdd->dev->adev->pdev;
1320 
1321 			dev_err(dev->adev->dev,
1322 			       "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n",
1323 			       pci_domain_nr(pdev->bus),
1324 			       pdev->bus->number,
1325 			       PCI_SLOT(pdev->devfn),
1326 			       PCI_FUNC(pdev->devfn),
1327 			       ((struct kgd_mem *)mem)->domain);
1328 			goto map_memory_to_gpu_failed;
1329 		}
1330 		args->n_success = i+1;
1331 	}
1332 
1333 	err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true);
1334 	if (err) {
1335 		pr_debug("Sync memory failed, wait interrupted by user signal\n");
1336 		goto sync_memory_failed;
1337 	}
1338 
1339 	mutex_unlock(&p->mutex);
1340 
1341 	/* Flush TLBs after waiting for the page table updates to complete */
1342 	for (i = 0; i < args->n_devices; i++) {
1343 		peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1344 		if (WARN_ON_ONCE(!peer_pdd))
1345 			continue;
1346 		kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
1347 	}
1348 	kfree(devices_arr);
1349 
1350 	return err;
1351 
1352 get_process_device_data_failed:
1353 bind_process_to_device_failed:
1354 get_mem_obj_from_handle_failed:
1355 map_memory_to_gpu_failed:
1356 sync_memory_failed:
1357 	mutex_unlock(&p->mutex);
1358 copy_from_user_failed:
1359 	kfree(devices_arr);
1360 
1361 	return err;
1362 }
1363 
kfd_ioctl_unmap_memory_from_gpu(struct file * filep,struct kfd_process * p,void * data)1364 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
1365 					struct kfd_process *p, void *data)
1366 {
1367 	struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1368 	struct kfd_process_device *pdd, *peer_pdd;
1369 	void *mem;
1370 	long err = 0;
1371 	uint32_t *devices_arr = NULL, i;
1372 	bool flush_tlb;
1373 
1374 	if (!args->n_devices) {
1375 		pr_debug("Device IDs array empty\n");
1376 		return -EINVAL;
1377 	}
1378 	if (args->n_success > args->n_devices) {
1379 		pr_debug("n_success exceeds n_devices\n");
1380 		return -EINVAL;
1381 	}
1382 
1383 	devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1384 				    GFP_KERNEL);
1385 	if (!devices_arr)
1386 		return -ENOMEM;
1387 
1388 	err = copy_from_user(devices_arr,
1389 			     (void __user *)args->device_ids_array_ptr,
1390 			     args->n_devices * sizeof(*devices_arr));
1391 	if (err != 0) {
1392 		err = -EFAULT;
1393 		goto copy_from_user_failed;
1394 	}
1395 
1396 	mutex_lock(&p->mutex);
1397 	pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1398 	if (!pdd) {
1399 		err = -EINVAL;
1400 		goto bind_process_to_device_failed;
1401 	}
1402 
1403 	mem = kfd_process_device_translate_handle(pdd,
1404 						GET_IDR_HANDLE(args->handle));
1405 	if (!mem) {
1406 		err = -ENOMEM;
1407 		goto get_mem_obj_from_handle_failed;
1408 	}
1409 
1410 	for (i = args->n_success; i < args->n_devices; i++) {
1411 		peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1412 		if (!peer_pdd) {
1413 			err = -EINVAL;
1414 			goto get_mem_obj_from_handle_failed;
1415 		}
1416 		err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1417 			peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv);
1418 		if (err) {
1419 			pr_err("Failed to unmap from gpu %d/%d\n",
1420 			       i, args->n_devices);
1421 			goto unmap_memory_from_gpu_failed;
1422 		}
1423 		args->n_success = i+1;
1424 	}
1425 
1426 	flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev->kfd);
1427 	if (flush_tlb) {
1428 		err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev,
1429 				(struct kgd_mem *) mem, true);
1430 		if (err) {
1431 			pr_debug("Sync memory failed, wait interrupted by user signal\n");
1432 			goto sync_memory_failed;
1433 		}
1434 	}
1435 	mutex_unlock(&p->mutex);
1436 
1437 	if (flush_tlb) {
1438 		/* Flush TLBs after waiting for the page table updates to complete */
1439 		for (i = 0; i < args->n_devices; i++) {
1440 			peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1441 			if (WARN_ON_ONCE(!peer_pdd))
1442 				continue;
1443 			kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
1444 		}
1445 	}
1446 	kfree(devices_arr);
1447 
1448 	return 0;
1449 
1450 bind_process_to_device_failed:
1451 get_mem_obj_from_handle_failed:
1452 unmap_memory_from_gpu_failed:
1453 sync_memory_failed:
1454 	mutex_unlock(&p->mutex);
1455 copy_from_user_failed:
1456 	kfree(devices_arr);
1457 	return err;
1458 }
1459 
kfd_ioctl_alloc_queue_gws(struct file * filep,struct kfd_process * p,void * data)1460 static int kfd_ioctl_alloc_queue_gws(struct file *filep,
1461 		struct kfd_process *p, void *data)
1462 {
1463 	int retval;
1464 	struct kfd_ioctl_alloc_queue_gws_args *args = data;
1465 	struct queue *q;
1466 	struct kfd_node *dev;
1467 
1468 	mutex_lock(&p->mutex);
1469 	q = pqm_get_user_queue(&p->pqm, args->queue_id);
1470 
1471 	if (q) {
1472 		dev = q->device;
1473 	} else {
1474 		retval = -EINVAL;
1475 		goto out_unlock;
1476 	}
1477 
1478 	if (!dev->gws) {
1479 		retval = -ENODEV;
1480 		goto out_unlock;
1481 	}
1482 
1483 	if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
1484 		retval = -ENODEV;
1485 		goto out_unlock;
1486 	}
1487 
1488 	if (p->debug_trap_enabled && (!kfd_dbg_has_gws_support(dev) ||
1489 				      kfd_dbg_has_cwsr_workaround(dev))) {
1490 		retval = -EBUSY;
1491 		goto out_unlock;
1492 	}
1493 
1494 	retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1495 	mutex_unlock(&p->mutex);
1496 
1497 	args->first_gws = 0;
1498 	return retval;
1499 
1500 out_unlock:
1501 	mutex_unlock(&p->mutex);
1502 	return retval;
1503 }
1504 
kfd_ioctl_get_dmabuf_info(struct file * filep,struct kfd_process * p,void * data)1505 static int kfd_ioctl_get_dmabuf_info(struct file *filep,
1506 		struct kfd_process *p, void *data)
1507 {
1508 	struct kfd_ioctl_get_dmabuf_info_args *args = data;
1509 	struct kfd_node *dev = NULL;
1510 	struct amdgpu_device *dmabuf_adev;
1511 	void *metadata_buffer = NULL;
1512 	uint32_t flags;
1513 	int8_t xcp_id;
1514 	unsigned int i;
1515 	int r;
1516 
1517 	/* Find a KFD GPU device that supports the get_dmabuf_info query */
1518 	for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++)
1519 		if (dev)
1520 			break;
1521 	if (!dev)
1522 		return -EINVAL;
1523 
1524 	if (args->metadata_ptr) {
1525 		metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL);
1526 		if (!metadata_buffer)
1527 			return -ENOMEM;
1528 	}
1529 
1530 	/* Get dmabuf info from KGD */
1531 	r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd,
1532 					  &dmabuf_adev, &args->size,
1533 					  metadata_buffer, args->metadata_size,
1534 					  &args->metadata_size, &flags, &xcp_id);
1535 	if (r)
1536 		goto exit;
1537 
1538 	if (xcp_id >= 0)
1539 		args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id;
1540 	else
1541 		args->gpu_id = dmabuf_adev->kfd.dev->nodes[0]->id;
1542 	args->flags = flags;
1543 
1544 	/* Copy metadata buffer to user mode */
1545 	if (metadata_buffer) {
1546 		r = copy_to_user((void __user *)args->metadata_ptr,
1547 				 metadata_buffer, args->metadata_size);
1548 		if (r != 0)
1549 			r = -EFAULT;
1550 	}
1551 
1552 exit:
1553 	kfree(metadata_buffer);
1554 
1555 	return r;
1556 }
1557 
kfd_ioctl_import_dmabuf(struct file * filep,struct kfd_process * p,void * data)1558 static int kfd_ioctl_import_dmabuf(struct file *filep,
1559 				   struct kfd_process *p, void *data)
1560 {
1561 	struct kfd_ioctl_import_dmabuf_args *args = data;
1562 	struct kfd_process_device *pdd;
1563 	struct dma_buf *dmabuf;
1564 	int idr_handle;
1565 	uint64_t size;
1566 	void *mem;
1567 	int r;
1568 
1569 	dmabuf = dma_buf_get(args->dmabuf_fd);
1570 	if (IS_ERR(dmabuf))
1571 		return PTR_ERR(dmabuf);
1572 
1573 	mutex_lock(&p->mutex);
1574 	pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1575 	if (!pdd) {
1576 		r = -EINVAL;
1577 		goto err_unlock;
1578 	}
1579 
1580 	pdd = kfd_bind_process_to_device(pdd->dev, p);
1581 	if (IS_ERR(pdd)) {
1582 		r = PTR_ERR(pdd);
1583 		goto err_unlock;
1584 	}
1585 
1586 	r = amdgpu_amdkfd_gpuvm_import_dmabuf(pdd->dev->adev, dmabuf,
1587 					      args->va_addr, pdd->drm_priv,
1588 					      (struct kgd_mem **)&mem, &size,
1589 					      NULL);
1590 	if (r)
1591 		goto err_unlock;
1592 
1593 	idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1594 	if (idr_handle < 0) {
1595 		r = -EFAULT;
1596 		goto err_free;
1597 	}
1598 
1599 	mutex_unlock(&p->mutex);
1600 	dma_buf_put(dmabuf);
1601 
1602 	args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1603 
1604 	return 0;
1605 
1606 err_free:
1607 	amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem,
1608 					       pdd->drm_priv, NULL);
1609 err_unlock:
1610 	mutex_unlock(&p->mutex);
1611 	dma_buf_put(dmabuf);
1612 	return r;
1613 }
1614 
kfd_ioctl_export_dmabuf(struct file * filep,struct kfd_process * p,void * data)1615 static int kfd_ioctl_export_dmabuf(struct file *filep,
1616 				   struct kfd_process *p, void *data)
1617 {
1618 	struct kfd_ioctl_export_dmabuf_args *args = data;
1619 	struct kfd_process_device *pdd;
1620 	struct dma_buf *dmabuf;
1621 	struct kfd_node *dev;
1622 	void *mem;
1623 	int ret = 0;
1624 
1625 	dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1626 	if (!dev)
1627 		return -EINVAL;
1628 
1629 	mutex_lock(&p->mutex);
1630 
1631 	pdd = kfd_get_process_device_data(dev, p);
1632 	if (!pdd) {
1633 		ret = -EINVAL;
1634 		goto err_unlock;
1635 	}
1636 
1637 	mem = kfd_process_device_translate_handle(pdd,
1638 						GET_IDR_HANDLE(args->handle));
1639 	if (!mem) {
1640 		ret = -EINVAL;
1641 		goto err_unlock;
1642 	}
1643 
1644 	ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf);
1645 	mutex_unlock(&p->mutex);
1646 	if (ret)
1647 		goto err_out;
1648 
1649 	ret = dma_buf_fd(dmabuf, args->flags);
1650 	if (ret < 0) {
1651 		dma_buf_put(dmabuf);
1652 		goto err_out;
1653 	}
1654 	/* dma_buf_fd assigns the reference count to the fd, no need to
1655 	 * put the reference here.
1656 	 */
1657 	args->dmabuf_fd = ret;
1658 
1659 	return 0;
1660 
1661 err_unlock:
1662 	mutex_unlock(&p->mutex);
1663 err_out:
1664 	return ret;
1665 }
1666 
1667 /* Handle requests for watching SMI events */
kfd_ioctl_smi_events(struct file * filep,struct kfd_process * p,void * data)1668 static int kfd_ioctl_smi_events(struct file *filep,
1669 				struct kfd_process *p, void *data)
1670 {
1671 	struct kfd_ioctl_smi_events_args *args = data;
1672 	struct kfd_process_device *pdd;
1673 
1674 	mutex_lock(&p->mutex);
1675 
1676 	pdd = kfd_process_device_data_by_id(p, args->gpuid);
1677 	mutex_unlock(&p->mutex);
1678 	if (!pdd)
1679 		return -EINVAL;
1680 
1681 	return kfd_smi_event_open(pdd->dev, &args->anon_fd);
1682 }
1683 
1684 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1685 
kfd_ioctl_set_xnack_mode(struct file * filep,struct kfd_process * p,void * data)1686 static int kfd_ioctl_set_xnack_mode(struct file *filep,
1687 				    struct kfd_process *p, void *data)
1688 {
1689 	struct kfd_ioctl_set_xnack_mode_args *args = data;
1690 	int r = 0;
1691 
1692 	mutex_lock(&p->mutex);
1693 	if (args->xnack_enabled >= 0) {
1694 		if (!list_empty(&p->pqm.queues)) {
1695 			pr_debug("Process has user queues running\n");
1696 			r = -EBUSY;
1697 			goto out_unlock;
1698 		}
1699 
1700 		if (p->xnack_enabled == args->xnack_enabled)
1701 			goto out_unlock;
1702 
1703 		if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) {
1704 			r = -EPERM;
1705 			goto out_unlock;
1706 		}
1707 
1708 		r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled);
1709 	} else {
1710 		args->xnack_enabled = p->xnack_enabled;
1711 	}
1712 
1713 out_unlock:
1714 	mutex_unlock(&p->mutex);
1715 
1716 	return r;
1717 }
1718 
kfd_ioctl_svm(struct file * filep,struct kfd_process * p,void * data)1719 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1720 {
1721 	struct kfd_ioctl_svm_args *args = data;
1722 	int r = 0;
1723 
1724 	pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n",
1725 		 args->start_addr, args->size, args->op, args->nattr);
1726 
1727 	if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK))
1728 		return -EINVAL;
1729 	if (!args->start_addr || !args->size)
1730 		return -EINVAL;
1731 
1732 	r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr,
1733 		      args->attrs);
1734 
1735 	return r;
1736 }
1737 #else
kfd_ioctl_set_xnack_mode(struct file * filep,struct kfd_process * p,void * data)1738 static int kfd_ioctl_set_xnack_mode(struct file *filep,
1739 				    struct kfd_process *p, void *data)
1740 {
1741 	return -EPERM;
1742 }
kfd_ioctl_svm(struct file * filep,struct kfd_process * p,void * data)1743 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1744 {
1745 	return -EPERM;
1746 }
1747 #endif
1748 
criu_checkpoint_process(struct kfd_process * p,uint8_t __user * user_priv_data,uint64_t * priv_offset)1749 static int criu_checkpoint_process(struct kfd_process *p,
1750 			     uint8_t __user *user_priv_data,
1751 			     uint64_t *priv_offset)
1752 {
1753 	struct kfd_criu_process_priv_data process_priv;
1754 	int ret;
1755 
1756 	memset(&process_priv, 0, sizeof(process_priv));
1757 
1758 	process_priv.version = KFD_CRIU_PRIV_VERSION;
1759 	/* For CR, we don't consider negative xnack mode which is used for
1760 	 * querying without changing it, here 0 simply means disabled and 1
1761 	 * means enabled so retry for finding a valid PTE.
1762 	 */
1763 	process_priv.xnack_mode = p->xnack_enabled ? 1 : 0;
1764 
1765 	ret = copy_to_user(user_priv_data + *priv_offset,
1766 				&process_priv, sizeof(process_priv));
1767 
1768 	if (ret) {
1769 		pr_err("Failed to copy process information to user\n");
1770 		ret = -EFAULT;
1771 	}
1772 
1773 	*priv_offset += sizeof(process_priv);
1774 	return ret;
1775 }
1776 
criu_checkpoint_devices(struct kfd_process * p,uint32_t num_devices,uint8_t __user * user_addr,uint8_t __user * user_priv_data,uint64_t * priv_offset)1777 static int criu_checkpoint_devices(struct kfd_process *p,
1778 			     uint32_t num_devices,
1779 			     uint8_t __user *user_addr,
1780 			     uint8_t __user *user_priv_data,
1781 			     uint64_t *priv_offset)
1782 {
1783 	struct kfd_criu_device_priv_data *device_priv = NULL;
1784 	struct kfd_criu_device_bucket *device_buckets = NULL;
1785 	int ret = 0, i;
1786 
1787 	device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL);
1788 	if (!device_buckets) {
1789 		ret = -ENOMEM;
1790 		goto exit;
1791 	}
1792 
1793 	device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL);
1794 	if (!device_priv) {
1795 		ret = -ENOMEM;
1796 		goto exit;
1797 	}
1798 
1799 	for (i = 0; i < num_devices; i++) {
1800 		struct kfd_process_device *pdd = p->pdds[i];
1801 
1802 		device_buckets[i].user_gpu_id = pdd->user_gpu_id;
1803 		device_buckets[i].actual_gpu_id = pdd->dev->id;
1804 
1805 		/*
1806 		 * priv_data does not contain useful information for now and is reserved for
1807 		 * future use, so we do not set its contents.
1808 		 */
1809 	}
1810 
1811 	ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets));
1812 	if (ret) {
1813 		pr_err("Failed to copy device information to user\n");
1814 		ret = -EFAULT;
1815 		goto exit;
1816 	}
1817 
1818 	ret = copy_to_user(user_priv_data + *priv_offset,
1819 			   device_priv,
1820 			   num_devices * sizeof(*device_priv));
1821 	if (ret) {
1822 		pr_err("Failed to copy device information to user\n");
1823 		ret = -EFAULT;
1824 	}
1825 	*priv_offset += num_devices * sizeof(*device_priv);
1826 
1827 exit:
1828 	kvfree(device_buckets);
1829 	kvfree(device_priv);
1830 	return ret;
1831 }
1832 
get_process_num_bos(struct kfd_process * p)1833 static uint32_t get_process_num_bos(struct kfd_process *p)
1834 {
1835 	uint32_t num_of_bos = 0;
1836 	int i;
1837 
1838 	/* Run over all PDDs of the process */
1839 	for (i = 0; i < p->n_pdds; i++) {
1840 		struct kfd_process_device *pdd = p->pdds[i];
1841 		void *mem;
1842 		int id;
1843 
1844 		idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1845 			struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
1846 
1847 			if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base)
1848 				num_of_bos++;
1849 		}
1850 	}
1851 	return num_of_bos;
1852 }
1853 
criu_get_prime_handle(struct kgd_mem * mem,int flags,u32 * shared_fd)1854 static int criu_get_prime_handle(struct kgd_mem *mem, int flags,
1855 				      u32 *shared_fd)
1856 {
1857 	struct dma_buf *dmabuf;
1858 	int ret;
1859 
1860 	ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf);
1861 	if (ret) {
1862 		pr_err("dmabuf export failed for the BO\n");
1863 		return ret;
1864 	}
1865 
1866 	ret = dma_buf_fd(dmabuf, flags);
1867 	if (ret < 0) {
1868 		pr_err("dmabuf create fd failed, ret:%d\n", ret);
1869 		goto out_free_dmabuf;
1870 	}
1871 
1872 	*shared_fd = ret;
1873 	return 0;
1874 
1875 out_free_dmabuf:
1876 	dma_buf_put(dmabuf);
1877 	return ret;
1878 }
1879 
criu_checkpoint_bos(struct kfd_process * p,uint32_t num_bos,uint8_t __user * user_bos,uint8_t __user * user_priv_data,uint64_t * priv_offset)1880 static int criu_checkpoint_bos(struct kfd_process *p,
1881 			       uint32_t num_bos,
1882 			       uint8_t __user *user_bos,
1883 			       uint8_t __user *user_priv_data,
1884 			       uint64_t *priv_offset)
1885 {
1886 	struct kfd_criu_bo_bucket *bo_buckets;
1887 	struct kfd_criu_bo_priv_data *bo_privs;
1888 	int ret = 0, pdd_index, bo_index = 0, id;
1889 	void *mem;
1890 
1891 	bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL);
1892 	if (!bo_buckets)
1893 		return -ENOMEM;
1894 
1895 	bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL);
1896 	if (!bo_privs) {
1897 		ret = -ENOMEM;
1898 		goto exit;
1899 	}
1900 
1901 	for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
1902 		struct kfd_process_device *pdd = p->pdds[pdd_index];
1903 		struct amdgpu_bo *dumper_bo;
1904 		struct kgd_mem *kgd_mem;
1905 
1906 		idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1907 			struct kfd_criu_bo_bucket *bo_bucket;
1908 			struct kfd_criu_bo_priv_data *bo_priv;
1909 			int i, dev_idx = 0;
1910 
1911 			if (!mem) {
1912 				ret = -ENOMEM;
1913 				goto exit;
1914 			}
1915 
1916 			kgd_mem = (struct kgd_mem *)mem;
1917 			dumper_bo = kgd_mem->bo;
1918 
1919 			/* Skip checkpointing BOs that are used for Trap handler
1920 			 * code and state. Currently, these BOs have a VA that
1921 			 * is less GPUVM Base
1922 			 */
1923 			if (kgd_mem->va && kgd_mem->va <= pdd->gpuvm_base)
1924 				continue;
1925 
1926 			bo_bucket = &bo_buckets[bo_index];
1927 			bo_priv = &bo_privs[bo_index];
1928 
1929 			bo_bucket->gpu_id = pdd->user_gpu_id;
1930 			bo_bucket->addr = (uint64_t)kgd_mem->va;
1931 			bo_bucket->size = amdgpu_bo_size(dumper_bo);
1932 			bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags;
1933 			bo_priv->idr_handle = id;
1934 
1935 			if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1936 				ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo,
1937 								&bo_priv->user_addr);
1938 				if (ret) {
1939 					pr_err("Failed to obtain user address for user-pointer bo\n");
1940 					goto exit;
1941 				}
1942 			}
1943 			if (bo_bucket->alloc_flags
1944 			    & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
1945 				ret = criu_get_prime_handle(kgd_mem,
1946 						bo_bucket->alloc_flags &
1947 						KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0,
1948 						&bo_bucket->dmabuf_fd);
1949 				if (ret)
1950 					goto exit;
1951 			} else {
1952 				bo_bucket->dmabuf_fd = KFD_INVALID_FD;
1953 			}
1954 
1955 			if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
1956 				bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL |
1957 					KFD_MMAP_GPU_ID(pdd->dev->id);
1958 			else if (bo_bucket->alloc_flags &
1959 				KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1960 				bo_bucket->offset = KFD_MMAP_TYPE_MMIO |
1961 					KFD_MMAP_GPU_ID(pdd->dev->id);
1962 			else
1963 				bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo);
1964 
1965 			for (i = 0; i < p->n_pdds; i++) {
1966 				if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->dev->adev, kgd_mem))
1967 					bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id;
1968 			}
1969 
1970 			pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n"
1971 					"gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x",
1972 					bo_bucket->size,
1973 					bo_bucket->addr,
1974 					bo_bucket->offset,
1975 					bo_bucket->gpu_id,
1976 					bo_bucket->alloc_flags,
1977 					bo_priv->idr_handle);
1978 			bo_index++;
1979 		}
1980 	}
1981 
1982 	ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets));
1983 	if (ret) {
1984 		pr_err("Failed to copy BO information to user\n");
1985 		ret = -EFAULT;
1986 		goto exit;
1987 	}
1988 
1989 	ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs));
1990 	if (ret) {
1991 		pr_err("Failed to copy BO priv information to user\n");
1992 		ret = -EFAULT;
1993 		goto exit;
1994 	}
1995 
1996 	*priv_offset += num_bos * sizeof(*bo_privs);
1997 
1998 exit:
1999 	while (ret && bo_index--) {
2000 		if (bo_buckets[bo_index].alloc_flags
2001 		    & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
2002 			close_fd(bo_buckets[bo_index].dmabuf_fd);
2003 	}
2004 
2005 	kvfree(bo_buckets);
2006 	kvfree(bo_privs);
2007 	return ret;
2008 }
2009 
criu_get_process_object_info(struct kfd_process * p,uint32_t * num_devices,uint32_t * num_bos,uint32_t * num_objects,uint64_t * objs_priv_size)2010 static int criu_get_process_object_info(struct kfd_process *p,
2011 					uint32_t *num_devices,
2012 					uint32_t *num_bos,
2013 					uint32_t *num_objects,
2014 					uint64_t *objs_priv_size)
2015 {
2016 	uint64_t queues_priv_data_size, svm_priv_data_size, priv_size;
2017 	uint32_t num_queues, num_events, num_svm_ranges;
2018 	int ret;
2019 
2020 	*num_devices = p->n_pdds;
2021 	*num_bos = get_process_num_bos(p);
2022 
2023 	ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size);
2024 	if (ret)
2025 		return ret;
2026 
2027 	num_events = kfd_get_num_events(p);
2028 
2029 	ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size);
2030 	if (ret)
2031 		return ret;
2032 
2033 	*num_objects = num_queues + num_events + num_svm_ranges;
2034 
2035 	if (objs_priv_size) {
2036 		priv_size = sizeof(struct kfd_criu_process_priv_data);
2037 		priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data);
2038 		priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data);
2039 		priv_size += queues_priv_data_size;
2040 		priv_size += num_events * sizeof(struct kfd_criu_event_priv_data);
2041 		priv_size += svm_priv_data_size;
2042 		*objs_priv_size = priv_size;
2043 	}
2044 	return 0;
2045 }
2046 
criu_checkpoint(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args)2047 static int criu_checkpoint(struct file *filep,
2048 			   struct kfd_process *p,
2049 			   struct kfd_ioctl_criu_args *args)
2050 {
2051 	int ret;
2052 	uint32_t num_devices, num_bos, num_objects;
2053 	uint64_t priv_size, priv_offset = 0, bo_priv_offset;
2054 
2055 	if (!args->devices || !args->bos || !args->priv_data)
2056 		return -EINVAL;
2057 
2058 	mutex_lock(&p->mutex);
2059 
2060 	if (!p->n_pdds) {
2061 		pr_err("No pdd for given process\n");
2062 		ret = -ENODEV;
2063 		goto exit_unlock;
2064 	}
2065 
2066 	/* Confirm all process queues are evicted */
2067 	if (!p->queues_paused) {
2068 		pr_err("Cannot dump process when queues are not in evicted state\n");
2069 		/* CRIU plugin did not call op PROCESS_INFO before checkpointing */
2070 		ret = -EINVAL;
2071 		goto exit_unlock;
2072 	}
2073 
2074 	ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size);
2075 	if (ret)
2076 		goto exit_unlock;
2077 
2078 	if (num_devices != args->num_devices ||
2079 	    num_bos != args->num_bos ||
2080 	    num_objects != args->num_objects ||
2081 	    priv_size != args->priv_data_size) {
2082 
2083 		ret = -EINVAL;
2084 		goto exit_unlock;
2085 	}
2086 
2087 	/* each function will store private data inside priv_data and adjust priv_offset */
2088 	ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset);
2089 	if (ret)
2090 		goto exit_unlock;
2091 
2092 	ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices,
2093 				(uint8_t __user *)args->priv_data, &priv_offset);
2094 	if (ret)
2095 		goto exit_unlock;
2096 
2097 	/* Leave room for BOs in the private data. They need to be restored
2098 	 * before events, but we checkpoint them last to simplify the error
2099 	 * handling.
2100 	 */
2101 	bo_priv_offset = priv_offset;
2102 	priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data);
2103 
2104 	if (num_objects) {
2105 		ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,
2106 						 &priv_offset);
2107 		if (ret)
2108 			goto exit_unlock;
2109 
2110 		ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,
2111 						 &priv_offset);
2112 		if (ret)
2113 			goto exit_unlock;
2114 
2115 		ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);
2116 		if (ret)
2117 			goto exit_unlock;
2118 	}
2119 
2120 	/* This must be the last thing in this function that can fail.
2121 	 * Otherwise we leak dmabuf file descriptors.
2122 	 */
2123 	ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
2124 			   (uint8_t __user *)args->priv_data, &bo_priv_offset);
2125 
2126 exit_unlock:
2127 	mutex_unlock(&p->mutex);
2128 	if (ret)
2129 		pr_err("Failed to dump CRIU ret:%d\n", ret);
2130 	else
2131 		pr_debug("CRIU dump ret:%d\n", ret);
2132 
2133 	return ret;
2134 }
2135 
criu_restore_process(struct kfd_process * p,struct kfd_ioctl_criu_args * args,uint64_t * priv_offset,uint64_t max_priv_data_size)2136 static int criu_restore_process(struct kfd_process *p,
2137 				struct kfd_ioctl_criu_args *args,
2138 				uint64_t *priv_offset,
2139 				uint64_t max_priv_data_size)
2140 {
2141 	int ret = 0;
2142 	struct kfd_criu_process_priv_data process_priv;
2143 
2144 	if (*priv_offset + sizeof(process_priv) > max_priv_data_size)
2145 		return -EINVAL;
2146 
2147 	ret = copy_from_user(&process_priv,
2148 				(void __user *)(args->priv_data + *priv_offset),
2149 				sizeof(process_priv));
2150 	if (ret) {
2151 		pr_err("Failed to copy process private information from user\n");
2152 		ret = -EFAULT;
2153 		goto exit;
2154 	}
2155 	*priv_offset += sizeof(process_priv);
2156 
2157 	if (process_priv.version != KFD_CRIU_PRIV_VERSION) {
2158 		pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n",
2159 			process_priv.version, KFD_CRIU_PRIV_VERSION);
2160 		return -EINVAL;
2161 	}
2162 
2163 	pr_debug("Setting XNACK mode\n");
2164 	if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) {
2165 		pr_err("xnack mode cannot be set\n");
2166 		ret = -EPERM;
2167 		goto exit;
2168 	} else {
2169 		pr_debug("set xnack mode: %d\n", process_priv.xnack_mode);
2170 		p->xnack_enabled = process_priv.xnack_mode;
2171 	}
2172 
2173 exit:
2174 	return ret;
2175 }
2176 
criu_restore_devices(struct kfd_process * p,struct kfd_ioctl_criu_args * args,uint64_t * priv_offset,uint64_t max_priv_data_size)2177 static int criu_restore_devices(struct kfd_process *p,
2178 				struct kfd_ioctl_criu_args *args,
2179 				uint64_t *priv_offset,
2180 				uint64_t max_priv_data_size)
2181 {
2182 	struct kfd_criu_device_bucket *device_buckets;
2183 	struct kfd_criu_device_priv_data *device_privs;
2184 	int ret = 0;
2185 	uint32_t i;
2186 
2187 	if (args->num_devices != p->n_pdds)
2188 		return -EINVAL;
2189 
2190 	if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size)
2191 		return -EINVAL;
2192 
2193 	device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL);
2194 	if (!device_buckets)
2195 		return -ENOMEM;
2196 
2197 	ret = copy_from_user(device_buckets, (void __user *)args->devices,
2198 				args->num_devices * sizeof(*device_buckets));
2199 	if (ret) {
2200 		pr_err("Failed to copy devices buckets from user\n");
2201 		ret = -EFAULT;
2202 		goto exit;
2203 	}
2204 
2205 	for (i = 0; i < args->num_devices; i++) {
2206 		struct kfd_node *dev;
2207 		struct kfd_process_device *pdd;
2208 		struct file *drm_file;
2209 
2210 		/* device private data is not currently used */
2211 
2212 		if (!device_buckets[i].user_gpu_id) {
2213 			pr_err("Invalid user gpu_id\n");
2214 			ret = -EINVAL;
2215 			goto exit;
2216 		}
2217 
2218 		dev = kfd_device_by_id(device_buckets[i].actual_gpu_id);
2219 		if (!dev) {
2220 			pr_err("Failed to find device with gpu_id = %x\n",
2221 				device_buckets[i].actual_gpu_id);
2222 			ret = -EINVAL;
2223 			goto exit;
2224 		}
2225 
2226 		pdd = kfd_get_process_device_data(dev, p);
2227 		if (!pdd) {
2228 			pr_err("Failed to get pdd for gpu_id = %x\n",
2229 					device_buckets[i].actual_gpu_id);
2230 			ret = -EINVAL;
2231 			goto exit;
2232 		}
2233 		pdd->user_gpu_id = device_buckets[i].user_gpu_id;
2234 
2235 		drm_file = fget(device_buckets[i].drm_fd);
2236 		if (!drm_file) {
2237 			pr_err("Invalid render node file descriptor sent from plugin (%d)\n",
2238 				device_buckets[i].drm_fd);
2239 			ret = -EINVAL;
2240 			goto exit;
2241 		}
2242 
2243 		if (pdd->drm_file) {
2244 			ret = -EINVAL;
2245 			goto exit;
2246 		}
2247 
2248 		/* create the vm using render nodes for kfd pdd */
2249 		if (kfd_process_device_init_vm(pdd, drm_file)) {
2250 			pr_err("could not init vm for given pdd\n");
2251 			/* On success, the PDD keeps the drm_file reference */
2252 			fput(drm_file);
2253 			ret = -EINVAL;
2254 			goto exit;
2255 		}
2256 		/*
2257 		 * pdd now already has the vm bound to render node so below api won't create a new
2258 		 * exclusive kfd mapping but use existing one with renderDXXX but is still needed
2259 		 * for iommu v2 binding  and runtime pm.
2260 		 */
2261 		pdd = kfd_bind_process_to_device(dev, p);
2262 		if (IS_ERR(pdd)) {
2263 			ret = PTR_ERR(pdd);
2264 			goto exit;
2265 		}
2266 
2267 		if (!pdd->qpd.proc_doorbells) {
2268 			ret = kfd_alloc_process_doorbells(dev->kfd, pdd);
2269 			if (ret)
2270 				goto exit;
2271 		}
2272 	}
2273 
2274 	/*
2275 	 * We are not copying device private data from user as we are not using the data for now,
2276 	 * but we still adjust for its private data.
2277 	 */
2278 	*priv_offset += args->num_devices * sizeof(*device_privs);
2279 
2280 exit:
2281 	kfree(device_buckets);
2282 	return ret;
2283 }
2284 
criu_restore_memory_of_gpu(struct kfd_process_device * pdd,struct kfd_criu_bo_bucket * bo_bucket,struct kfd_criu_bo_priv_data * bo_priv,struct kgd_mem ** kgd_mem)2285 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd,
2286 				      struct kfd_criu_bo_bucket *bo_bucket,
2287 				      struct kfd_criu_bo_priv_data *bo_priv,
2288 				      struct kgd_mem **kgd_mem)
2289 {
2290 	int idr_handle;
2291 	int ret;
2292 	const bool criu_resume = true;
2293 	u64 offset;
2294 
2295 	if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
2296 		if (bo_bucket->size !=
2297 				kfd_doorbell_process_slice(pdd->dev->kfd))
2298 			return -EINVAL;
2299 
2300 		offset = kfd_get_process_doorbells(pdd);
2301 		if (!offset)
2302 			return -ENOMEM;
2303 	} else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2304 		/* MMIO BOs need remapped bus address */
2305 		if (bo_bucket->size != PAGE_SIZE) {
2306 			pr_err("Invalid page size\n");
2307 			return -EINVAL;
2308 		}
2309 		offset = pdd->dev->adev->rmmio_remap.bus_addr;
2310 		if (!offset) {
2311 			pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");
2312 			return -ENOMEM;
2313 		}
2314 	} else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
2315 		offset = bo_priv->user_addr;
2316 	}
2317 	/* Create the BO */
2318 	ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr,
2319 						      bo_bucket->size, pdd->drm_priv, kgd_mem,
2320 						      &offset, bo_bucket->alloc_flags, criu_resume);
2321 	if (ret) {
2322 		pr_err("Could not create the BO\n");
2323 		return ret;
2324 	}
2325 	pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n",
2326 		 bo_bucket->size, bo_bucket->addr, offset);
2327 
2328 	/* Restore previous IDR handle */
2329 	pr_debug("Restoring old IDR handle for the BO");
2330 	idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle,
2331 			       bo_priv->idr_handle + 1, GFP_KERNEL);
2332 
2333 	if (idr_handle < 0) {
2334 		pr_err("Could not allocate idr\n");
2335 		amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv,
2336 						       NULL);
2337 		return -ENOMEM;
2338 	}
2339 
2340 	if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
2341 		bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id);
2342 	if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2343 		bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id);
2344 	} else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
2345 		bo_bucket->restored_offset = offset;
2346 	} else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
2347 		bo_bucket->restored_offset = offset;
2348 		/* Update the VRAM usage count */
2349 		WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size);
2350 	}
2351 	return 0;
2352 }
2353 
criu_restore_bo(struct kfd_process * p,struct kfd_criu_bo_bucket * bo_bucket,struct kfd_criu_bo_priv_data * bo_priv)2354 static int criu_restore_bo(struct kfd_process *p,
2355 			   struct kfd_criu_bo_bucket *bo_bucket,
2356 			   struct kfd_criu_bo_priv_data *bo_priv)
2357 {
2358 	struct kfd_process_device *pdd;
2359 	struct kgd_mem *kgd_mem;
2360 	int ret;
2361 	int j;
2362 
2363 	pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n",
2364 		 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags,
2365 		 bo_priv->idr_handle);
2366 
2367 	pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id);
2368 	if (!pdd) {
2369 		pr_err("Failed to get pdd\n");
2370 		return -ENODEV;
2371 	}
2372 
2373 	ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem);
2374 	if (ret)
2375 		return ret;
2376 
2377 	/* now map these BOs to GPU/s */
2378 	for (j = 0; j < p->n_pdds; j++) {
2379 		struct kfd_node *peer;
2380 		struct kfd_process_device *peer_pdd;
2381 
2382 		if (!bo_priv->mapped_gpuids[j])
2383 			break;
2384 
2385 		peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]);
2386 		if (!peer_pdd)
2387 			return -EINVAL;
2388 
2389 		peer = peer_pdd->dev;
2390 
2391 		peer_pdd = kfd_bind_process_to_device(peer, p);
2392 		if (IS_ERR(peer_pdd))
2393 			return PTR_ERR(peer_pdd);
2394 
2395 		ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem,
2396 							    peer_pdd->drm_priv);
2397 		if (ret) {
2398 			pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds);
2399 			return ret;
2400 		}
2401 	}
2402 
2403 	pr_debug("map memory was successful for the BO\n");
2404 	/* create the dmabuf object and export the bo */
2405 	if (bo_bucket->alloc_flags
2406 	    & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
2407 		ret = criu_get_prime_handle(kgd_mem, DRM_RDWR,
2408 					    &bo_bucket->dmabuf_fd);
2409 		if (ret)
2410 			return ret;
2411 	} else {
2412 		bo_bucket->dmabuf_fd = KFD_INVALID_FD;
2413 	}
2414 
2415 	return 0;
2416 }
2417 
criu_restore_bos(struct kfd_process * p,struct kfd_ioctl_criu_args * args,uint64_t * priv_offset,uint64_t max_priv_data_size)2418 static int criu_restore_bos(struct kfd_process *p,
2419 			    struct kfd_ioctl_criu_args *args,
2420 			    uint64_t *priv_offset,
2421 			    uint64_t max_priv_data_size)
2422 {
2423 	struct kfd_criu_bo_bucket *bo_buckets = NULL;
2424 	struct kfd_criu_bo_priv_data *bo_privs = NULL;
2425 	int ret = 0;
2426 	uint32_t i = 0;
2427 
2428 	if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size)
2429 		return -EINVAL;
2430 
2431 	/* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */
2432 	amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info);
2433 
2434 	bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL);
2435 	if (!bo_buckets)
2436 		return -ENOMEM;
2437 
2438 	ret = copy_from_user(bo_buckets, (void __user *)args->bos,
2439 			     args->num_bos * sizeof(*bo_buckets));
2440 	if (ret) {
2441 		pr_err("Failed to copy BOs information from user\n");
2442 		ret = -EFAULT;
2443 		goto exit;
2444 	}
2445 
2446 	bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL);
2447 	if (!bo_privs) {
2448 		ret = -ENOMEM;
2449 		goto exit;
2450 	}
2451 
2452 	ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset,
2453 			     args->num_bos * sizeof(*bo_privs));
2454 	if (ret) {
2455 		pr_err("Failed to copy BOs information from user\n");
2456 		ret = -EFAULT;
2457 		goto exit;
2458 	}
2459 	*priv_offset += args->num_bos * sizeof(*bo_privs);
2460 
2461 	/* Create and map new BOs */
2462 	for (; i < args->num_bos; i++) {
2463 		ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i]);
2464 		if (ret) {
2465 			pr_debug("Failed to restore BO[%d] ret%d\n", i, ret);
2466 			goto exit;
2467 		}
2468 	} /* done */
2469 
2470 	/* Copy only the buckets back so user can read bo_buckets[N].restored_offset */
2471 	ret = copy_to_user((void __user *)args->bos,
2472 				bo_buckets,
2473 				(args->num_bos * sizeof(*bo_buckets)));
2474 	if (ret)
2475 		ret = -EFAULT;
2476 
2477 exit:
2478 	while (ret && i--) {
2479 		if (bo_buckets[i].alloc_flags
2480 		   & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
2481 			close_fd(bo_buckets[i].dmabuf_fd);
2482 	}
2483 	kvfree(bo_buckets);
2484 	kvfree(bo_privs);
2485 	return ret;
2486 }
2487 
criu_restore_objects(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args,uint64_t * priv_offset,uint64_t max_priv_data_size)2488 static int criu_restore_objects(struct file *filep,
2489 				struct kfd_process *p,
2490 				struct kfd_ioctl_criu_args *args,
2491 				uint64_t *priv_offset,
2492 				uint64_t max_priv_data_size)
2493 {
2494 	int ret = 0;
2495 	uint32_t i;
2496 
2497 	BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type));
2498 	BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type));
2499 	BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type));
2500 
2501 	for (i = 0; i < args->num_objects; i++) {
2502 		uint32_t object_type;
2503 
2504 		if (*priv_offset + sizeof(object_type) > max_priv_data_size) {
2505 			pr_err("Invalid private data size\n");
2506 			return -EINVAL;
2507 		}
2508 
2509 		ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset));
2510 		if (ret) {
2511 			pr_err("Failed to copy private information from user\n");
2512 			goto exit;
2513 		}
2514 
2515 		switch (object_type) {
2516 		case KFD_CRIU_OBJECT_TYPE_QUEUE:
2517 			ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data,
2518 						     priv_offset, max_priv_data_size);
2519 			if (ret)
2520 				goto exit;
2521 			break;
2522 		case KFD_CRIU_OBJECT_TYPE_EVENT:
2523 			ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data,
2524 						     priv_offset, max_priv_data_size);
2525 			if (ret)
2526 				goto exit;
2527 			break;
2528 		case KFD_CRIU_OBJECT_TYPE_SVM_RANGE:
2529 			ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data,
2530 						     priv_offset, max_priv_data_size);
2531 			if (ret)
2532 				goto exit;
2533 			break;
2534 		default:
2535 			pr_err("Invalid object type:%u at index:%d\n", object_type, i);
2536 			ret = -EINVAL;
2537 			goto exit;
2538 		}
2539 	}
2540 exit:
2541 	return ret;
2542 }
2543 
criu_restore(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args)2544 static int criu_restore(struct file *filep,
2545 			struct kfd_process *p,
2546 			struct kfd_ioctl_criu_args *args)
2547 {
2548 	uint64_t priv_offset = 0;
2549 	int ret = 0;
2550 
2551 	pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n",
2552 		 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size);
2553 
2554 	if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size ||
2555 	    !args->num_devices || !args->num_bos)
2556 		return -EINVAL;
2557 
2558 	mutex_lock(&p->mutex);
2559 
2560 	/*
2561 	 * Set the process to evicted state to avoid running any new queues before all the memory
2562 	 * mappings are ready.
2563 	 */
2564 	ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE);
2565 	if (ret)
2566 		goto exit_unlock;
2567 
2568 	/* Each function will adjust priv_offset based on how many bytes they consumed */
2569 	ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size);
2570 	if (ret)
2571 		goto exit_unlock;
2572 
2573 	ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size);
2574 	if (ret)
2575 		goto exit_unlock;
2576 
2577 	ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size);
2578 	if (ret)
2579 		goto exit_unlock;
2580 
2581 	ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size);
2582 	if (ret)
2583 		goto exit_unlock;
2584 
2585 	if (priv_offset != args->priv_data_size) {
2586 		pr_err("Invalid private data size\n");
2587 		ret = -EINVAL;
2588 	}
2589 
2590 exit_unlock:
2591 	mutex_unlock(&p->mutex);
2592 	if (ret)
2593 		pr_err("Failed to restore CRIU ret:%d\n", ret);
2594 	else
2595 		pr_debug("CRIU restore successful\n");
2596 
2597 	return ret;
2598 }
2599 
criu_unpause(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args)2600 static int criu_unpause(struct file *filep,
2601 			struct kfd_process *p,
2602 			struct kfd_ioctl_criu_args *args)
2603 {
2604 	int ret;
2605 
2606 	mutex_lock(&p->mutex);
2607 
2608 	if (!p->queues_paused) {
2609 		mutex_unlock(&p->mutex);
2610 		return -EINVAL;
2611 	}
2612 
2613 	ret = kfd_process_restore_queues(p);
2614 	if (ret)
2615 		pr_err("Failed to unpause queues ret:%d\n", ret);
2616 	else
2617 		p->queues_paused = false;
2618 
2619 	mutex_unlock(&p->mutex);
2620 
2621 	return ret;
2622 }
2623 
criu_resume(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args)2624 static int criu_resume(struct file *filep,
2625 			struct kfd_process *p,
2626 			struct kfd_ioctl_criu_args *args)
2627 {
2628 	struct kfd_process *target = NULL;
2629 	struct pid *pid = NULL;
2630 	int ret = 0;
2631 
2632 	pr_debug("Inside %s, target pid for criu restore: %d\n", __func__,
2633 		 args->pid);
2634 
2635 	pid = find_get_pid(args->pid);
2636 	if (!pid) {
2637 		pr_err("Cannot find pid info for %i\n", args->pid);
2638 		return -ESRCH;
2639 	}
2640 
2641 	pr_debug("calling kfd_lookup_process_by_pid\n");
2642 	target = kfd_lookup_process_by_pid(pid);
2643 
2644 	put_pid(pid);
2645 
2646 	if (!target) {
2647 		pr_debug("Cannot find process info for %i\n", args->pid);
2648 		return -ESRCH;
2649 	}
2650 
2651 	mutex_lock(&target->mutex);
2652 	ret = kfd_criu_resume_svm(target);
2653 	if (ret) {
2654 		pr_err("kfd_criu_resume_svm failed for %i\n", args->pid);
2655 		goto exit;
2656 	}
2657 
2658 	ret =  amdgpu_amdkfd_criu_resume(target->kgd_process_info);
2659 	if (ret)
2660 		pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid);
2661 
2662 exit:
2663 	mutex_unlock(&target->mutex);
2664 
2665 	kfd_unref_process(target);
2666 	return ret;
2667 }
2668 
criu_process_info(struct file * filep,struct kfd_process * p,struct kfd_ioctl_criu_args * args)2669 static int criu_process_info(struct file *filep,
2670 				struct kfd_process *p,
2671 				struct kfd_ioctl_criu_args *args)
2672 {
2673 	int ret = 0;
2674 
2675 	mutex_lock(&p->mutex);
2676 
2677 	if (!p->n_pdds) {
2678 		pr_err("No pdd for given process\n");
2679 		ret = -ENODEV;
2680 		goto err_unlock;
2681 	}
2682 
2683 	ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT);
2684 	if (ret)
2685 		goto err_unlock;
2686 
2687 	p->queues_paused = true;
2688 
2689 	args->pid = task_pid_nr_ns(p->lead_thread,
2690 					task_active_pid_ns(p->lead_thread));
2691 
2692 	ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos,
2693 					   &args->num_objects, &args->priv_data_size);
2694 	if (ret)
2695 		goto err_unlock;
2696 
2697 	dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n",
2698 				args->num_devices, args->num_bos, args->num_objects,
2699 				args->priv_data_size);
2700 
2701 err_unlock:
2702 	if (ret) {
2703 		kfd_process_restore_queues(p);
2704 		p->queues_paused = false;
2705 	}
2706 	mutex_unlock(&p->mutex);
2707 	return ret;
2708 }
2709 
kfd_ioctl_criu(struct file * filep,struct kfd_process * p,void * data)2710 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data)
2711 {
2712 	struct kfd_ioctl_criu_args *args = data;
2713 	int ret;
2714 
2715 	dev_dbg(kfd_device, "CRIU operation: %d\n", args->op);
2716 	switch (args->op) {
2717 	case KFD_CRIU_OP_PROCESS_INFO:
2718 		ret = criu_process_info(filep, p, args);
2719 		break;
2720 	case KFD_CRIU_OP_CHECKPOINT:
2721 		ret = criu_checkpoint(filep, p, args);
2722 		break;
2723 	case KFD_CRIU_OP_UNPAUSE:
2724 		ret = criu_unpause(filep, p, args);
2725 		break;
2726 	case KFD_CRIU_OP_RESTORE:
2727 		ret = criu_restore(filep, p, args);
2728 		break;
2729 	case KFD_CRIU_OP_RESUME:
2730 		ret = criu_resume(filep, p, args);
2731 		break;
2732 	default:
2733 		dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op);
2734 		ret = -EINVAL;
2735 		break;
2736 	}
2737 
2738 	if (ret)
2739 		dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret);
2740 
2741 	return ret;
2742 }
2743 
runtime_enable(struct kfd_process * p,uint64_t r_debug,bool enable_ttmp_setup)2744 static int runtime_enable(struct kfd_process *p, uint64_t r_debug,
2745 			bool enable_ttmp_setup)
2746 {
2747 	int i = 0, ret = 0;
2748 
2749 	if (p->is_runtime_retry)
2750 		goto retry;
2751 
2752 	if (p->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED)
2753 		return -EBUSY;
2754 
2755 	for (i = 0; i < p->n_pdds; i++) {
2756 		struct kfd_process_device *pdd = p->pdds[i];
2757 
2758 		if (pdd->qpd.queue_count)
2759 			return -EEXIST;
2760 
2761 		/*
2762 		 * Setup TTMPs by default.
2763 		 * Note that this call must remain here for MES ADD QUEUE to
2764 		 * skip_process_ctx_clear unconditionally as the first call to
2765 		 * SET_SHADER_DEBUGGER clears any stale process context data
2766 		 * saved in MES.
2767 		 */
2768 		if (pdd->dev->kfd->shared_resources.enable_mes)
2769 			kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev));
2770 	}
2771 
2772 	p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED;
2773 	p->runtime_info.r_debug = r_debug;
2774 	p->runtime_info.ttmp_setup = enable_ttmp_setup;
2775 
2776 	if (p->runtime_info.ttmp_setup) {
2777 		for (i = 0; i < p->n_pdds; i++) {
2778 			struct kfd_process_device *pdd = p->pdds[i];
2779 
2780 			if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) {
2781 				amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
2782 				pdd->dev->kfd2kgd->enable_debug_trap(
2783 						pdd->dev->adev,
2784 						true,
2785 						pdd->dev->vm_info.last_vmid_kfd);
2786 			} else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) {
2787 				pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap(
2788 						pdd->dev->adev,
2789 						false,
2790 						0);
2791 			}
2792 		}
2793 	}
2794 
2795 retry:
2796 	if (p->debug_trap_enabled) {
2797 		if (!p->is_runtime_retry) {
2798 			kfd_dbg_trap_activate(p);
2799 			kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME),
2800 					p, NULL, 0, false, NULL, 0);
2801 		}
2802 
2803 		mutex_unlock(&p->mutex);
2804 		ret = down_interruptible(&p->runtime_enable_sema);
2805 		mutex_lock(&p->mutex);
2806 
2807 		p->is_runtime_retry = !!ret;
2808 	}
2809 
2810 	return ret;
2811 }
2812 
runtime_disable(struct kfd_process * p)2813 static int runtime_disable(struct kfd_process *p)
2814 {
2815 	int i = 0, ret;
2816 	bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED;
2817 
2818 	p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED;
2819 	p->runtime_info.r_debug = 0;
2820 
2821 	if (p->debug_trap_enabled) {
2822 		if (was_enabled)
2823 			kfd_dbg_trap_deactivate(p, false, 0);
2824 
2825 		if (!p->is_runtime_retry)
2826 			kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME),
2827 					p, NULL, 0, false, NULL, 0);
2828 
2829 		mutex_unlock(&p->mutex);
2830 		ret = down_interruptible(&p->runtime_enable_sema);
2831 		mutex_lock(&p->mutex);
2832 
2833 		p->is_runtime_retry = !!ret;
2834 		if (ret)
2835 			return ret;
2836 	}
2837 
2838 	if (was_enabled && p->runtime_info.ttmp_setup) {
2839 		for (i = 0; i < p->n_pdds; i++) {
2840 			struct kfd_process_device *pdd = p->pdds[i];
2841 
2842 			if (!kfd_dbg_is_rlc_restore_supported(pdd->dev))
2843 				amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
2844 		}
2845 	}
2846 
2847 	p->runtime_info.ttmp_setup = false;
2848 
2849 	/* disable ttmp setup */
2850 	for (i = 0; i < p->n_pdds; i++) {
2851 		struct kfd_process_device *pdd = p->pdds[i];
2852 
2853 		if (kfd_dbg_is_per_vmid_supported(pdd->dev)) {
2854 			pdd->spi_dbg_override =
2855 					pdd->dev->kfd2kgd->disable_debug_trap(
2856 					pdd->dev->adev,
2857 					false,
2858 					pdd->dev->vm_info.last_vmid_kfd);
2859 
2860 			if (!pdd->dev->kfd->shared_resources.enable_mes)
2861 				debug_refresh_runlist(pdd->dev->dqm);
2862 			else
2863 				kfd_dbg_set_mes_debug_mode(pdd,
2864 							   !kfd_dbg_has_cwsr_workaround(pdd->dev));
2865 		}
2866 	}
2867 
2868 	return 0;
2869 }
2870 
kfd_ioctl_runtime_enable(struct file * filep,struct kfd_process * p,void * data)2871 static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data)
2872 {
2873 	struct kfd_ioctl_runtime_enable_args *args = data;
2874 	int r;
2875 
2876 	mutex_lock(&p->mutex);
2877 
2878 	if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK)
2879 		r = runtime_enable(p, args->r_debug,
2880 				!!(args->mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK));
2881 	else
2882 		r = runtime_disable(p);
2883 
2884 	mutex_unlock(&p->mutex);
2885 
2886 	return r;
2887 }
2888 
kfd_ioctl_set_debug_trap(struct file * filep,struct kfd_process * p,void * data)2889 static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, void *data)
2890 {
2891 	struct kfd_ioctl_dbg_trap_args *args = data;
2892 	struct task_struct *thread = NULL;
2893 	struct mm_struct *mm = NULL;
2894 	struct pid *pid = NULL;
2895 	struct kfd_process *target = NULL;
2896 	struct kfd_process_device *pdd = NULL;
2897 	int r = 0;
2898 
2899 	if (sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2900 		pr_err("Debugging does not support sched_policy %i", sched_policy);
2901 		return -EINVAL;
2902 	}
2903 
2904 	pid = find_get_pid(args->pid);
2905 	if (!pid) {
2906 		pr_debug("Cannot find pid info for %i\n", args->pid);
2907 		r = -ESRCH;
2908 		goto out;
2909 	}
2910 
2911 	thread = get_pid_task(pid, PIDTYPE_PID);
2912 	if (!thread) {
2913 		r = -ESRCH;
2914 		goto out;
2915 	}
2916 
2917 	mm = get_task_mm(thread);
2918 	if (!mm) {
2919 		r = -ESRCH;
2920 		goto out;
2921 	}
2922 
2923 	if (args->op == KFD_IOC_DBG_TRAP_ENABLE) {
2924 		bool create_process;
2925 
2926 		rcu_read_lock();
2927 		create_process = thread && thread != current && ptrace_parent(thread) == current;
2928 		rcu_read_unlock();
2929 
2930 		target = create_process ? kfd_create_process(thread) :
2931 					kfd_lookup_process_by_pid(pid);
2932 	} else {
2933 		target = kfd_lookup_process_by_pid(pid);
2934 	}
2935 
2936 	if (IS_ERR_OR_NULL(target)) {
2937 		pr_debug("Cannot find process PID %i to debug\n", args->pid);
2938 		r = target ? PTR_ERR(target) : -ESRCH;
2939 		goto out;
2940 	}
2941 
2942 	/* Check if target is still PTRACED. */
2943 	rcu_read_lock();
2944 	if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE
2945 				&& ptrace_parent(target->lead_thread) != current) {
2946 		pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid);
2947 		r = -EPERM;
2948 	}
2949 	rcu_read_unlock();
2950 
2951 	if (r)
2952 		goto out;
2953 
2954 	mutex_lock(&target->mutex);
2955 
2956 	if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) {
2957 		pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op);
2958 		r = -EINVAL;
2959 		goto unlock_out;
2960 	}
2961 
2962 	if (target->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_ENABLED &&
2963 			(args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE ||
2964 			 args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE ||
2965 			 args->op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES ||
2966 			 args->op == KFD_IOC_DBG_TRAP_RESUME_QUEUES ||
2967 			 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2968 			 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH ||
2969 			 args->op == KFD_IOC_DBG_TRAP_SET_FLAGS)) {
2970 		r = -EPERM;
2971 		goto unlock_out;
2972 	}
2973 
2974 	if (args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2975 	    args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH) {
2976 		int user_gpu_id = kfd_process_get_user_gpu_id(target,
2977 				args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ?
2978 					args->set_node_address_watch.gpu_id :
2979 					args->clear_node_address_watch.gpu_id);
2980 
2981 		pdd = kfd_process_device_data_by_id(target, user_gpu_id);
2982 		if (user_gpu_id == -EINVAL || !pdd) {
2983 			r = -ENODEV;
2984 			goto unlock_out;
2985 		}
2986 	}
2987 
2988 	switch (args->op) {
2989 	case KFD_IOC_DBG_TRAP_ENABLE:
2990 		if (target != p)
2991 			target->debugger_process = p;
2992 
2993 		r = kfd_dbg_trap_enable(target,
2994 					args->enable.dbg_fd,
2995 					(void __user *)args->enable.rinfo_ptr,
2996 					&args->enable.rinfo_size);
2997 		if (!r)
2998 			target->exception_enable_mask = args->enable.exception_mask;
2999 
3000 		break;
3001 	case KFD_IOC_DBG_TRAP_DISABLE:
3002 		r = kfd_dbg_trap_disable(target);
3003 		break;
3004 	case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT:
3005 		r = kfd_dbg_send_exception_to_runtime(target,
3006 				args->send_runtime_event.gpu_id,
3007 				args->send_runtime_event.queue_id,
3008 				args->send_runtime_event.exception_mask);
3009 		break;
3010 	case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED:
3011 		kfd_dbg_set_enabled_debug_exception_mask(target,
3012 				args->set_exceptions_enabled.exception_mask);
3013 		break;
3014 	case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
3015 		r = kfd_dbg_trap_set_wave_launch_override(target,
3016 				args->launch_override.override_mode,
3017 				args->launch_override.enable_mask,
3018 				args->launch_override.support_request_mask,
3019 				&args->launch_override.enable_mask,
3020 				&args->launch_override.support_request_mask);
3021 		break;
3022 	case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE:
3023 		r = kfd_dbg_trap_set_wave_launch_mode(target,
3024 				args->launch_mode.launch_mode);
3025 		break;
3026 	case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES:
3027 		r = suspend_queues(target,
3028 				args->suspend_queues.num_queues,
3029 				args->suspend_queues.grace_period,
3030 				args->suspend_queues.exception_mask,
3031 				(uint32_t *)args->suspend_queues.queue_array_ptr);
3032 
3033 		break;
3034 	case KFD_IOC_DBG_TRAP_RESUME_QUEUES:
3035 		r = resume_queues(target, args->resume_queues.num_queues,
3036 				(uint32_t *)args->resume_queues.queue_array_ptr);
3037 		break;
3038 	case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH:
3039 		r = kfd_dbg_trap_set_dev_address_watch(pdd,
3040 				args->set_node_address_watch.address,
3041 				args->set_node_address_watch.mask,
3042 				&args->set_node_address_watch.id,
3043 				args->set_node_address_watch.mode);
3044 		break;
3045 	case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH:
3046 		r = kfd_dbg_trap_clear_dev_address_watch(pdd,
3047 				args->clear_node_address_watch.id);
3048 		break;
3049 	case KFD_IOC_DBG_TRAP_SET_FLAGS:
3050 		r = kfd_dbg_trap_set_flags(target, &args->set_flags.flags);
3051 		break;
3052 	case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
3053 		r = kfd_dbg_ev_query_debug_event(target,
3054 				&args->query_debug_event.queue_id,
3055 				&args->query_debug_event.gpu_id,
3056 				args->query_debug_event.exception_mask,
3057 				&args->query_debug_event.exception_mask);
3058 		break;
3059 	case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO:
3060 		r = kfd_dbg_trap_query_exception_info(target,
3061 				args->query_exception_info.source_id,
3062 				args->query_exception_info.exception_code,
3063 				args->query_exception_info.clear_exception,
3064 				(void __user *)args->query_exception_info.info_ptr,
3065 				&args->query_exception_info.info_size);
3066 		break;
3067 	case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
3068 		r = pqm_get_queue_snapshot(&target->pqm,
3069 				args->queue_snapshot.exception_mask,
3070 				(void __user *)args->queue_snapshot.snapshot_buf_ptr,
3071 				&args->queue_snapshot.num_queues,
3072 				&args->queue_snapshot.entry_size);
3073 		break;
3074 	case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT:
3075 		r = kfd_dbg_trap_device_snapshot(target,
3076 				args->device_snapshot.exception_mask,
3077 				(void __user *)args->device_snapshot.snapshot_buf_ptr,
3078 				&args->device_snapshot.num_devices,
3079 				&args->device_snapshot.entry_size);
3080 		break;
3081 	default:
3082 		pr_err("Invalid option: %i\n", args->op);
3083 		r = -EINVAL;
3084 	}
3085 
3086 unlock_out:
3087 	mutex_unlock(&target->mutex);
3088 
3089 out:
3090 	if (thread)
3091 		put_task_struct(thread);
3092 
3093 	if (mm)
3094 		mmput(mm);
3095 
3096 	if (pid)
3097 		put_pid(pid);
3098 
3099 	if (target)
3100 		kfd_unref_process(target);
3101 
3102 	return r;
3103 }
3104 
3105 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
3106 	[_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
3107 			    .cmd_drv = 0, .name = #ioctl}
3108 
3109 /** Ioctl table */
3110 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
3111 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
3112 			kfd_ioctl_get_version, 0),
3113 
3114 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
3115 			kfd_ioctl_create_queue, 0),
3116 
3117 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
3118 			kfd_ioctl_destroy_queue, 0),
3119 
3120 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
3121 			kfd_ioctl_set_memory_policy, 0),
3122 
3123 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
3124 			kfd_ioctl_get_clock_counters, 0),
3125 
3126 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
3127 			kfd_ioctl_get_process_apertures, 0),
3128 
3129 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
3130 			kfd_ioctl_update_queue, 0),
3131 
3132 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
3133 			kfd_ioctl_create_event, 0),
3134 
3135 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
3136 			kfd_ioctl_destroy_event, 0),
3137 
3138 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
3139 			kfd_ioctl_set_event, 0),
3140 
3141 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
3142 			kfd_ioctl_reset_event, 0),
3143 
3144 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
3145 			kfd_ioctl_wait_events, 0),
3146 
3147 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED,
3148 			kfd_ioctl_dbg_register, 0),
3149 
3150 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED,
3151 			kfd_ioctl_dbg_unregister, 0),
3152 
3153 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED,
3154 			kfd_ioctl_dbg_address_watch, 0),
3155 
3156 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED,
3157 			kfd_ioctl_dbg_wave_control, 0),
3158 
3159 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
3160 			kfd_ioctl_set_scratch_backing_va, 0),
3161 
3162 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
3163 			kfd_ioctl_get_tile_config, 0),
3164 
3165 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
3166 			kfd_ioctl_set_trap_handler, 0),
3167 
3168 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW,
3169 			kfd_ioctl_get_process_apertures_new, 0),
3170 
3171 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM,
3172 			kfd_ioctl_acquire_vm, 0),
3173 
3174 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU,
3175 			kfd_ioctl_alloc_memory_of_gpu, 0),
3176 
3177 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU,
3178 			kfd_ioctl_free_memory_of_gpu, 0),
3179 
3180 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU,
3181 			kfd_ioctl_map_memory_to_gpu, 0),
3182 
3183 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU,
3184 			kfd_ioctl_unmap_memory_from_gpu, 0),
3185 
3186 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK,
3187 			kfd_ioctl_set_cu_mask, 0),
3188 
3189 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE,
3190 			kfd_ioctl_get_queue_wave_state, 0),
3191 
3192 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO,
3193 				kfd_ioctl_get_dmabuf_info, 0),
3194 
3195 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
3196 				kfd_ioctl_import_dmabuf, 0),
3197 
3198 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
3199 			kfd_ioctl_alloc_queue_gws, 0),
3200 
3201 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS,
3202 			kfd_ioctl_smi_events, 0),
3203 
3204 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0),
3205 
3206 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE,
3207 			kfd_ioctl_set_xnack_mode, 0),
3208 
3209 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP,
3210 			kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE),
3211 
3212 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY,
3213 			kfd_ioctl_get_available_memory, 0),
3214 
3215 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF,
3216 				kfd_ioctl_export_dmabuf, 0),
3217 
3218 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE,
3219 			kfd_ioctl_runtime_enable, 0),
3220 
3221 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP,
3222 			kfd_ioctl_set_debug_trap, 0),
3223 };
3224 
3225 #define AMDKFD_CORE_IOCTL_COUNT	ARRAY_SIZE(amdkfd_ioctls)
3226 
kfd_ioctl(struct file * filep,unsigned int cmd,unsigned long arg)3227 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
3228 {
3229 	struct kfd_process *process;
3230 	amdkfd_ioctl_t *func;
3231 	const struct amdkfd_ioctl_desc *ioctl = NULL;
3232 	unsigned int nr = _IOC_NR(cmd);
3233 	char stack_kdata[128];
3234 	char *kdata = NULL;
3235 	unsigned int usize, asize;
3236 	int retcode = -EINVAL;
3237 	bool ptrace_attached = false;
3238 
3239 	if (nr >= AMDKFD_CORE_IOCTL_COUNT)
3240 		goto err_i1;
3241 
3242 	if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
3243 		u32 amdkfd_size;
3244 
3245 		ioctl = &amdkfd_ioctls[nr];
3246 
3247 		amdkfd_size = _IOC_SIZE(ioctl->cmd);
3248 		usize = asize = _IOC_SIZE(cmd);
3249 		if (amdkfd_size > asize)
3250 			asize = amdkfd_size;
3251 
3252 		cmd = ioctl->cmd;
3253 	} else
3254 		goto err_i1;
3255 
3256 	dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
3257 
3258 	/* Get the process struct from the filep. Only the process
3259 	 * that opened /dev/kfd can use the file descriptor. Child
3260 	 * processes need to create their own KFD device context.
3261 	 */
3262 	process = filep->private_data;
3263 
3264 	rcu_read_lock();
3265 	if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) &&
3266 	    ptrace_parent(process->lead_thread) == current)
3267 		ptrace_attached = true;
3268 	rcu_read_unlock();
3269 
3270 	if (process->lead_thread != current->group_leader
3271 	    && !ptrace_attached) {
3272 		dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
3273 		retcode = -EBADF;
3274 		goto err_i1;
3275 	}
3276 
3277 	/* Do not trust userspace, use our own definition */
3278 	func = ioctl->func;
3279 
3280 	if (unlikely(!func)) {
3281 		dev_dbg(kfd_device, "no function\n");
3282 		retcode = -EINVAL;
3283 		goto err_i1;
3284 	}
3285 
3286 	/*
3287 	 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support
3288 	 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a
3289 	 * more priviledged access.
3290 	 */
3291 	if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) {
3292 		if (!capable(CAP_CHECKPOINT_RESTORE) &&
3293 						!capable(CAP_SYS_ADMIN)) {
3294 			retcode = -EACCES;
3295 			goto err_i1;
3296 		}
3297 	}
3298 
3299 	if (cmd & (IOC_IN | IOC_OUT)) {
3300 		if (asize <= sizeof(stack_kdata)) {
3301 			kdata = stack_kdata;
3302 		} else {
3303 			kdata = kmalloc(asize, GFP_KERNEL);
3304 			if (!kdata) {
3305 				retcode = -ENOMEM;
3306 				goto err_i1;
3307 			}
3308 		}
3309 		if (asize > usize)
3310 			memset(kdata + usize, 0, asize - usize);
3311 	}
3312 
3313 	if (cmd & IOC_IN) {
3314 		if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
3315 			retcode = -EFAULT;
3316 			goto err_i1;
3317 		}
3318 	} else if (cmd & IOC_OUT) {
3319 		memset(kdata, 0, usize);
3320 	}
3321 
3322 	retcode = func(filep, process, kdata);
3323 
3324 	if (cmd & IOC_OUT)
3325 		if (copy_to_user((void __user *)arg, kdata, usize) != 0)
3326 			retcode = -EFAULT;
3327 
3328 err_i1:
3329 	if (!ioctl)
3330 		dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
3331 			  task_pid_nr(current), cmd, nr);
3332 
3333 	if (kdata != stack_kdata)
3334 		kfree(kdata);
3335 
3336 	if (retcode)
3337 		dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n",
3338 				nr, arg, retcode);
3339 
3340 	return retcode;
3341 }
3342 
kfd_mmio_mmap(struct kfd_node * dev,struct kfd_process * process,struct vm_area_struct * vma)3343 static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process,
3344 		      struct vm_area_struct *vma)
3345 {
3346 	phys_addr_t address;
3347 
3348 	if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3349 		return -EINVAL;
3350 
3351 	address = dev->adev->rmmio_remap.bus_addr;
3352 
3353 	vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
3354 				VM_DONTDUMP | VM_PFNMAP);
3355 
3356 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3357 
3358 	pr_debug("pasid 0x%x mapping mmio page\n"
3359 		 "     target user address == 0x%08llX\n"
3360 		 "     physical address    == 0x%08llX\n"
3361 		 "     vm_flags            == 0x%04lX\n"
3362 		 "     size                == 0x%04lX\n",
3363 		 process->pasid, (unsigned long long) vma->vm_start,
3364 		 address, vma->vm_flags, PAGE_SIZE);
3365 
3366 	return io_remap_pfn_range(vma,
3367 				vma->vm_start,
3368 				address >> PAGE_SHIFT,
3369 				PAGE_SIZE,
3370 				vma->vm_page_prot);
3371 }
3372 
3373 
kfd_mmap(struct file * filp,struct vm_area_struct * vma)3374 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
3375 {
3376 	struct kfd_process *process;
3377 	struct kfd_node *dev = NULL;
3378 	unsigned long mmap_offset;
3379 	unsigned int gpu_id;
3380 
3381 	process = kfd_get_process(current);
3382 	if (IS_ERR(process))
3383 		return PTR_ERR(process);
3384 
3385 	mmap_offset = vma->vm_pgoff << PAGE_SHIFT;
3386 	gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset);
3387 	if (gpu_id)
3388 		dev = kfd_device_by_id(gpu_id);
3389 
3390 	switch (mmap_offset & KFD_MMAP_TYPE_MASK) {
3391 	case KFD_MMAP_TYPE_DOORBELL:
3392 		if (!dev)
3393 			return -ENODEV;
3394 		return kfd_doorbell_mmap(dev, process, vma);
3395 
3396 	case KFD_MMAP_TYPE_EVENTS:
3397 		return kfd_event_mmap(process, vma);
3398 
3399 	case KFD_MMAP_TYPE_RESERVED_MEM:
3400 		if (!dev)
3401 			return -ENODEV;
3402 		return kfd_reserved_mem_mmap(dev, process, vma);
3403 	case KFD_MMAP_TYPE_MMIO:
3404 		if (!dev)
3405 			return -ENODEV;
3406 		return kfd_mmio_mmap(dev, process, vma);
3407 	}
3408 
3409 	return -EFAULT;
3410 }
3411