1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #include <linux/init.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/slab.h>
7 #include <linux/pci.h>
8 #include <linux/interrupt.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/workqueue.h>
12 #include <linux/fs.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
14 #include <linux/device.h>
15 #include <linux/idr.h>
16 #include <linux/iommu.h>
17 #include <uapi/linux/idxd.h>
18 #include <linux/dmaengine.h>
19 #include "../dmaengine.h"
20 #include "registers.h"
21 #include "idxd.h"
22 #include "perfmon.h"
23
24 MODULE_VERSION(IDXD_DRIVER_VERSION);
25 MODULE_LICENSE("GPL v2");
26 MODULE_AUTHOR("Intel Corporation");
27 MODULE_IMPORT_NS(IDXD);
28
29 static bool sva = true;
30 module_param(sva, bool, 0644);
31 MODULE_PARM_DESC(sva, "Toggle SVA support on/off");
32
33 bool tc_override;
34 module_param(tc_override, bool, 0644);
35 MODULE_PARM_DESC(tc_override, "Override traffic class defaults");
36
37 #define DRV_NAME "idxd"
38
39 bool support_enqcmd;
40 DEFINE_IDA(idxd_ida);
41
42 static struct idxd_driver_data idxd_driver_data[] = {
43 [IDXD_TYPE_DSA] = {
44 .name_prefix = "dsa",
45 .type = IDXD_TYPE_DSA,
46 .compl_size = sizeof(struct dsa_completion_record),
47 .align = 32,
48 .dev_type = &dsa_device_type,
49 .evl_cr_off = offsetof(struct dsa_evl_entry, cr),
50 .cr_status_off = offsetof(struct dsa_completion_record, status),
51 .cr_result_off = offsetof(struct dsa_completion_record, result),
52 },
53 [IDXD_TYPE_IAX] = {
54 .name_prefix = "iax",
55 .type = IDXD_TYPE_IAX,
56 .compl_size = sizeof(struct iax_completion_record),
57 .align = 64,
58 .dev_type = &iax_device_type,
59 .evl_cr_off = offsetof(struct iax_evl_entry, cr),
60 .cr_status_off = offsetof(struct iax_completion_record, status),
61 .cr_result_off = offsetof(struct iax_completion_record, error_code),
62 },
63 };
64
65 static struct pci_device_id idxd_pci_tbl[] = {
66 /* DSA ver 1.0 platforms */
67 { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) },
68
69 /* IAX ver 1.0 platforms */
70 { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) },
71 { 0, }
72 };
73 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl);
74
idxd_setup_interrupts(struct idxd_device * idxd)75 static int idxd_setup_interrupts(struct idxd_device *idxd)
76 {
77 struct pci_dev *pdev = idxd->pdev;
78 struct device *dev = &pdev->dev;
79 struct idxd_irq_entry *ie;
80 int i, msixcnt;
81 int rc = 0;
82
83 msixcnt = pci_msix_vec_count(pdev);
84 if (msixcnt < 0) {
85 dev_err(dev, "Not MSI-X interrupt capable.\n");
86 return -ENOSPC;
87 }
88 idxd->irq_cnt = msixcnt;
89
90 rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX);
91 if (rc != msixcnt) {
92 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc);
93 return -ENOSPC;
94 }
95 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt);
96
97
98 ie = idxd_get_ie(idxd, 0);
99 ie->vector = pci_irq_vector(pdev, 0);
100 rc = request_threaded_irq(ie->vector, NULL, idxd_misc_thread, 0, "idxd-misc", ie);
101 if (rc < 0) {
102 dev_err(dev, "Failed to allocate misc interrupt.\n");
103 goto err_misc_irq;
104 }
105 dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector);
106
107 for (i = 0; i < idxd->max_wqs; i++) {
108 int msix_idx = i + 1;
109
110 ie = idxd_get_ie(idxd, msix_idx);
111 ie->id = msix_idx;
112 ie->int_handle = INVALID_INT_HANDLE;
113 ie->pasid = IOMMU_PASID_INVALID;
114
115 spin_lock_init(&ie->list_lock);
116 init_llist_head(&ie->pending_llist);
117 INIT_LIST_HEAD(&ie->work_list);
118 }
119
120 idxd_unmask_error_interrupts(idxd);
121 return 0;
122
123 err_misc_irq:
124 idxd_mask_error_interrupts(idxd);
125 pci_free_irq_vectors(pdev);
126 dev_err(dev, "No usable interrupts\n");
127 return rc;
128 }
129
idxd_cleanup_interrupts(struct idxd_device * idxd)130 static void idxd_cleanup_interrupts(struct idxd_device *idxd)
131 {
132 struct pci_dev *pdev = idxd->pdev;
133 struct idxd_irq_entry *ie;
134 int msixcnt;
135
136 msixcnt = pci_msix_vec_count(pdev);
137 if (msixcnt <= 0)
138 return;
139
140 ie = idxd_get_ie(idxd, 0);
141 idxd_mask_error_interrupts(idxd);
142 free_irq(ie->vector, ie);
143 pci_free_irq_vectors(pdev);
144 }
145
idxd_setup_wqs(struct idxd_device * idxd)146 static int idxd_setup_wqs(struct idxd_device *idxd)
147 {
148 struct device *dev = &idxd->pdev->dev;
149 struct idxd_wq *wq;
150 struct device *conf_dev;
151 int i, rc;
152
153 idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *),
154 GFP_KERNEL, dev_to_node(dev));
155 if (!idxd->wqs)
156 return -ENOMEM;
157
158 idxd->wq_enable_map = bitmap_zalloc_node(idxd->max_wqs, GFP_KERNEL, dev_to_node(dev));
159 if (!idxd->wq_enable_map) {
160 kfree(idxd->wqs);
161 return -ENOMEM;
162 }
163
164 for (i = 0; i < idxd->max_wqs; i++) {
165 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev));
166 if (!wq) {
167 rc = -ENOMEM;
168 goto err;
169 }
170
171 idxd_dev_set_type(&wq->idxd_dev, IDXD_DEV_WQ);
172 conf_dev = wq_confdev(wq);
173 wq->id = i;
174 wq->idxd = idxd;
175 device_initialize(wq_confdev(wq));
176 conf_dev->parent = idxd_confdev(idxd);
177 conf_dev->bus = &dsa_bus_type;
178 conf_dev->type = &idxd_wq_device_type;
179 rc = dev_set_name(conf_dev, "wq%d.%d", idxd->id, wq->id);
180 if (rc < 0) {
181 put_device(conf_dev);
182 goto err;
183 }
184
185 mutex_init(&wq->wq_lock);
186 init_waitqueue_head(&wq->err_queue);
187 init_completion(&wq->wq_dead);
188 init_completion(&wq->wq_resurrect);
189 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
190 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
191 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
192 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
193 if (!wq->wqcfg) {
194 put_device(conf_dev);
195 rc = -ENOMEM;
196 goto err;
197 }
198
199 if (idxd->hw.wq_cap.op_config) {
200 wq->opcap_bmap = bitmap_zalloc(IDXD_MAX_OPCAP_BITS, GFP_KERNEL);
201 if (!wq->opcap_bmap) {
202 put_device(conf_dev);
203 rc = -ENOMEM;
204 goto err;
205 }
206 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS);
207 }
208 mutex_init(&wq->uc_lock);
209 xa_init(&wq->upasid_xa);
210 idxd->wqs[i] = wq;
211 }
212
213 return 0;
214
215 err:
216 while (--i >= 0) {
217 wq = idxd->wqs[i];
218 conf_dev = wq_confdev(wq);
219 put_device(conf_dev);
220 }
221 return rc;
222 }
223
idxd_setup_engines(struct idxd_device * idxd)224 static int idxd_setup_engines(struct idxd_device *idxd)
225 {
226 struct idxd_engine *engine;
227 struct device *dev = &idxd->pdev->dev;
228 struct device *conf_dev;
229 int i, rc;
230
231 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *),
232 GFP_KERNEL, dev_to_node(dev));
233 if (!idxd->engines)
234 return -ENOMEM;
235
236 for (i = 0; i < idxd->max_engines; i++) {
237 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev));
238 if (!engine) {
239 rc = -ENOMEM;
240 goto err;
241 }
242
243 idxd_dev_set_type(&engine->idxd_dev, IDXD_DEV_ENGINE);
244 conf_dev = engine_confdev(engine);
245 engine->id = i;
246 engine->idxd = idxd;
247 device_initialize(conf_dev);
248 conf_dev->parent = idxd_confdev(idxd);
249 conf_dev->bus = &dsa_bus_type;
250 conf_dev->type = &idxd_engine_device_type;
251 rc = dev_set_name(conf_dev, "engine%d.%d", idxd->id, engine->id);
252 if (rc < 0) {
253 put_device(conf_dev);
254 goto err;
255 }
256
257 idxd->engines[i] = engine;
258 }
259
260 return 0;
261
262 err:
263 while (--i >= 0) {
264 engine = idxd->engines[i];
265 conf_dev = engine_confdev(engine);
266 put_device(conf_dev);
267 }
268 return rc;
269 }
270
idxd_setup_groups(struct idxd_device * idxd)271 static int idxd_setup_groups(struct idxd_device *idxd)
272 {
273 struct device *dev = &idxd->pdev->dev;
274 struct device *conf_dev;
275 struct idxd_group *group;
276 int i, rc;
277
278 idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *),
279 GFP_KERNEL, dev_to_node(dev));
280 if (!idxd->groups)
281 return -ENOMEM;
282
283 for (i = 0; i < idxd->max_groups; i++) {
284 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev));
285 if (!group) {
286 rc = -ENOMEM;
287 goto err;
288 }
289
290 idxd_dev_set_type(&group->idxd_dev, IDXD_DEV_GROUP);
291 conf_dev = group_confdev(group);
292 group->id = i;
293 group->idxd = idxd;
294 device_initialize(conf_dev);
295 conf_dev->parent = idxd_confdev(idxd);
296 conf_dev->bus = &dsa_bus_type;
297 conf_dev->type = &idxd_group_device_type;
298 rc = dev_set_name(conf_dev, "group%d.%d", idxd->id, group->id);
299 if (rc < 0) {
300 put_device(conf_dev);
301 goto err;
302 }
303
304 idxd->groups[i] = group;
305 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) {
306 group->tc_a = 1;
307 group->tc_b = 1;
308 } else {
309 group->tc_a = -1;
310 group->tc_b = -1;
311 }
312 /*
313 * The default value is the same as the value of
314 * total read buffers in GRPCAP.
315 */
316 group->rdbufs_allowed = idxd->max_rdbufs;
317 }
318
319 return 0;
320
321 err:
322 while (--i >= 0) {
323 group = idxd->groups[i];
324 put_device(group_confdev(group));
325 }
326 return rc;
327 }
328
idxd_cleanup_internals(struct idxd_device * idxd)329 static void idxd_cleanup_internals(struct idxd_device *idxd)
330 {
331 int i;
332
333 for (i = 0; i < idxd->max_groups; i++)
334 put_device(group_confdev(idxd->groups[i]));
335 for (i = 0; i < idxd->max_engines; i++)
336 put_device(engine_confdev(idxd->engines[i]));
337 for (i = 0; i < idxd->max_wqs; i++)
338 put_device(wq_confdev(idxd->wqs[i]));
339 destroy_workqueue(idxd->wq);
340 }
341
idxd_init_evl(struct idxd_device * idxd)342 static int idxd_init_evl(struct idxd_device *idxd)
343 {
344 struct device *dev = &idxd->pdev->dev;
345 unsigned int evl_cache_size;
346 struct idxd_evl *evl;
347 const char *idxd_name;
348
349 if (idxd->hw.gen_cap.evl_support == 0)
350 return 0;
351
352 evl = kzalloc_node(sizeof(*evl), GFP_KERNEL, dev_to_node(dev));
353 if (!evl)
354 return -ENOMEM;
355
356 spin_lock_init(&evl->lock);
357 evl->size = IDXD_EVL_SIZE_MIN;
358
359 idxd_name = dev_name(idxd_confdev(idxd));
360 evl_cache_size = sizeof(struct idxd_evl_fault) + evl_ent_size(idxd);
361 /*
362 * Since completion record in evl_cache will be copied to user
363 * when handling completion record page fault, need to create
364 * the cache suitable for user copy.
365 */
366 idxd->evl_cache = kmem_cache_create_usercopy(idxd_name, evl_cache_size,
367 0, 0, 0, evl_cache_size,
368 NULL);
369 if (!idxd->evl_cache) {
370 kfree(evl);
371 return -ENOMEM;
372 }
373
374 idxd->evl = evl;
375 return 0;
376 }
377
idxd_setup_internals(struct idxd_device * idxd)378 static int idxd_setup_internals(struct idxd_device *idxd)
379 {
380 struct device *dev = &idxd->pdev->dev;
381 int rc, i;
382
383 init_waitqueue_head(&idxd->cmd_waitq);
384
385 rc = idxd_setup_wqs(idxd);
386 if (rc < 0)
387 goto err_wqs;
388
389 rc = idxd_setup_engines(idxd);
390 if (rc < 0)
391 goto err_engine;
392
393 rc = idxd_setup_groups(idxd);
394 if (rc < 0)
395 goto err_group;
396
397 idxd->wq = create_workqueue(dev_name(dev));
398 if (!idxd->wq) {
399 rc = -ENOMEM;
400 goto err_wkq_create;
401 }
402
403 rc = idxd_init_evl(idxd);
404 if (rc < 0)
405 goto err_evl;
406
407 return 0;
408
409 err_evl:
410 destroy_workqueue(idxd->wq);
411 err_wkq_create:
412 for (i = 0; i < idxd->max_groups; i++)
413 put_device(group_confdev(idxd->groups[i]));
414 err_group:
415 for (i = 0; i < idxd->max_engines; i++)
416 put_device(engine_confdev(idxd->engines[i]));
417 err_engine:
418 for (i = 0; i < idxd->max_wqs; i++)
419 put_device(wq_confdev(idxd->wqs[i]));
420 err_wqs:
421 return rc;
422 }
423
idxd_read_table_offsets(struct idxd_device * idxd)424 static void idxd_read_table_offsets(struct idxd_device *idxd)
425 {
426 union offsets_reg offsets;
427 struct device *dev = &idxd->pdev->dev;
428
429 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
430 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64));
431 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT;
432 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset);
433 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT;
434 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset);
435 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT;
436 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset);
437 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT;
438 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
439 }
440
multi_u64_to_bmap(unsigned long * bmap,u64 * val,int count)441 void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count)
442 {
443 int i, j, nr;
444
445 for (i = 0, nr = 0; i < count; i++) {
446 for (j = 0; j < BITS_PER_LONG_LONG; j++) {
447 if (val[i] & BIT(j))
448 set_bit(nr, bmap);
449 nr++;
450 }
451 }
452 }
453
idxd_read_caps(struct idxd_device * idxd)454 static void idxd_read_caps(struct idxd_device *idxd)
455 {
456 struct device *dev = &idxd->pdev->dev;
457 int i;
458
459 /* reading generic capabilities */
460 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
461 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits);
462
463 if (idxd->hw.gen_cap.cmd_cap) {
464 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET);
465 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap);
466 }
467
468 /* reading command capabilities */
469 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))
470 idxd->request_int_handles = true;
471
472 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
473 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
474 idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift);
475 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
476 if (idxd->hw.gen_cap.config_en)
477 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);
478
479 /* reading group capabilities */
480 idxd->hw.group_cap.bits =
481 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
482 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits);
483 idxd->max_groups = idxd->hw.group_cap.num_groups;
484 dev_dbg(dev, "max groups: %u\n", idxd->max_groups);
485 idxd->max_rdbufs = idxd->hw.group_cap.total_rdbufs;
486 dev_dbg(dev, "max read buffers: %u\n", idxd->max_rdbufs);
487 idxd->nr_rdbufs = idxd->max_rdbufs;
488
489 /* read engine capabilities */
490 idxd->hw.engine_cap.bits =
491 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
492 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits);
493 idxd->max_engines = idxd->hw.engine_cap.num_engines;
494 dev_dbg(dev, "max engines: %u\n", idxd->max_engines);
495
496 /* read workqueue capabilities */
497 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
498 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits);
499 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size;
500 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size);
501 idxd->max_wqs = idxd->hw.wq_cap.num_wqs;
502 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs);
503 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN);
504 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size);
505
506 /* reading operation capabilities */
507 for (i = 0; i < 4; i++) {
508 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
509 IDXD_OPCAP_OFFSET + i * sizeof(u64));
510 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]);
511 }
512 multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4);
513
514 /* read iaa cap */
515 if (idxd->data->type == IDXD_TYPE_IAX && idxd->hw.version >= DEVICE_VERSION_2)
516 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET);
517 }
518
idxd_alloc(struct pci_dev * pdev,struct idxd_driver_data * data)519 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data)
520 {
521 struct device *dev = &pdev->dev;
522 struct device *conf_dev;
523 struct idxd_device *idxd;
524 int rc;
525
526 idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev));
527 if (!idxd)
528 return NULL;
529
530 conf_dev = idxd_confdev(idxd);
531 idxd->pdev = pdev;
532 idxd->data = data;
533 idxd_dev_set_type(&idxd->idxd_dev, idxd->data->type);
534 idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL);
535 if (idxd->id < 0)
536 return NULL;
537
538 idxd->opcap_bmap = bitmap_zalloc_node(IDXD_MAX_OPCAP_BITS, GFP_KERNEL, dev_to_node(dev));
539 if (!idxd->opcap_bmap) {
540 ida_free(&idxd_ida, idxd->id);
541 return NULL;
542 }
543
544 device_initialize(conf_dev);
545 conf_dev->parent = dev;
546 conf_dev->bus = &dsa_bus_type;
547 conf_dev->type = idxd->data->dev_type;
548 rc = dev_set_name(conf_dev, "%s%d", idxd->data->name_prefix, idxd->id);
549 if (rc < 0) {
550 put_device(conf_dev);
551 return NULL;
552 }
553
554 spin_lock_init(&idxd->dev_lock);
555 spin_lock_init(&idxd->cmd_lock);
556
557 return idxd;
558 }
559
idxd_enable_system_pasid(struct idxd_device * idxd)560 static int idxd_enable_system_pasid(struct idxd_device *idxd)
561 {
562 struct pci_dev *pdev = idxd->pdev;
563 struct device *dev = &pdev->dev;
564 struct iommu_domain *domain;
565 ioasid_t pasid;
566 int ret;
567
568 /*
569 * Attach a global PASID to the DMA domain so that we can use ENQCMDS
570 * to submit work on buffers mapped by DMA API.
571 */
572 domain = iommu_get_domain_for_dev(dev);
573 if (!domain)
574 return -EPERM;
575
576 pasid = iommu_alloc_global_pasid(dev);
577 if (pasid == IOMMU_PASID_INVALID)
578 return -ENOSPC;
579
580 /*
581 * DMA domain is owned by the driver, it should support all valid
582 * types such as DMA-FQ, identity, etc.
583 */
584 ret = iommu_attach_device_pasid(domain, dev, pasid);
585 if (ret) {
586 dev_err(dev, "failed to attach device pasid %d, domain type %d",
587 pasid, domain->type);
588 iommu_free_global_pasid(pasid);
589 return ret;
590 }
591
592 /* Since we set user privilege for kernel DMA, enable completion IRQ */
593 idxd_set_user_intr(idxd, 1);
594 idxd->pasid = pasid;
595
596 return ret;
597 }
598
idxd_disable_system_pasid(struct idxd_device * idxd)599 static void idxd_disable_system_pasid(struct idxd_device *idxd)
600 {
601 struct pci_dev *pdev = idxd->pdev;
602 struct device *dev = &pdev->dev;
603 struct iommu_domain *domain;
604
605 domain = iommu_get_domain_for_dev(dev);
606 if (!domain)
607 return;
608
609 iommu_detach_device_pasid(domain, dev, idxd->pasid);
610 iommu_free_global_pasid(idxd->pasid);
611
612 idxd_set_user_intr(idxd, 0);
613 idxd->sva = NULL;
614 idxd->pasid = IOMMU_PASID_INVALID;
615 }
616
idxd_enable_sva(struct pci_dev * pdev)617 static int idxd_enable_sva(struct pci_dev *pdev)
618 {
619 int ret;
620
621 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
622 if (ret)
623 return ret;
624
625 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
626 if (ret)
627 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
628
629 return ret;
630 }
631
idxd_disable_sva(struct pci_dev * pdev)632 static void idxd_disable_sva(struct pci_dev *pdev)
633 {
634 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
635 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
636 }
637
idxd_probe(struct idxd_device * idxd)638 static int idxd_probe(struct idxd_device *idxd)
639 {
640 struct pci_dev *pdev = idxd->pdev;
641 struct device *dev = &pdev->dev;
642 int rc;
643
644 dev_dbg(dev, "%s entered and resetting device\n", __func__);
645 rc = idxd_device_init_reset(idxd);
646 if (rc < 0)
647 return rc;
648
649 dev_dbg(dev, "IDXD reset complete\n");
650
651 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) {
652 if (idxd_enable_sva(pdev)) {
653 dev_warn(dev, "Unable to turn on user SVA feature.\n");
654 } else {
655 set_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags);
656
657 rc = idxd_enable_system_pasid(idxd);
658 if (rc)
659 dev_warn(dev, "No in-kernel DMA with PASID. %d\n", rc);
660 else
661 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags);
662 }
663 } else if (!sva) {
664 dev_warn(dev, "User forced SVA off via module param.\n");
665 }
666
667 idxd_read_caps(idxd);
668 idxd_read_table_offsets(idxd);
669
670 rc = idxd_setup_internals(idxd);
671 if (rc)
672 goto err;
673
674 /* If the configs are readonly, then load them from device */
675 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
676 dev_dbg(dev, "Loading RO device config\n");
677 rc = idxd_device_load_config(idxd);
678 if (rc < 0)
679 goto err_config;
680 }
681
682 rc = idxd_setup_interrupts(idxd);
683 if (rc)
684 goto err_config;
685
686 idxd->major = idxd_cdev_get_major(idxd);
687
688 rc = perfmon_pmu_init(idxd);
689 if (rc < 0)
690 dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc);
691
692 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id);
693 return 0;
694
695 err_config:
696 idxd_cleanup_internals(idxd);
697 err:
698 if (device_pasid_enabled(idxd))
699 idxd_disable_system_pasid(idxd);
700 if (device_user_pasid_enabled(idxd))
701 idxd_disable_sva(pdev);
702 return rc;
703 }
704
idxd_cleanup(struct idxd_device * idxd)705 static void idxd_cleanup(struct idxd_device *idxd)
706 {
707 perfmon_pmu_remove(idxd);
708 idxd_cleanup_interrupts(idxd);
709 idxd_cleanup_internals(idxd);
710 if (device_pasid_enabled(idxd))
711 idxd_disable_system_pasid(idxd);
712 if (device_user_pasid_enabled(idxd))
713 idxd_disable_sva(idxd->pdev);
714 }
715
idxd_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)716 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
717 {
718 struct device *dev = &pdev->dev;
719 struct idxd_device *idxd;
720 struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data;
721 int rc;
722
723 rc = pci_enable_device(pdev);
724 if (rc)
725 return rc;
726
727 dev_dbg(dev, "Alloc IDXD context\n");
728 idxd = idxd_alloc(pdev, data);
729 if (!idxd) {
730 rc = -ENOMEM;
731 goto err_idxd_alloc;
732 }
733
734 dev_dbg(dev, "Mapping BARs\n");
735 idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0);
736 if (!idxd->reg_base) {
737 rc = -ENOMEM;
738 goto err_iomap;
739 }
740
741 dev_dbg(dev, "Set DMA masks\n");
742 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
743 if (rc)
744 goto err;
745
746 dev_dbg(dev, "Set PCI master\n");
747 pci_set_master(pdev);
748 pci_set_drvdata(pdev, idxd);
749
750 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET);
751 rc = idxd_probe(idxd);
752 if (rc) {
753 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n");
754 goto err;
755 }
756
757 rc = idxd_register_devices(idxd);
758 if (rc) {
759 dev_err(dev, "IDXD sysfs setup failed\n");
760 goto err_dev_register;
761 }
762
763 rc = idxd_device_init_debugfs(idxd);
764 if (rc)
765 dev_warn(dev, "IDXD debugfs failed to setup\n");
766
767 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n",
768 idxd->hw.version);
769
770 return 0;
771
772 err_dev_register:
773 idxd_cleanup(idxd);
774 err:
775 pci_iounmap(pdev, idxd->reg_base);
776 err_iomap:
777 put_device(idxd_confdev(idxd));
778 err_idxd_alloc:
779 pci_disable_device(pdev);
780 return rc;
781 }
782
idxd_wqs_quiesce(struct idxd_device * idxd)783 void idxd_wqs_quiesce(struct idxd_device *idxd)
784 {
785 struct idxd_wq *wq;
786 int i;
787
788 for (i = 0; i < idxd->max_wqs; i++) {
789 wq = idxd->wqs[i];
790 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL)
791 idxd_wq_quiesce(wq);
792 }
793 }
794
idxd_shutdown(struct pci_dev * pdev)795 static void idxd_shutdown(struct pci_dev *pdev)
796 {
797 struct idxd_device *idxd = pci_get_drvdata(pdev);
798 struct idxd_irq_entry *irq_entry;
799 int rc;
800
801 rc = idxd_device_disable(idxd);
802 if (rc)
803 dev_err(&pdev->dev, "Disabling device failed\n");
804
805 irq_entry = &idxd->ie;
806 synchronize_irq(irq_entry->vector);
807 idxd_mask_error_interrupts(idxd);
808 flush_workqueue(idxd->wq);
809 }
810
idxd_remove(struct pci_dev * pdev)811 static void idxd_remove(struct pci_dev *pdev)
812 {
813 struct idxd_device *idxd = pci_get_drvdata(pdev);
814 struct idxd_irq_entry *irq_entry;
815
816 idxd_unregister_devices(idxd);
817 /*
818 * When ->release() is called for the idxd->conf_dev, it frees all the memory related
819 * to the idxd context. The driver still needs those bits in order to do the rest of
820 * the cleanup. However, we do need to unbound the idxd sub-driver. So take a ref
821 * on the device here to hold off the freeing while allowing the idxd sub-driver
822 * to unbind.
823 */
824 get_device(idxd_confdev(idxd));
825 device_unregister(idxd_confdev(idxd));
826 idxd_shutdown(pdev);
827 if (device_pasid_enabled(idxd))
828 idxd_disable_system_pasid(idxd);
829 idxd_device_remove_debugfs(idxd);
830
831 irq_entry = idxd_get_ie(idxd, 0);
832 free_irq(irq_entry->vector, irq_entry);
833 pci_free_irq_vectors(pdev);
834 pci_iounmap(pdev, idxd->reg_base);
835 if (device_user_pasid_enabled(idxd))
836 idxd_disable_sva(pdev);
837 pci_disable_device(pdev);
838 destroy_workqueue(idxd->wq);
839 perfmon_pmu_remove(idxd);
840 put_device(idxd_confdev(idxd));
841 }
842
843 static struct pci_driver idxd_pci_driver = {
844 .name = DRV_NAME,
845 .id_table = idxd_pci_tbl,
846 .probe = idxd_pci_probe,
847 .remove = idxd_remove,
848 .shutdown = idxd_shutdown,
849 };
850
idxd_init_module(void)851 static int __init idxd_init_module(void)
852 {
853 int err;
854
855 /*
856 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in
857 * enumerating the device. We can not utilize it.
858 */
859 if (!cpu_feature_enabled(X86_FEATURE_MOVDIR64B)) {
860 pr_warn("idxd driver failed to load without MOVDIR64B.\n");
861 return -ENODEV;
862 }
863
864 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
865 pr_warn("Platform does not have ENQCMD(S) support.\n");
866 else
867 support_enqcmd = true;
868
869 perfmon_init();
870
871 err = idxd_driver_register(&idxd_drv);
872 if (err < 0)
873 goto err_idxd_driver_register;
874
875 err = idxd_driver_register(&idxd_dmaengine_drv);
876 if (err < 0)
877 goto err_idxd_dmaengine_driver_register;
878
879 err = idxd_driver_register(&idxd_user_drv);
880 if (err < 0)
881 goto err_idxd_user_driver_register;
882
883 err = idxd_cdev_register();
884 if (err)
885 goto err_cdev_register;
886
887 err = idxd_init_debugfs();
888 if (err)
889 goto err_debugfs;
890
891 err = pci_register_driver(&idxd_pci_driver);
892 if (err)
893 goto err_pci_register;
894
895 return 0;
896
897 err_pci_register:
898 idxd_remove_debugfs();
899 err_debugfs:
900 idxd_cdev_remove();
901 err_cdev_register:
902 idxd_driver_unregister(&idxd_user_drv);
903 err_idxd_user_driver_register:
904 idxd_driver_unregister(&idxd_dmaengine_drv);
905 err_idxd_dmaengine_driver_register:
906 idxd_driver_unregister(&idxd_drv);
907 err_idxd_driver_register:
908 return err;
909 }
910 module_init(idxd_init_module);
911
idxd_exit_module(void)912 static void __exit idxd_exit_module(void)
913 {
914 idxd_driver_unregister(&idxd_user_drv);
915 idxd_driver_unregister(&idxd_dmaengine_drv);
916 idxd_driver_unregister(&idxd_drv);
917 pci_unregister_driver(&idxd_pci_driver);
918 idxd_cdev_remove();
919 perfmon_exit();
920 idxd_remove_debugfs();
921 }
922 module_exit(idxd_exit_module);
923