1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/err.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13
14 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
15
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "common.h"
21 #include "gdsc.h"
22 #include "reset.h"
23
24 enum {
25 P_BI_TCXO,
26 P_GPLL0_OUT_EVEN,
27 P_GPLL0_OUT_MAIN,
28 P_GPLL1_OUT_MAIN,
29 P_GPLL4_OUT_MAIN,
30 P_GPLL6_OUT_MAIN,
31 P_GPLL7_OUT_MAIN,
32 P_SLEEP_CLK,
33 };
34
35 static struct clk_alpha_pll gpll0 = {
36 .offset = 0x0,
37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
38 .clkr = {
39 .enable_reg = 0x52010,
40 .enable_mask = BIT(0),
41 .hw.init = &(struct clk_init_data){
42 .name = "gpll0",
43 .parent_data = &(const struct clk_parent_data){
44 .fw_name = "bi_tcxo",
45 .name = "bi_tcxo",
46 },
47 .num_parents = 1,
48 .ops = &clk_alpha_pll_fixed_fabia_ops,
49 },
50 },
51 };
52
53 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
54 { 0x1, 2 },
55 { }
56 };
57
58 static struct clk_alpha_pll_postdiv gpll0_out_even = {
59 .offset = 0x0,
60 .post_div_shift = 8,
61 .post_div_table = post_div_table_gpll0_out_even,
62 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
63 .width = 4,
64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
65 .clkr.hw.init = &(struct clk_init_data){
66 .name = "gpll0_out_even",
67 .parent_hws = (const struct clk_hw*[]){
68 &gpll0.clkr.hw,
69 },
70 .num_parents = 1,
71 .ops = &clk_alpha_pll_postdiv_fabia_ops,
72 },
73 };
74
75 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
76 .mult = 1,
77 .div = 2,
78 .hw.init = &(struct clk_init_data){
79 .name = "gcc_pll0_main_div_cdiv",
80 .parent_hws = (const struct clk_hw*[]){
81 &gpll0.clkr.hw,
82 },
83 .num_parents = 1,
84 .ops = &clk_fixed_factor_ops,
85 },
86 };
87
88 static struct clk_alpha_pll gpll1 = {
89 .offset = 0x01000,
90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
91 .clkr = {
92 .enable_reg = 0x52010,
93 .enable_mask = BIT(1),
94 .hw.init = &(struct clk_init_data){
95 .name = "gpll1",
96 .parent_data = &(const struct clk_parent_data){
97 .fw_name = "bi_tcxo",
98 .name = "bi_tcxo",
99 },
100 .num_parents = 1,
101 .ops = &clk_alpha_pll_fixed_fabia_ops,
102 },
103 },
104 };
105
106 static struct clk_alpha_pll gpll4 = {
107 .offset = 0x76000,
108 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
109 .clkr = {
110 .enable_reg = 0x52010,
111 .enable_mask = BIT(4),
112 .hw.init = &(struct clk_init_data){
113 .name = "gpll4",
114 .parent_data = &(const struct clk_parent_data){
115 .fw_name = "bi_tcxo",
116 .name = "bi_tcxo",
117 },
118 .num_parents = 1,
119 .ops = &clk_alpha_pll_fixed_fabia_ops,
120 },
121 },
122 };
123
124 static struct clk_alpha_pll gpll6 = {
125 .offset = 0x13000,
126 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
127 .clkr = {
128 .enable_reg = 0x52010,
129 .enable_mask = BIT(6),
130 .hw.init = &(struct clk_init_data){
131 .name = "gpll6",
132 .parent_data = &(const struct clk_parent_data){
133 .fw_name = "bi_tcxo",
134 .name = "bi_tcxo",
135 },
136 .num_parents = 1,
137 .ops = &clk_alpha_pll_fixed_fabia_ops,
138 },
139 },
140 };
141
142 static struct clk_alpha_pll gpll7 = {
143 .offset = 0x27000,
144 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
145 .clkr = {
146 .enable_reg = 0x52010,
147 .enable_mask = BIT(7),
148 .hw.init = &(struct clk_init_data){
149 .name = "gpll7",
150 .parent_data = &(const struct clk_parent_data){
151 .fw_name = "bi_tcxo",
152 .name = "bi_tcxo",
153 },
154 .num_parents = 1,
155 .ops = &clk_alpha_pll_fixed_fabia_ops,
156 },
157 },
158 };
159
160 static const struct parent_map gcc_parent_map_0[] = {
161 { P_BI_TCXO, 0 },
162 { P_GPLL0_OUT_MAIN, 1 },
163 { P_GPLL0_OUT_EVEN, 6 },
164 };
165
166 static const struct clk_parent_data gcc_parent_data_0[] = {
167 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
168 { .hw = &gpll0.clkr.hw },
169 { .hw = &gpll0_out_even.clkr.hw },
170 };
171
172 static const struct clk_parent_data gcc_parent_data_0_ao[] = {
173 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
174 { .hw = &gpll0.clkr.hw },
175 { .hw = &gpll0_out_even.clkr.hw },
176 };
177
178 static const struct parent_map gcc_parent_map_1[] = {
179 { P_BI_TCXO, 0 },
180 { P_GPLL0_OUT_MAIN, 1 },
181 { P_GPLL6_OUT_MAIN, 2 },
182 { P_GPLL0_OUT_EVEN, 6 },
183 };
184
185 static const struct clk_parent_data gcc_parent_data_1[] = {
186 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
187 { .hw = &gpll0.clkr.hw },
188 { .hw = &gpll6.clkr.hw },
189 { .hw = &gpll0_out_even.clkr.hw },
190 };
191
192 static const struct parent_map gcc_parent_map_2[] = {
193 { P_BI_TCXO, 0 },
194 { P_GPLL0_OUT_MAIN, 1 },
195 { P_GPLL1_OUT_MAIN, 4 },
196 { P_GPLL4_OUT_MAIN, 5 },
197 { P_GPLL0_OUT_EVEN, 6 },
198 };
199
200 static const struct clk_parent_data gcc_parent_data_2[] = {
201 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
202 { .hw = &gpll0.clkr.hw },
203 { .hw = &gpll1.clkr.hw },
204 { .hw = &gpll4.clkr.hw },
205 { .hw = &gpll0_out_even.clkr.hw },
206 };
207
208 static const struct parent_map gcc_parent_map_3[] = {
209 { P_BI_TCXO, 0 },
210 { P_GPLL0_OUT_MAIN, 1 },
211 };
212
213 static const struct clk_parent_data gcc_parent_data_3[] = {
214 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
215 { .hw = &gpll0.clkr.hw },
216 };
217
218 static const struct parent_map gcc_parent_map_4[] = {
219 { P_BI_TCXO, 0 },
220 { P_GPLL0_OUT_MAIN, 1 },
221 { P_SLEEP_CLK, 5 },
222 { P_GPLL0_OUT_EVEN, 6 },
223 };
224
225 static const struct clk_parent_data gcc_parent_data_4[] = {
226 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
227 { .hw = &gpll0.clkr.hw },
228 { .fw_name = "sleep_clk", .name = "sleep_clk" },
229 { .hw = &gpll0_out_even.clkr.hw },
230 };
231
232 static const struct parent_map gcc_parent_map_5[] = {
233 { P_BI_TCXO, 0 },
234 { P_GPLL0_OUT_MAIN, 1 },
235 { P_GPLL7_OUT_MAIN, 3 },
236 { P_GPLL0_OUT_EVEN, 6 },
237 };
238
239 static const struct clk_parent_data gcc_parent_data_5[] = {
240 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
241 { .hw = &gpll0.clkr.hw },
242 { .hw = &gpll7.clkr.hw },
243 { .hw = &gpll0_out_even.clkr.hw },
244 };
245
246 static const struct parent_map gcc_parent_map_6[] = {
247 { P_BI_TCXO, 0 },
248 { P_GPLL0_OUT_MAIN, 1 },
249 { P_SLEEP_CLK, 5 },
250 };
251
252 static const struct clk_parent_data gcc_parent_data_6[] = {
253 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
254 { .hw = &gpll0.clkr.hw },
255 { .fw_name = "sleep_clk", .name = "sleep_clk" },
256 };
257
258 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
259 F(19200000, P_BI_TCXO, 1, 0, 0),
260 { }
261 };
262
263 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
264 .cmd_rcgr = 0x48014,
265 .mnd_width = 0,
266 .hid_width = 5,
267 .parent_map = gcc_parent_map_0,
268 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
269 .clkr.hw.init = &(struct clk_init_data){
270 .name = "gcc_cpuss_ahb_clk_src",
271 .parent_data = gcc_parent_data_0_ao,
272 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
273 .flags = CLK_SET_RATE_PARENT,
274 .ops = &clk_rcg2_ops,
275 },
276 };
277
278 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
279 F(19200000, P_BI_TCXO, 1, 0, 0),
280 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
281 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
282 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
283 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
284 { }
285 };
286
287 static struct clk_rcg2 gcc_gp1_clk_src = {
288 .cmd_rcgr = 0x64004,
289 .mnd_width = 8,
290 .hid_width = 5,
291 .parent_map = gcc_parent_map_4,
292 .freq_tbl = ftbl_gcc_gp1_clk_src,
293 .clkr.hw.init = &(struct clk_init_data){
294 .name = "gcc_gp1_clk_src",
295 .parent_data = gcc_parent_data_4,
296 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
297 .ops = &clk_rcg2_ops,
298 },
299 };
300
301 static struct clk_rcg2 gcc_gp2_clk_src = {
302 .cmd_rcgr = 0x65004,
303 .mnd_width = 8,
304 .hid_width = 5,
305 .parent_map = gcc_parent_map_4,
306 .freq_tbl = ftbl_gcc_gp1_clk_src,
307 .clkr.hw.init = &(struct clk_init_data){
308 .name = "gcc_gp2_clk_src",
309 .parent_data = gcc_parent_data_4,
310 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
311 .ops = &clk_rcg2_ops,
312 },
313 };
314
315 static struct clk_rcg2 gcc_gp3_clk_src = {
316 .cmd_rcgr = 0x66004,
317 .mnd_width = 8,
318 .hid_width = 5,
319 .parent_map = gcc_parent_map_4,
320 .freq_tbl = ftbl_gcc_gp1_clk_src,
321 .clkr.hw.init = &(struct clk_init_data){
322 .name = "gcc_gp3_clk_src",
323 .parent_data = gcc_parent_data_4,
324 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
325 .ops = &clk_rcg2_ops,
326 },
327 };
328
329 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
330 F(19200000, P_BI_TCXO, 1, 0, 0),
331 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
332 { }
333 };
334
335 static struct clk_rcg2 gcc_pdm2_clk_src = {
336 .cmd_rcgr = 0x33010,
337 .mnd_width = 0,
338 .hid_width = 5,
339 .parent_map = gcc_parent_map_0,
340 .freq_tbl = ftbl_gcc_pdm2_clk_src,
341 .clkr.hw.init = &(struct clk_init_data){
342 .name = "gcc_pdm2_clk_src",
343 .parent_data = gcc_parent_data_0,
344 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
345 .ops = &clk_rcg2_ops,
346 },
347 };
348
349 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
350 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
351 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
352 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
353 { }
354 };
355
356 static struct clk_rcg2 gcc_qspi_core_clk_src = {
357 .cmd_rcgr = 0x4b00c,
358 .mnd_width = 0,
359 .hid_width = 5,
360 .parent_map = gcc_parent_map_2,
361 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
362 .clkr.hw.init = &(struct clk_init_data){
363 .name = "gcc_qspi_core_clk_src",
364 .parent_data = gcc_parent_data_2,
365 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
366 .ops = &clk_rcg2_ops,
367 },
368 };
369
370 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
371 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
372 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
373 F(19200000, P_BI_TCXO, 1, 0, 0),
374 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
375 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
376 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
377 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
378 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
379 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
380 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
381 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
382 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
383 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
384 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
385 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
386 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
387 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
388 { }
389 };
390
391 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
392 .name = "gcc_qupv3_wrap0_s0_clk_src",
393 .parent_data = gcc_parent_data_1,
394 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
395 .ops = &clk_rcg2_ops,
396 };
397
398 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
399 .cmd_rcgr = 0x17034,
400 .mnd_width = 16,
401 .hid_width = 5,
402 .parent_map = gcc_parent_map_1,
403 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
404 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
405 };
406
407 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
408 .name = "gcc_qupv3_wrap0_s1_clk_src",
409 .parent_data = gcc_parent_data_1,
410 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
411 .ops = &clk_rcg2_ops,
412 };
413
414 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
415 .cmd_rcgr = 0x17164,
416 .mnd_width = 16,
417 .hid_width = 5,
418 .parent_map = gcc_parent_map_1,
419 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
420 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
421 };
422
423 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
424 .name = "gcc_qupv3_wrap0_s2_clk_src",
425 .parent_data = gcc_parent_data_1,
426 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
427 .ops = &clk_rcg2_ops,
428 };
429
430 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
431 .cmd_rcgr = 0x17294,
432 .mnd_width = 16,
433 .hid_width = 5,
434 .parent_map = gcc_parent_map_1,
435 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
436 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
437 };
438
439 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
440 .name = "gcc_qupv3_wrap0_s3_clk_src",
441 .parent_data = gcc_parent_data_1,
442 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
443 .ops = &clk_rcg2_ops,
444 };
445
446 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
447 .cmd_rcgr = 0x173c4,
448 .mnd_width = 16,
449 .hid_width = 5,
450 .parent_map = gcc_parent_map_1,
451 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
452 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
453 };
454
455 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
456 .name = "gcc_qupv3_wrap0_s4_clk_src",
457 .parent_data = gcc_parent_data_1,
458 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
459 .ops = &clk_rcg2_ops,
460 };
461
462 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
463 .cmd_rcgr = 0x174f4,
464 .mnd_width = 16,
465 .hid_width = 5,
466 .parent_map = gcc_parent_map_1,
467 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
468 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
469 };
470
471 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
472 .name = "gcc_qupv3_wrap0_s5_clk_src",
473 .parent_data = gcc_parent_data_1,
474 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
475 .ops = &clk_rcg2_ops,
476 };
477
478 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
479 .cmd_rcgr = 0x17624,
480 .mnd_width = 16,
481 .hid_width = 5,
482 .parent_map = gcc_parent_map_1,
483 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
484 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
485 };
486
487 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
488 .name = "gcc_qupv3_wrap1_s0_clk_src",
489 .parent_data = gcc_parent_data_1,
490 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
491 .ops = &clk_rcg2_ops,
492 };
493
494 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
495 .cmd_rcgr = 0x18018,
496 .mnd_width = 16,
497 .hid_width = 5,
498 .parent_map = gcc_parent_map_1,
499 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
500 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
501 };
502
503 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
504 .name = "gcc_qupv3_wrap1_s1_clk_src",
505 .parent_data = gcc_parent_data_1,
506 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
507 .ops = &clk_rcg2_ops,
508 };
509
510 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
511 .cmd_rcgr = 0x18148,
512 .mnd_width = 16,
513 .hid_width = 5,
514 .parent_map = gcc_parent_map_1,
515 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
516 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
517 };
518
519 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
520 .name = "gcc_qupv3_wrap1_s2_clk_src",
521 .parent_data = gcc_parent_data_1,
522 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
523 .ops = &clk_rcg2_ops,
524 };
525
526 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
527 .cmd_rcgr = 0x18278,
528 .mnd_width = 16,
529 .hid_width = 5,
530 .parent_map = gcc_parent_map_1,
531 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
532 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
533 };
534
535 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
536 .name = "gcc_qupv3_wrap1_s3_clk_src",
537 .parent_data = gcc_parent_data_1,
538 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
539 .ops = &clk_rcg2_ops,
540 };
541
542 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
543 .cmd_rcgr = 0x183a8,
544 .mnd_width = 16,
545 .hid_width = 5,
546 .parent_map = gcc_parent_map_1,
547 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
548 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
549 };
550
551 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
552 .name = "gcc_qupv3_wrap1_s4_clk_src",
553 .parent_data = gcc_parent_data_1,
554 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
555 .ops = &clk_rcg2_ops,
556 };
557
558 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
559 .cmd_rcgr = 0x184d8,
560 .mnd_width = 16,
561 .hid_width = 5,
562 .parent_map = gcc_parent_map_1,
563 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
564 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
565 };
566
567 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
568 .name = "gcc_qupv3_wrap1_s5_clk_src",
569 .parent_data = gcc_parent_data_1,
570 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
571 .ops = &clk_rcg2_ops,
572 };
573
574 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
575 .cmd_rcgr = 0x18608,
576 .mnd_width = 16,
577 .hid_width = 5,
578 .parent_map = gcc_parent_map_1,
579 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
580 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
581 };
582
583
584 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
585 F(144000, P_BI_TCXO, 16, 3, 25),
586 F(400000, P_BI_TCXO, 12, 1, 4),
587 F(19200000, P_BI_TCXO, 1, 0, 0),
588 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
589 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
590 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
591 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
592 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
593 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
594 { }
595 };
596
597 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
598 .cmd_rcgr = 0x12028,
599 .mnd_width = 8,
600 .hid_width = 5,
601 .parent_map = gcc_parent_map_1,
602 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
603 .clkr.hw.init = &(struct clk_init_data){
604 .name = "gcc_sdcc1_apps_clk_src",
605 .parent_data = gcc_parent_data_1,
606 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
607 .ops = &clk_rcg2_floor_ops,
608 },
609 };
610
611 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
612 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
613 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
614 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
615 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
616 { }
617 };
618
619 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
620 .cmd_rcgr = 0x12010,
621 .mnd_width = 0,
622 .hid_width = 5,
623 .parent_map = gcc_parent_map_0,
624 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "gcc_sdcc1_ice_core_clk_src",
627 .parent_data = gcc_parent_data_0,
628 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
629 .ops = &clk_rcg2_ops,
630 },
631 };
632
633 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
634 F(400000, P_BI_TCXO, 12, 1, 4),
635 F(9600000, P_BI_TCXO, 2, 0, 0),
636 F(19200000, P_BI_TCXO, 1, 0, 0),
637 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
638 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
639 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
640 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
641 { }
642 };
643
644 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
645 .cmd_rcgr = 0x1400c,
646 .mnd_width = 8,
647 .hid_width = 5,
648 .parent_map = gcc_parent_map_5,
649 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
650 .clkr.hw.init = &(struct clk_init_data){
651 .name = "gcc_sdcc2_apps_clk_src",
652 .parent_data = gcc_parent_data_5,
653 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
654 .flags = CLK_OPS_PARENT_ENABLE,
655 .ops = &clk_rcg2_floor_ops,
656 },
657 };
658
659 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
660 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
661 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
662 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
663 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
664 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
665 { }
666 };
667
668 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
669 .cmd_rcgr = 0x77020,
670 .mnd_width = 8,
671 .hid_width = 5,
672 .parent_map = gcc_parent_map_0,
673 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
674 .clkr.hw.init = &(struct clk_init_data){
675 .name = "gcc_ufs_phy_axi_clk_src",
676 .parent_data = gcc_parent_data_0,
677 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
678 .ops = &clk_rcg2_ops,
679 },
680 };
681
682 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
683 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
684 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
685 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
686 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
687 { }
688 };
689
690 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
691 .cmd_rcgr = 0x77048,
692 .mnd_width = 0,
693 .hid_width = 5,
694 .parent_map = gcc_parent_map_0,
695 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
696 .clkr.hw.init = &(struct clk_init_data){
697 .name = "gcc_ufs_phy_ice_core_clk_src",
698 .parent_data = gcc_parent_data_0,
699 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
700 .ops = &clk_rcg2_ops,
701 },
702 };
703
704 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
705 F(9600000, P_BI_TCXO, 2, 0, 0),
706 F(19200000, P_BI_TCXO, 1, 0, 0),
707 { }
708 };
709
710 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
711 .cmd_rcgr = 0x77098,
712 .mnd_width = 0,
713 .hid_width = 5,
714 .parent_map = gcc_parent_map_3,
715 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
716 .clkr.hw.init = &(struct clk_init_data){
717 .name = "gcc_ufs_phy_phy_aux_clk_src",
718 .parent_data = gcc_parent_data_3,
719 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
720 .ops = &clk_rcg2_ops,
721 },
722 };
723
724 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
725 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
726 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
727 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
728 { }
729 };
730
731 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
732 .cmd_rcgr = 0x77060,
733 .mnd_width = 0,
734 .hid_width = 5,
735 .parent_map = gcc_parent_map_0,
736 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
737 .clkr.hw.init = &(struct clk_init_data){
738 .name = "gcc_ufs_phy_unipro_core_clk_src",
739 .parent_data = gcc_parent_data_0,
740 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
741 .ops = &clk_rcg2_ops,
742 },
743 };
744
745 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
746 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
747 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
748 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
749 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
750 { }
751 };
752
753 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
754 .cmd_rcgr = 0xf01c,
755 .mnd_width = 8,
756 .hid_width = 5,
757 .parent_map = gcc_parent_map_0,
758 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
759 .clkr.hw.init = &(struct clk_init_data){
760 .name = "gcc_usb30_prim_master_clk_src",
761 .parent_data = gcc_parent_data_0,
762 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
763 .ops = &clk_rcg2_ops,
764 },
765 };
766
767 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
768 F(19200000, P_BI_TCXO, 1, 0, 0),
769 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
770 { }
771 };
772
773 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
774 .cmd_rcgr = 0xf034,
775 .mnd_width = 0,
776 .hid_width = 5,
777 .parent_map = gcc_parent_map_0,
778 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
779 .clkr.hw.init = &(struct clk_init_data){
780 .name = "gcc_usb30_prim_mock_utmi_clk_src",
781 .parent_data = gcc_parent_data_0,
782 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
783 .ops = &clk_rcg2_ops,
784 },
785 };
786
787 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
788 F(19200000, P_BI_TCXO, 1, 0, 0),
789 { }
790 };
791
792 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
793 .cmd_rcgr = 0xf060,
794 .mnd_width = 0,
795 .hid_width = 5,
796 .parent_map = gcc_parent_map_6,
797 .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
798 .clkr.hw.init = &(struct clk_init_data){
799 .name = "gcc_usb3_prim_phy_aux_clk_src",
800 .parent_data = gcc_parent_data_6,
801 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
802 .ops = &clk_rcg2_ops,
803 },
804 };
805
806 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
807 F(4800000, P_BI_TCXO, 4, 0, 0),
808 F(19200000, P_BI_TCXO, 1, 0, 0),
809 { }
810 };
811
812 static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
813 .cmd_rcgr = 0x3d030,
814 .mnd_width = 0,
815 .hid_width = 5,
816 .parent_map = gcc_parent_map_3,
817 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
818 .clkr.hw.init = &(struct clk_init_data){
819 .name = "gcc_sec_ctrl_clk_src",
820 .parent_data = gcc_parent_data_3,
821 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
822 .ops = &clk_rcg2_ops,
823 },
824 };
825
826 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
827 .halt_reg = 0x82024,
828 .halt_check = BRANCH_HALT_DELAY,
829 .hwcg_reg = 0x82024,
830 .hwcg_bit = 1,
831 .clkr = {
832 .enable_reg = 0x82024,
833 .enable_mask = BIT(0),
834 .hw.init = &(struct clk_init_data){
835 .name = "gcc_aggre_ufs_phy_axi_clk",
836 .parent_hws = (const struct clk_hw*[]){
837 &gcc_ufs_phy_axi_clk_src.clkr.hw,
838 },
839 .num_parents = 1,
840 .flags = CLK_SET_RATE_PARENT,
841 .ops = &clk_branch2_ops,
842 },
843 },
844 };
845
846 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
847 .halt_reg = 0x8201c,
848 .halt_check = BRANCH_HALT,
849 .clkr = {
850 .enable_reg = 0x8201c,
851 .enable_mask = BIT(0),
852 .hw.init = &(struct clk_init_data){
853 .name = "gcc_aggre_usb3_prim_axi_clk",
854 .parent_hws = (const struct clk_hw*[]){
855 &gcc_usb30_prim_master_clk_src.clkr.hw,
856 },
857 .num_parents = 1,
858 .flags = CLK_SET_RATE_PARENT,
859 .ops = &clk_branch2_ops,
860 },
861 },
862 };
863
864 static struct clk_branch gcc_boot_rom_ahb_clk = {
865 .halt_reg = 0x38004,
866 .halt_check = BRANCH_HALT_VOTED,
867 .hwcg_reg = 0x38004,
868 .hwcg_bit = 1,
869 .clkr = {
870 .enable_reg = 0x52000,
871 .enable_mask = BIT(10),
872 .hw.init = &(struct clk_init_data){
873 .name = "gcc_boot_rom_ahb_clk",
874 .ops = &clk_branch2_ops,
875 },
876 },
877 };
878
879 static struct clk_branch gcc_camera_hf_axi_clk = {
880 .halt_reg = 0xb020,
881 .halt_check = BRANCH_HALT,
882 .clkr = {
883 .enable_reg = 0xb020,
884 .enable_mask = BIT(0),
885 .hw.init = &(struct clk_init_data){
886 .name = "gcc_camera_hf_axi_clk",
887 .ops = &clk_branch2_ops,
888 },
889 },
890 };
891
892 static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
893 .halt_reg = 0xb080,
894 .halt_check = BRANCH_HALT,
895 .hwcg_reg = 0xb080,
896 .hwcg_bit = 1,
897 .clkr = {
898 .enable_reg = 0xb080,
899 .enable_mask = BIT(0),
900 .hw.init = &(struct clk_init_data){
901 .name = "gcc_camera_throttle_hf_axi_clk",
902 .ops = &clk_branch2_ops,
903 },
904 },
905 };
906
907 static struct clk_branch gcc_ce1_ahb_clk = {
908 .halt_reg = 0x4100c,
909 .halt_check = BRANCH_HALT_VOTED,
910 .hwcg_reg = 0x4100c,
911 .hwcg_bit = 1,
912 .clkr = {
913 .enable_reg = 0x52000,
914 .enable_mask = BIT(3),
915 .hw.init = &(struct clk_init_data){
916 .name = "gcc_ce1_ahb_clk",
917 .ops = &clk_branch2_ops,
918 },
919 },
920 };
921
922 static struct clk_branch gcc_ce1_axi_clk = {
923 .halt_reg = 0x41008,
924 .halt_check = BRANCH_HALT_VOTED,
925 .clkr = {
926 .enable_reg = 0x52000,
927 .enable_mask = BIT(4),
928 .hw.init = &(struct clk_init_data){
929 .name = "gcc_ce1_axi_clk",
930 .ops = &clk_branch2_ops,
931 },
932 },
933 };
934
935 static struct clk_branch gcc_ce1_clk = {
936 .halt_reg = 0x41004,
937 .halt_check = BRANCH_HALT_VOTED,
938 .clkr = {
939 .enable_reg = 0x52000,
940 .enable_mask = BIT(5),
941 .hw.init = &(struct clk_init_data){
942 .name = "gcc_ce1_clk",
943 .ops = &clk_branch2_ops,
944 },
945 },
946 };
947
948 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
949 .halt_reg = 0x502c,
950 .halt_check = BRANCH_HALT,
951 .clkr = {
952 .enable_reg = 0x502c,
953 .enable_mask = BIT(0),
954 .hw.init = &(struct clk_init_data){
955 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
956 .parent_hws = (const struct clk_hw*[]){
957 &gcc_usb30_prim_master_clk_src.clkr.hw,
958 },
959 .num_parents = 1,
960 .flags = CLK_SET_RATE_PARENT,
961 .ops = &clk_branch2_ops,
962 },
963 },
964 };
965
966 /* For CPUSS functionality the AHB clock needs to be left enabled */
967 static struct clk_branch gcc_cpuss_ahb_clk = {
968 .halt_reg = 0x48000,
969 .halt_check = BRANCH_HALT_VOTED,
970 .clkr = {
971 .enable_reg = 0x52000,
972 .enable_mask = BIT(21),
973 .hw.init = &(struct clk_init_data){
974 .name = "gcc_cpuss_ahb_clk",
975 .parent_hws = (const struct clk_hw*[]){
976 &gcc_cpuss_ahb_clk_src.clkr.hw,
977 },
978 .num_parents = 1,
979 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
980 .ops = &clk_branch2_ops,
981 },
982 },
983 };
984
985 static struct clk_branch gcc_cpuss_rbcpr_clk = {
986 .halt_reg = 0x48008,
987 .halt_check = BRANCH_HALT,
988 .clkr = {
989 .enable_reg = 0x48008,
990 .enable_mask = BIT(0),
991 .hw.init = &(struct clk_init_data){
992 .name = "gcc_cpuss_rbcpr_clk",
993 .ops = &clk_branch2_ops,
994 },
995 },
996 };
997
998 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
999 .halt_reg = 0x4452c,
1000 .halt_check = BRANCH_VOTED,
1001 .clkr = {
1002 .enable_reg = 0x4452c,
1003 .enable_mask = BIT(0),
1004 .hw.init = &(struct clk_init_data){
1005 .name = "gcc_ddrss_gpu_axi_clk",
1006 .ops = &clk_branch2_ops,
1007 },
1008 },
1009 };
1010
1011 static struct clk_branch gcc_disp_gpll0_clk_src = {
1012 .halt_check = BRANCH_HALT_DELAY,
1013 .clkr = {
1014 .enable_reg = 0x52000,
1015 .enable_mask = BIT(18),
1016 .hw.init = &(struct clk_init_data){
1017 .name = "gcc_disp_gpll0_clk_src",
1018 .parent_hws = (const struct clk_hw*[]){
1019 &gpll0.clkr.hw,
1020 },
1021 .num_parents = 1,
1022 .ops = &clk_branch2_aon_ops,
1023 },
1024 },
1025 };
1026
1027 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1028 .halt_check = BRANCH_HALT_DELAY,
1029 .clkr = {
1030 .enable_reg = 0x52000,
1031 .enable_mask = BIT(19),
1032 .hw.init = &(struct clk_init_data){
1033 .name = "gcc_disp_gpll0_div_clk_src",
1034 .parent_hws = (const struct clk_hw*[]){
1035 &gcc_pll0_main_div_cdiv.hw,
1036 },
1037 .num_parents = 1,
1038 .ops = &clk_branch2_ops,
1039 },
1040 },
1041 };
1042
1043 static struct clk_branch gcc_disp_hf_axi_clk = {
1044 .halt_reg = 0xb024,
1045 .halt_check = BRANCH_HALT,
1046 .clkr = {
1047 .enable_reg = 0xb024,
1048 .enable_mask = BIT(0),
1049 .hw.init = &(struct clk_init_data){
1050 .name = "gcc_disp_hf_axi_clk",
1051 .ops = &clk_branch2_ops,
1052 },
1053 },
1054 };
1055
1056 static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
1057 .halt_reg = 0xb084,
1058 .halt_check = BRANCH_HALT,
1059 .hwcg_reg = 0xb084,
1060 .hwcg_bit = 1,
1061 .clkr = {
1062 .enable_reg = 0xb084,
1063 .enable_mask = BIT(0),
1064 .hw.init = &(struct clk_init_data){
1065 .name = "gcc_disp_throttle_hf_axi_clk",
1066 .ops = &clk_branch2_ops,
1067 },
1068 },
1069 };
1070
1071 static struct clk_branch gcc_gp1_clk = {
1072 .halt_reg = 0x64000,
1073 .halt_check = BRANCH_HALT,
1074 .clkr = {
1075 .enable_reg = 0x64000,
1076 .enable_mask = BIT(0),
1077 .hw.init = &(struct clk_init_data){
1078 .name = "gcc_gp1_clk",
1079 .parent_hws = (const struct clk_hw*[]){
1080 &gcc_gp1_clk_src.clkr.hw,
1081 },
1082 .num_parents = 1,
1083 .flags = CLK_SET_RATE_PARENT,
1084 .ops = &clk_branch2_ops,
1085 },
1086 },
1087 };
1088
1089 static struct clk_branch gcc_gp2_clk = {
1090 .halt_reg = 0x65000,
1091 .halt_check = BRANCH_HALT,
1092 .clkr = {
1093 .enable_reg = 0x65000,
1094 .enable_mask = BIT(0),
1095 .hw.init = &(struct clk_init_data){
1096 .name = "gcc_gp2_clk",
1097 .parent_hws = (const struct clk_hw*[]){
1098 &gcc_gp2_clk_src.clkr.hw,
1099 },
1100 .num_parents = 1,
1101 .flags = CLK_SET_RATE_PARENT,
1102 .ops = &clk_branch2_ops,
1103 },
1104 },
1105 };
1106
1107 static struct clk_branch gcc_gp3_clk = {
1108 .halt_reg = 0x66000,
1109 .halt_check = BRANCH_HALT,
1110 .clkr = {
1111 .enable_reg = 0x66000,
1112 .enable_mask = BIT(0),
1113 .hw.init = &(struct clk_init_data){
1114 .name = "gcc_gp3_clk",
1115 .parent_hws = (const struct clk_hw*[]){
1116 &gcc_gp3_clk_src.clkr.hw,
1117 },
1118 .num_parents = 1,
1119 .flags = CLK_SET_RATE_PARENT,
1120 .ops = &clk_branch2_ops,
1121 },
1122 },
1123 };
1124
1125 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1126 .halt_check = BRANCH_HALT_DELAY,
1127 .clkr = {
1128 .enable_reg = 0x52000,
1129 .enable_mask = BIT(15),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "gcc_gpu_gpll0_clk_src",
1132 .parent_hws = (const struct clk_hw*[]){
1133 &gpll0.clkr.hw,
1134 },
1135 .num_parents = 1,
1136 .ops = &clk_branch2_ops,
1137 },
1138 },
1139 };
1140
1141 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1142 .halt_check = BRANCH_HALT_DELAY,
1143 .clkr = {
1144 .enable_reg = 0x52000,
1145 .enable_mask = BIT(16),
1146 .hw.init = &(struct clk_init_data){
1147 .name = "gcc_gpu_gpll0_div_clk_src",
1148 .parent_hws = (const struct clk_hw*[]){
1149 &gcc_pll0_main_div_cdiv.hw,
1150 },
1151 .num_parents = 1,
1152 .ops = &clk_branch2_ops,
1153 },
1154 },
1155 };
1156
1157 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1158 .halt_reg = 0x7100c,
1159 .halt_check = BRANCH_VOTED,
1160 .clkr = {
1161 .enable_reg = 0x7100c,
1162 .enable_mask = BIT(0),
1163 .hw.init = &(struct clk_init_data){
1164 .name = "gcc_gpu_memnoc_gfx_clk",
1165 .ops = &clk_branch2_ops,
1166 },
1167 },
1168 };
1169
1170 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1171 .halt_reg = 0x71018,
1172 .halt_check = BRANCH_HALT,
1173 .clkr = {
1174 .enable_reg = 0x71018,
1175 .enable_mask = BIT(0),
1176 .hw.init = &(struct clk_init_data){
1177 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1178 .ops = &clk_branch2_ops,
1179 },
1180 },
1181 };
1182
1183 static struct clk_branch gcc_npu_axi_clk = {
1184 .halt_reg = 0x4d008,
1185 .halt_check = BRANCH_HALT,
1186 .clkr = {
1187 .enable_reg = 0x4d008,
1188 .enable_mask = BIT(0),
1189 .hw.init = &(struct clk_init_data){
1190 .name = "gcc_npu_axi_clk",
1191 .ops = &clk_branch2_ops,
1192 },
1193 },
1194 };
1195
1196 static struct clk_branch gcc_npu_bwmon_axi_clk = {
1197 .halt_reg = 0x73008,
1198 .halt_check = BRANCH_HALT,
1199 .clkr = {
1200 .enable_reg = 0x73008,
1201 .enable_mask = BIT(0),
1202 .hw.init = &(struct clk_init_data){
1203 .name = "gcc_npu_bwmon_axi_clk",
1204 .ops = &clk_branch2_ops,
1205 },
1206 },
1207 };
1208
1209 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
1210 .halt_reg = 0x73018,
1211 .halt_check = BRANCH_HALT,
1212 .clkr = {
1213 .enable_reg = 0x73018,
1214 .enable_mask = BIT(0),
1215 .hw.init = &(struct clk_init_data){
1216 .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
1217 .ops = &clk_branch2_ops,
1218 },
1219 },
1220 };
1221
1222 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
1223 .halt_reg = 0x7301c,
1224 .halt_check = BRANCH_HALT,
1225 .clkr = {
1226 .enable_reg = 0x7301c,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1230 .ops = &clk_branch2_ops,
1231 },
1232 },
1233 };
1234
1235 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1236 .halt_reg = 0x4d004,
1237 .halt_check = BRANCH_HALT,
1238 .hwcg_reg = 0x4d004,
1239 .hwcg_bit = 1,
1240 .clkr = {
1241 .enable_reg = 0x4d004,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "gcc_npu_cfg_ahb_clk",
1245 .ops = &clk_branch2_ops,
1246 },
1247 },
1248 };
1249
1250 static struct clk_branch gcc_npu_dma_clk = {
1251 .halt_reg = 0x4d1a0,
1252 .halt_check = BRANCH_HALT,
1253 .hwcg_reg = 0x4d1a0,
1254 .hwcg_bit = 1,
1255 .clkr = {
1256 .enable_reg = 0x4d1a0,
1257 .enable_mask = BIT(0),
1258 .hw.init = &(struct clk_init_data){
1259 .name = "gcc_npu_dma_clk",
1260 .ops = &clk_branch2_ops,
1261 },
1262 },
1263 };
1264
1265 static struct clk_branch gcc_npu_gpll0_clk_src = {
1266 .halt_check = BRANCH_HALT_DELAY,
1267 .clkr = {
1268 .enable_reg = 0x52000,
1269 .enable_mask = BIT(25),
1270 .hw.init = &(struct clk_init_data){
1271 .name = "gcc_npu_gpll0_clk_src",
1272 .parent_hws = (const struct clk_hw*[]){
1273 &gpll0.clkr.hw,
1274 },
1275 .num_parents = 1,
1276 .ops = &clk_branch2_ops,
1277 },
1278 },
1279 };
1280
1281 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1282 .halt_check = BRANCH_HALT_DELAY,
1283 .clkr = {
1284 .enable_reg = 0x52000,
1285 .enable_mask = BIT(26),
1286 .hw.init = &(struct clk_init_data){
1287 .name = "gcc_npu_gpll0_div_clk_src",
1288 .parent_hws = (const struct clk_hw*[]){
1289 &gcc_pll0_main_div_cdiv.hw,
1290 },
1291 .num_parents = 1,
1292 .flags = CLK_SET_RATE_PARENT,
1293 .ops = &clk_branch2_ops,
1294 },
1295 },
1296 };
1297
1298 static struct clk_branch gcc_pdm2_clk = {
1299 .halt_reg = 0x3300c,
1300 .halt_check = BRANCH_HALT,
1301 .clkr = {
1302 .enable_reg = 0x3300c,
1303 .enable_mask = BIT(0),
1304 .hw.init = &(struct clk_init_data){
1305 .name = "gcc_pdm2_clk",
1306 .parent_hws = (const struct clk_hw*[]){
1307 &gcc_pdm2_clk_src.clkr.hw,
1308 },
1309 .num_parents = 1,
1310 .flags = CLK_SET_RATE_PARENT,
1311 .ops = &clk_branch2_ops,
1312 },
1313 },
1314 };
1315
1316 static struct clk_branch gcc_pdm_ahb_clk = {
1317 .halt_reg = 0x33004,
1318 .halt_check = BRANCH_HALT,
1319 .hwcg_reg = 0x33004,
1320 .hwcg_bit = 1,
1321 .clkr = {
1322 .enable_reg = 0x33004,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data){
1325 .name = "gcc_pdm_ahb_clk",
1326 .ops = &clk_branch2_ops,
1327 },
1328 },
1329 };
1330
1331 static struct clk_branch gcc_pdm_xo4_clk = {
1332 .halt_reg = 0x33008,
1333 .halt_check = BRANCH_HALT,
1334 .clkr = {
1335 .enable_reg = 0x33008,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "gcc_pdm_xo4_clk",
1339 .ops = &clk_branch2_ops,
1340 },
1341 },
1342 };
1343
1344 static struct clk_branch gcc_prng_ahb_clk = {
1345 .halt_reg = 0x34004,
1346 .halt_check = BRANCH_HALT_VOTED,
1347 .hwcg_reg = 0x34004,
1348 .hwcg_bit = 1,
1349 .clkr = {
1350 .enable_reg = 0x52000,
1351 .enable_mask = BIT(13),
1352 .hw.init = &(struct clk_init_data){
1353 .name = "gcc_prng_ahb_clk",
1354 .ops = &clk_branch2_ops,
1355 },
1356 },
1357 };
1358
1359 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1360 .halt_reg = 0x4b004,
1361 .halt_check = BRANCH_HALT,
1362 .hwcg_reg = 0x4b004,
1363 .hwcg_bit = 1,
1364 .clkr = {
1365 .enable_reg = 0x4b004,
1366 .enable_mask = BIT(0),
1367 .hw.init = &(struct clk_init_data){
1368 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1369 .ops = &clk_branch2_ops,
1370 },
1371 },
1372 };
1373
1374 static struct clk_branch gcc_qspi_core_clk = {
1375 .halt_reg = 0x4b008,
1376 .halt_check = BRANCH_HALT,
1377 .clkr = {
1378 .enable_reg = 0x4b008,
1379 .enable_mask = BIT(0),
1380 .hw.init = &(struct clk_init_data){
1381 .name = "gcc_qspi_core_clk",
1382 .parent_hws = (const struct clk_hw*[]){
1383 &gcc_qspi_core_clk_src.clkr.hw,
1384 },
1385 .num_parents = 1,
1386 .flags = CLK_SET_RATE_PARENT,
1387 .ops = &clk_branch2_ops,
1388 },
1389 },
1390 };
1391
1392 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1393 .halt_reg = 0x17014,
1394 .halt_check = BRANCH_HALT_VOTED,
1395 .clkr = {
1396 .enable_reg = 0x52008,
1397 .enable_mask = BIT(9),
1398 .hw.init = &(struct clk_init_data){
1399 .name = "gcc_qupv3_wrap0_core_2x_clk",
1400 .ops = &clk_branch2_ops,
1401 },
1402 },
1403 };
1404
1405 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1406 .halt_reg = 0x1700c,
1407 .halt_check = BRANCH_HALT_VOTED,
1408 .clkr = {
1409 .enable_reg = 0x52008,
1410 .enable_mask = BIT(8),
1411 .hw.init = &(struct clk_init_data){
1412 .name = "gcc_qupv3_wrap0_core_clk",
1413 .ops = &clk_branch2_ops,
1414 },
1415 },
1416 };
1417
1418 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1419 .halt_reg = 0x17030,
1420 .halt_check = BRANCH_HALT_VOTED,
1421 .clkr = {
1422 .enable_reg = 0x52008,
1423 .enable_mask = BIT(10),
1424 .hw.init = &(struct clk_init_data){
1425 .name = "gcc_qupv3_wrap0_s0_clk",
1426 .parent_hws = (const struct clk_hw*[]){
1427 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1428 },
1429 .num_parents = 1,
1430 .flags = CLK_SET_RATE_PARENT,
1431 .ops = &clk_branch2_ops,
1432 },
1433 },
1434 };
1435
1436 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1437 .halt_reg = 0x17160,
1438 .halt_check = BRANCH_HALT_VOTED,
1439 .clkr = {
1440 .enable_reg = 0x52008,
1441 .enable_mask = BIT(11),
1442 .hw.init = &(struct clk_init_data){
1443 .name = "gcc_qupv3_wrap0_s1_clk",
1444 .parent_hws = (const struct clk_hw*[]){
1445 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1446 },
1447 .num_parents = 1,
1448 .flags = CLK_SET_RATE_PARENT,
1449 .ops = &clk_branch2_ops,
1450 },
1451 },
1452 };
1453
1454 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1455 .halt_reg = 0x17290,
1456 .halt_check = BRANCH_HALT_VOTED,
1457 .clkr = {
1458 .enable_reg = 0x52008,
1459 .enable_mask = BIT(12),
1460 .hw.init = &(struct clk_init_data){
1461 .name = "gcc_qupv3_wrap0_s2_clk",
1462 .parent_hws = (const struct clk_hw*[]){
1463 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1464 },
1465 .num_parents = 1,
1466 .flags = CLK_SET_RATE_PARENT,
1467 .ops = &clk_branch2_ops,
1468 },
1469 },
1470 };
1471
1472 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1473 .halt_reg = 0x173c0,
1474 .halt_check = BRANCH_HALT_VOTED,
1475 .clkr = {
1476 .enable_reg = 0x52008,
1477 .enable_mask = BIT(13),
1478 .hw.init = &(struct clk_init_data){
1479 .name = "gcc_qupv3_wrap0_s3_clk",
1480 .parent_hws = (const struct clk_hw*[]){
1481 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1482 },
1483 .num_parents = 1,
1484 .flags = CLK_SET_RATE_PARENT,
1485 .ops = &clk_branch2_ops,
1486 },
1487 },
1488 };
1489
1490 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1491 .halt_reg = 0x174f0,
1492 .halt_check = BRANCH_HALT_VOTED,
1493 .clkr = {
1494 .enable_reg = 0x52008,
1495 .enable_mask = BIT(14),
1496 .hw.init = &(struct clk_init_data){
1497 .name = "gcc_qupv3_wrap0_s4_clk",
1498 .parent_hws = (const struct clk_hw*[]){
1499 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1500 },
1501 .num_parents = 1,
1502 .flags = CLK_SET_RATE_PARENT,
1503 .ops = &clk_branch2_ops,
1504 },
1505 },
1506 };
1507
1508 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1509 .halt_reg = 0x17620,
1510 .halt_check = BRANCH_HALT_VOTED,
1511 .clkr = {
1512 .enable_reg = 0x52008,
1513 .enable_mask = BIT(15),
1514 .hw.init = &(struct clk_init_data){
1515 .name = "gcc_qupv3_wrap0_s5_clk",
1516 .parent_hws = (const struct clk_hw*[]){
1517 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1518 },
1519 .num_parents = 1,
1520 .flags = CLK_SET_RATE_PARENT,
1521 .ops = &clk_branch2_ops,
1522 },
1523 },
1524 };
1525
1526 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1527 .halt_reg = 0x18004,
1528 .halt_check = BRANCH_HALT_VOTED,
1529 .clkr = {
1530 .enable_reg = 0x52008,
1531 .enable_mask = BIT(18),
1532 .hw.init = &(struct clk_init_data){
1533 .name = "gcc_qupv3_wrap1_core_2x_clk",
1534 .ops = &clk_branch2_ops,
1535 },
1536 },
1537 };
1538
1539 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1540 .halt_reg = 0x18008,
1541 .halt_check = BRANCH_HALT_VOTED,
1542 .clkr = {
1543 .enable_reg = 0x52008,
1544 .enable_mask = BIT(19),
1545 .hw.init = &(struct clk_init_data){
1546 .name = "gcc_qupv3_wrap1_core_clk",
1547 .ops = &clk_branch2_ops,
1548 },
1549 },
1550 };
1551
1552 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1553 .halt_reg = 0x18014,
1554 .halt_check = BRANCH_HALT_VOTED,
1555 .clkr = {
1556 .enable_reg = 0x52008,
1557 .enable_mask = BIT(22),
1558 .hw.init = &(struct clk_init_data){
1559 .name = "gcc_qupv3_wrap1_s0_clk",
1560 .parent_hws = (const struct clk_hw*[]){
1561 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1562 },
1563 .num_parents = 1,
1564 .flags = CLK_SET_RATE_PARENT,
1565 .ops = &clk_branch2_ops,
1566 },
1567 },
1568 };
1569
1570 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1571 .halt_reg = 0x18144,
1572 .halt_check = BRANCH_HALT_VOTED,
1573 .clkr = {
1574 .enable_reg = 0x52008,
1575 .enable_mask = BIT(23),
1576 .hw.init = &(struct clk_init_data){
1577 .name = "gcc_qupv3_wrap1_s1_clk",
1578 .parent_hws = (const struct clk_hw*[]){
1579 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1580 },
1581 .num_parents = 1,
1582 .flags = CLK_SET_RATE_PARENT,
1583 .ops = &clk_branch2_ops,
1584 },
1585 },
1586 };
1587
1588 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1589 .halt_reg = 0x18274,
1590 .halt_check = BRANCH_HALT_VOTED,
1591 .clkr = {
1592 .enable_reg = 0x52008,
1593 .enable_mask = BIT(24),
1594 .hw.init = &(struct clk_init_data){
1595 .name = "gcc_qupv3_wrap1_s2_clk",
1596 .parent_hws = (const struct clk_hw*[]){
1597 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1598 },
1599 .num_parents = 1,
1600 .flags = CLK_SET_RATE_PARENT,
1601 .ops = &clk_branch2_ops,
1602 },
1603 },
1604 };
1605
1606 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1607 .halt_reg = 0x183a4,
1608 .halt_check = BRANCH_HALT_VOTED,
1609 .clkr = {
1610 .enable_reg = 0x52008,
1611 .enable_mask = BIT(25),
1612 .hw.init = &(struct clk_init_data){
1613 .name = "gcc_qupv3_wrap1_s3_clk",
1614 .parent_hws = (const struct clk_hw*[]){
1615 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1616 },
1617 .num_parents = 1,
1618 .flags = CLK_SET_RATE_PARENT,
1619 .ops = &clk_branch2_ops,
1620 },
1621 },
1622 };
1623
1624 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1625 .halt_reg = 0x184d4,
1626 .halt_check = BRANCH_HALT_VOTED,
1627 .clkr = {
1628 .enable_reg = 0x52008,
1629 .enable_mask = BIT(26),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "gcc_qupv3_wrap1_s4_clk",
1632 .parent_hws = (const struct clk_hw*[]){
1633 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1634 },
1635 .num_parents = 1,
1636 .flags = CLK_SET_RATE_PARENT,
1637 .ops = &clk_branch2_ops,
1638 },
1639 },
1640 };
1641
1642 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1643 .halt_reg = 0x18604,
1644 .halt_check = BRANCH_HALT_VOTED,
1645 .clkr = {
1646 .enable_reg = 0x52008,
1647 .enable_mask = BIT(27),
1648 .hw.init = &(struct clk_init_data){
1649 .name = "gcc_qupv3_wrap1_s5_clk",
1650 .parent_hws = (const struct clk_hw*[]){
1651 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1652 },
1653 .num_parents = 1,
1654 .flags = CLK_SET_RATE_PARENT,
1655 .ops = &clk_branch2_ops,
1656 },
1657 },
1658 };
1659
1660 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1661 .halt_reg = 0x17004,
1662 .halt_check = BRANCH_HALT_VOTED,
1663 .clkr = {
1664 .enable_reg = 0x52008,
1665 .enable_mask = BIT(6),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
1668 .ops = &clk_branch2_ops,
1669 },
1670 },
1671 };
1672
1673 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1674 .halt_reg = 0x17008,
1675 .halt_check = BRANCH_HALT_VOTED,
1676 .hwcg_reg = 0x17008,
1677 .hwcg_bit = 1,
1678 .clkr = {
1679 .enable_reg = 0x52008,
1680 .enable_mask = BIT(7),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
1683 .ops = &clk_branch2_ops,
1684 },
1685 },
1686 };
1687
1688 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1689 .halt_reg = 0x1800c,
1690 .halt_check = BRANCH_HALT_VOTED,
1691 .clkr = {
1692 .enable_reg = 0x52008,
1693 .enable_mask = BIT(20),
1694 .hw.init = &(struct clk_init_data){
1695 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
1696 .ops = &clk_branch2_ops,
1697 },
1698 },
1699 };
1700
1701 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1702 .halt_reg = 0x18010,
1703 .halt_check = BRANCH_HALT_VOTED,
1704 .hwcg_reg = 0x18010,
1705 .hwcg_bit = 1,
1706 .clkr = {
1707 .enable_reg = 0x52008,
1708 .enable_mask = BIT(21),
1709 .hw.init = &(struct clk_init_data){
1710 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
1711 .ops = &clk_branch2_ops,
1712 },
1713 },
1714 };
1715
1716 static struct clk_branch gcc_sdcc1_ahb_clk = {
1717 .halt_reg = 0x12008,
1718 .halt_check = BRANCH_HALT,
1719 .clkr = {
1720 .enable_reg = 0x12008,
1721 .enable_mask = BIT(0),
1722 .hw.init = &(struct clk_init_data){
1723 .name = "gcc_sdcc1_ahb_clk",
1724 .ops = &clk_branch2_ops,
1725 },
1726 },
1727 };
1728
1729 static struct clk_branch gcc_sdcc1_apps_clk = {
1730 .halt_reg = 0x1200c,
1731 .halt_check = BRANCH_HALT,
1732 .clkr = {
1733 .enable_reg = 0x1200c,
1734 .enable_mask = BIT(0),
1735 .hw.init = &(struct clk_init_data){
1736 .name = "gcc_sdcc1_apps_clk",
1737 .parent_hws = (const struct clk_hw*[]){
1738 &gcc_sdcc1_apps_clk_src.clkr.hw,
1739 },
1740 .num_parents = 1,
1741 .flags = CLK_SET_RATE_PARENT,
1742 .ops = &clk_branch2_ops,
1743 },
1744 },
1745 };
1746
1747 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1748 .halt_reg = 0x12040,
1749 .halt_check = BRANCH_HALT,
1750 .clkr = {
1751 .enable_reg = 0x12040,
1752 .enable_mask = BIT(0),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "gcc_sdcc1_ice_core_clk",
1755 .parent_hws = (const struct clk_hw*[]){
1756 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
1757 },
1758 .num_parents = 1,
1759 .flags = CLK_SET_RATE_PARENT,
1760 .ops = &clk_branch2_ops,
1761 },
1762 },
1763 };
1764
1765 static struct clk_branch gcc_sdcc2_ahb_clk = {
1766 .halt_reg = 0x14008,
1767 .halt_check = BRANCH_HALT,
1768 .clkr = {
1769 .enable_reg = 0x14008,
1770 .enable_mask = BIT(0),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "gcc_sdcc2_ahb_clk",
1773 .ops = &clk_branch2_ops,
1774 },
1775 },
1776 };
1777
1778 static struct clk_branch gcc_sdcc2_apps_clk = {
1779 .halt_reg = 0x14004,
1780 .halt_check = BRANCH_HALT,
1781 .clkr = {
1782 .enable_reg = 0x14004,
1783 .enable_mask = BIT(0),
1784 .hw.init = &(struct clk_init_data){
1785 .name = "gcc_sdcc2_apps_clk",
1786 .parent_hws = (const struct clk_hw*[]){
1787 &gcc_sdcc2_apps_clk_src.clkr.hw,
1788 },
1789 .num_parents = 1,
1790 .flags = CLK_SET_RATE_PARENT,
1791 .ops = &clk_branch2_ops,
1792 },
1793 },
1794 };
1795
1796 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */
1797 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
1798 .halt_reg = 0x4144,
1799 .halt_check = BRANCH_HALT_VOTED,
1800 .clkr = {
1801 .enable_reg = 0x52000,
1802 .enable_mask = BIT(0),
1803 .hw.init = &(struct clk_init_data){
1804 .name = "gcc_sys_noc_cpuss_ahb_clk",
1805 .parent_hws = (const struct clk_hw*[]){
1806 &gcc_cpuss_ahb_clk_src.clkr.hw,
1807 },
1808 .num_parents = 1,
1809 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1810 .ops = &clk_branch2_ops,
1811 },
1812 },
1813 };
1814
1815 static struct clk_branch gcc_ufs_mem_clkref_clk = {
1816 .halt_reg = 0x8c000,
1817 .halt_check = BRANCH_HALT,
1818 .clkr = {
1819 .enable_reg = 0x8c000,
1820 .enable_mask = BIT(0),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "gcc_ufs_mem_clkref_clk",
1823 .ops = &clk_branch2_ops,
1824 },
1825 },
1826 };
1827
1828 static struct clk_branch gcc_ufs_phy_ahb_clk = {
1829 .halt_reg = 0x77014,
1830 .halt_check = BRANCH_HALT,
1831 .hwcg_reg = 0x77014,
1832 .hwcg_bit = 1,
1833 .clkr = {
1834 .enable_reg = 0x77014,
1835 .enable_mask = BIT(0),
1836 .hw.init = &(struct clk_init_data){
1837 .name = "gcc_ufs_phy_ahb_clk",
1838 .ops = &clk_branch2_ops,
1839 },
1840 },
1841 };
1842
1843 static struct clk_branch gcc_ufs_phy_axi_clk = {
1844 .halt_reg = 0x77038,
1845 .halt_check = BRANCH_HALT,
1846 .hwcg_reg = 0x77038,
1847 .hwcg_bit = 1,
1848 .clkr = {
1849 .enable_reg = 0x77038,
1850 .enable_mask = BIT(0),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "gcc_ufs_phy_axi_clk",
1853 .parent_hws = (const struct clk_hw*[]){
1854 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1855 },
1856 .num_parents = 1,
1857 .flags = CLK_SET_RATE_PARENT,
1858 .ops = &clk_branch2_ops,
1859 },
1860 },
1861 };
1862
1863 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
1864 .halt_reg = 0x77090,
1865 .halt_check = BRANCH_HALT,
1866 .hwcg_reg = 0x77090,
1867 .hwcg_bit = 1,
1868 .clkr = {
1869 .enable_reg = 0x77090,
1870 .enable_mask = BIT(0),
1871 .hw.init = &(struct clk_init_data){
1872 .name = "gcc_ufs_phy_ice_core_clk",
1873 .parent_hws = (const struct clk_hw*[]){
1874 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
1875 },
1876 .num_parents = 1,
1877 .flags = CLK_SET_RATE_PARENT,
1878 .ops = &clk_branch2_ops,
1879 },
1880 },
1881 };
1882
1883 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
1884 .halt_reg = 0x77094,
1885 .halt_check = BRANCH_HALT,
1886 .hwcg_reg = 0x77094,
1887 .hwcg_bit = 1,
1888 .clkr = {
1889 .enable_reg = 0x77094,
1890 .enable_mask = BIT(0),
1891 .hw.init = &(struct clk_init_data){
1892 .name = "gcc_ufs_phy_phy_aux_clk",
1893 .parent_hws = (const struct clk_hw*[]){
1894 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
1895 },
1896 .num_parents = 1,
1897 .flags = CLK_SET_RATE_PARENT,
1898 .ops = &clk_branch2_ops,
1899 },
1900 },
1901 };
1902
1903 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
1904 .halt_reg = 0x7701c,
1905 .halt_check = BRANCH_HALT_SKIP,
1906 .clkr = {
1907 .enable_reg = 0x7701c,
1908 .enable_mask = BIT(0),
1909 .hw.init = &(struct clk_init_data){
1910 .name = "gcc_ufs_phy_rx_symbol_0_clk",
1911 .ops = &clk_branch2_ops,
1912 },
1913 },
1914 };
1915
1916 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
1917 .halt_reg = 0x77018,
1918 .halt_check = BRANCH_HALT_SKIP,
1919 .clkr = {
1920 .enable_reg = 0x77018,
1921 .enable_mask = BIT(0),
1922 .hw.init = &(struct clk_init_data){
1923 .name = "gcc_ufs_phy_tx_symbol_0_clk",
1924 .ops = &clk_branch2_ops,
1925 },
1926 },
1927 };
1928
1929 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
1930 .halt_reg = 0x7708c,
1931 .halt_check = BRANCH_HALT,
1932 .hwcg_reg = 0x7708c,
1933 .hwcg_bit = 1,
1934 .clkr = {
1935 .enable_reg = 0x7708c,
1936 .enable_mask = BIT(0),
1937 .hw.init = &(struct clk_init_data){
1938 .name = "gcc_ufs_phy_unipro_core_clk",
1939 .parent_hws = (const struct clk_hw*[]){
1940 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
1941 },
1942 .num_parents = 1,
1943 .flags = CLK_SET_RATE_PARENT,
1944 .ops = &clk_branch2_ops,
1945 },
1946 },
1947 };
1948
1949 static struct clk_branch gcc_usb30_prim_master_clk = {
1950 .halt_reg = 0xf010,
1951 .halt_check = BRANCH_HALT,
1952 .clkr = {
1953 .enable_reg = 0xf010,
1954 .enable_mask = BIT(0),
1955 .hw.init = &(struct clk_init_data){
1956 .name = "gcc_usb30_prim_master_clk",
1957 .parent_hws = (const struct clk_hw*[]){
1958 &gcc_usb30_prim_master_clk_src.clkr.hw,
1959 },
1960 .num_parents = 1,
1961 .flags = CLK_SET_RATE_PARENT,
1962 .ops = &clk_branch2_ops,
1963 },
1964 },
1965 };
1966
1967 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
1968 .halt_reg = 0xf018,
1969 .halt_check = BRANCH_HALT,
1970 .clkr = {
1971 .enable_reg = 0xf018,
1972 .enable_mask = BIT(0),
1973 .hw.init = &(struct clk_init_data){
1974 .name = "gcc_usb30_prim_mock_utmi_clk",
1975 .parent_hws = (const struct clk_hw*[]) {
1976 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1977 },
1978 .num_parents = 1,
1979 .flags = CLK_SET_RATE_PARENT,
1980 .ops = &clk_branch2_ops,
1981 },
1982 },
1983 };
1984
1985 static struct clk_branch gcc_usb30_prim_sleep_clk = {
1986 .halt_reg = 0xf014,
1987 .halt_check = BRANCH_HALT,
1988 .clkr = {
1989 .enable_reg = 0xf014,
1990 .enable_mask = BIT(0),
1991 .hw.init = &(struct clk_init_data){
1992 .name = "gcc_usb30_prim_sleep_clk",
1993 .ops = &clk_branch2_ops,
1994 },
1995 },
1996 };
1997
1998 static struct clk_branch gcc_usb3_prim_clkref_clk = {
1999 .halt_reg = 0x8c010,
2000 .halt_check = BRANCH_HALT,
2001 .clkr = {
2002 .enable_reg = 0x8c010,
2003 .enable_mask = BIT(0),
2004 .hw.init = &(struct clk_init_data){
2005 .name = "gcc_usb3_prim_clkref_clk",
2006 .ops = &clk_branch2_ops,
2007 },
2008 },
2009 };
2010
2011 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2012 .halt_reg = 0xf050,
2013 .halt_check = BRANCH_HALT,
2014 .clkr = {
2015 .enable_reg = 0xf050,
2016 .enable_mask = BIT(0),
2017 .hw.init = &(struct clk_init_data){
2018 .name = "gcc_usb3_prim_phy_aux_clk",
2019 .parent_hws = (const struct clk_hw*[]){
2020 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2021 },
2022 .num_parents = 1,
2023 .flags = CLK_SET_RATE_PARENT,
2024 .ops = &clk_branch2_ops,
2025 },
2026 },
2027 };
2028
2029 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2030 .halt_reg = 0xf054,
2031 .halt_check = BRANCH_HALT,
2032 .clkr = {
2033 .enable_reg = 0xf054,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "gcc_usb3_prim_phy_com_aux_clk",
2037 .parent_hws = (const struct clk_hw*[]){
2038 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2039 },
2040 .num_parents = 1,
2041 .flags = CLK_SET_RATE_PARENT,
2042 .ops = &clk_branch2_ops,
2043 },
2044 },
2045 };
2046
2047 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2048 .halt_reg = 0xf058,
2049 .halt_check = BRANCH_HALT_SKIP,
2050 .clkr = {
2051 .enable_reg = 0xf058,
2052 .enable_mask = BIT(0),
2053 .hw.init = &(struct clk_init_data){
2054 .name = "gcc_usb3_prim_phy_pipe_clk",
2055 .ops = &clk_branch2_ops,
2056 },
2057 },
2058 };
2059
2060 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2061 .halt_reg = 0x6a004,
2062 .halt_check = BRANCH_HALT,
2063 .hwcg_reg = 0x6a004,
2064 .hwcg_bit = 1,
2065 .clkr = {
2066 .enable_reg = 0x6a004,
2067 .enable_mask = BIT(0),
2068 .hw.init = &(struct clk_init_data){
2069 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2070 .ops = &clk_branch2_ops,
2071 },
2072 },
2073 };
2074
2075 static struct clk_branch gcc_video_axi_clk = {
2076 .halt_reg = 0xb01c,
2077 .halt_check = BRANCH_HALT,
2078 .clkr = {
2079 .enable_reg = 0xb01c,
2080 .enable_mask = BIT(0),
2081 .hw.init = &(struct clk_init_data){
2082 .name = "gcc_video_axi_clk",
2083 .ops = &clk_branch2_ops,
2084 },
2085 },
2086 };
2087
2088 static struct clk_branch gcc_video_gpll0_div_clk_src = {
2089 .halt_check = BRANCH_HALT_DELAY,
2090 .clkr = {
2091 .enable_reg = 0x52000,
2092 .enable_mask = BIT(20),
2093 .hw.init = &(struct clk_init_data){
2094 .name = "gcc_video_gpll0_div_clk_src",
2095 .parent_hws = (const struct clk_hw*[]){
2096 &gcc_pll0_main_div_cdiv.hw,
2097 },
2098 .num_parents = 1,
2099 .flags = CLK_SET_RATE_PARENT,
2100 .ops = &clk_branch2_ops,
2101 },
2102 },
2103 };
2104
2105 static struct clk_branch gcc_video_throttle_axi_clk = {
2106 .halt_reg = 0xb07c,
2107 .halt_check = BRANCH_HALT,
2108 .hwcg_reg = 0xb07c,
2109 .hwcg_bit = 1,
2110 .clkr = {
2111 .enable_reg = 0xb07c,
2112 .enable_mask = BIT(0),
2113 .hw.init = &(struct clk_init_data){
2114 .name = "gcc_video_throttle_axi_clk",
2115 .ops = &clk_branch2_ops,
2116 },
2117 },
2118 };
2119
2120 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2121 .halt_reg = 0x8a000,
2122 .halt_check = BRANCH_HALT,
2123 .clkr = {
2124 .enable_reg = 0x8a000,
2125 .enable_mask = BIT(0),
2126 .hw.init = &(struct clk_init_data){
2127 .name = "gcc_mss_cfg_ahb_clk",
2128 .ops = &clk_branch2_ops,
2129 },
2130 },
2131 };
2132
2133 static struct clk_branch gcc_mss_mfab_axis_clk = {
2134 .halt_reg = 0x8a004,
2135 .halt_check = BRANCH_HALT_VOTED,
2136 .clkr = {
2137 .enable_reg = 0x8a004,
2138 .enable_mask = BIT(0),
2139 .hw.init = &(struct clk_init_data){
2140 .name = "gcc_mss_mfab_axis_clk",
2141 .ops = &clk_branch2_ops,
2142 },
2143 },
2144 };
2145
2146 static struct clk_branch gcc_mss_nav_axi_clk = {
2147 .halt_reg = 0x8a00c,
2148 .halt_check = BRANCH_HALT_VOTED,
2149 .clkr = {
2150 .enable_reg = 0x8a00c,
2151 .enable_mask = BIT(0),
2152 .hw.init = &(struct clk_init_data){
2153 .name = "gcc_mss_nav_axi_clk",
2154 .ops = &clk_branch2_ops,
2155 },
2156 },
2157 };
2158
2159 static struct clk_branch gcc_mss_snoc_axi_clk = {
2160 .halt_reg = 0x8a150,
2161 .halt_check = BRANCH_HALT,
2162 .clkr = {
2163 .enable_reg = 0x8a150,
2164 .enable_mask = BIT(0),
2165 .hw.init = &(struct clk_init_data){
2166 .name = "gcc_mss_snoc_axi_clk",
2167 .ops = &clk_branch2_ops,
2168 },
2169 },
2170 };
2171
2172 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
2173 .halt_reg = 0x8a154,
2174 .halt_check = BRANCH_HALT,
2175 .clkr = {
2176 .enable_reg = 0x8a154,
2177 .enable_mask = BIT(0),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "gcc_mss_q6_memnoc_axi_clk",
2180 .ops = &clk_branch2_ops,
2181 },
2182 },
2183 };
2184
2185 static struct clk_branch gcc_lpass_cfg_noc_sway_clk = {
2186 .halt_reg = 0x47018,
2187 .halt_check = BRANCH_HALT_DELAY,
2188 .clkr = {
2189 .enable_reg = 0x47018,
2190 .enable_mask = BIT(0),
2191 .hw.init = &(struct clk_init_data){
2192 .name = "gcc_lpass_cfg_noc_sway_clk",
2193 .ops = &clk_branch2_ops,
2194 },
2195 },
2196 };
2197
2198 static struct gdsc ufs_phy_gdsc = {
2199 .gdscr = 0x77004,
2200 .pd = {
2201 .name = "ufs_phy_gdsc",
2202 },
2203 .pwrsts = PWRSTS_OFF_ON,
2204 };
2205
2206 static struct gdsc usb30_prim_gdsc = {
2207 .gdscr = 0x0f004,
2208 .pd = {
2209 .name = "usb30_prim_gdsc",
2210 },
2211 .pwrsts = PWRSTS_RET_ON,
2212 };
2213
2214 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2215 .gdscr = 0x7d040,
2216 .pd = {
2217 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2218 },
2219 .pwrsts = PWRSTS_OFF_ON,
2220 .flags = VOTABLE,
2221 };
2222
2223 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
2224 .gdscr = 0x7d044,
2225 .pd = {
2226 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
2227 },
2228 .pwrsts = PWRSTS_OFF_ON,
2229 .flags = VOTABLE,
2230 };
2231
2232 static struct gdsc *gcc_sc7180_gdscs[] = {
2233 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2234 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2235 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
2236 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2237 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =
2238 &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
2239 };
2240
2241
2242 static struct clk_hw *gcc_sc7180_hws[] = {
2243 [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
2244 };
2245
2246 static struct clk_regmap *gcc_sc7180_clocks[] = {
2247 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2248 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2249 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2250 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2251 [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
2252 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2253 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2254 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2255 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2256 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2257 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2258 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2259 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2260 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
2261 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2262 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2263 [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
2264 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2265 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2266 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2267 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2268 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2269 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2270 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2271 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2272 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2273 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2274 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2275 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
2276 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
2277 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
2278 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2279 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
2280 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
2281 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
2282 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2283 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2284 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2285 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2286 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2287 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
2288 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
2289 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
2290 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2291 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2292 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2293 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2294 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2295 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2296 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2297 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2298 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2299 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2300 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2301 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2302 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2303 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2304 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2305 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2306 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2307 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2308 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2309 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2310 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2311 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2312 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2313 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2314 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2315 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2316 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2317 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2318 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2319 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2320 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2321 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2322 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2323 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2324 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2325 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2326 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2327 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2328 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2329 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2330 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2331 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2332 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2333 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2334 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2335 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2336 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2337 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2338 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2339 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2340 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2341 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2342 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2343 &gcc_ufs_phy_unipro_core_clk_src.clkr,
2344 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2345 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2346 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2347 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2348 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2349 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2350 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2351 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2352 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2353 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2354 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2355 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2356 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2357 [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
2358 [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
2359 [GPLL0] = &gpll0.clkr,
2360 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2361 [GPLL6] = &gpll6.clkr,
2362 [GPLL7] = &gpll7.clkr,
2363 [GPLL4] = &gpll4.clkr,
2364 [GPLL1] = &gpll1.clkr,
2365 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2366 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
2367 [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
2368 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
2369 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2370 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
2371 [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr,
2372 };
2373
2374 static const struct qcom_reset_map gcc_sc7180_resets[] = {
2375 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2376 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
2377 [GCC_UFS_PHY_BCR] = { 0x77000 },
2378 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2379 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2380 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
2381 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2382 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2383 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
2384 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2385 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2386 };
2387
2388 static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2389 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2390 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2391 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2392 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2393 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2394 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2395 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2396 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2397 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2398 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2399 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2400 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2401 };
2402
2403 static const struct regmap_config gcc_sc7180_regmap_config = {
2404 .reg_bits = 32,
2405 .reg_stride = 4,
2406 .val_bits = 32,
2407 .max_register = 0x18208c,
2408 .fast_io = true,
2409 };
2410
2411 static const struct qcom_cc_desc gcc_sc7180_desc = {
2412 .config = &gcc_sc7180_regmap_config,
2413 .clk_hws = gcc_sc7180_hws,
2414 .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
2415 .clks = gcc_sc7180_clocks,
2416 .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
2417 .resets = gcc_sc7180_resets,
2418 .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
2419 .gdscs = gcc_sc7180_gdscs,
2420 .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
2421 };
2422
2423 static const struct of_device_id gcc_sc7180_match_table[] = {
2424 { .compatible = "qcom,gcc-sc7180" },
2425 { }
2426 };
2427 MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
2428
gcc_sc7180_probe(struct platform_device * pdev)2429 static int gcc_sc7180_probe(struct platform_device *pdev)
2430 {
2431 struct regmap *regmap;
2432 int ret;
2433
2434 regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
2435 if (IS_ERR(regmap))
2436 return PTR_ERR(regmap);
2437
2438 /*
2439 * Disable the GPLL0 active input to MM blocks, NPU
2440 * and GPU via MISC registers.
2441 */
2442 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
2443 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
2444 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
2445
2446 /*
2447 * Keep the clocks always-ON
2448 * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
2449 * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK
2450 */
2451 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
2452 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
2453 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
2454 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
2455 regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
2456 regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
2457 regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
2458 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
2459
2460 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2461 ARRAY_SIZE(gcc_dfs_clocks));
2462 if (ret)
2463 return ret;
2464
2465 return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
2466 }
2467
2468 static struct platform_driver gcc_sc7180_driver = {
2469 .probe = gcc_sc7180_probe,
2470 .driver = {
2471 .name = "gcc-sc7180",
2472 .of_match_table = gcc_sc7180_match_table,
2473 },
2474 };
2475
gcc_sc7180_init(void)2476 static int __init gcc_sc7180_init(void)
2477 {
2478 return platform_driver_register(&gcc_sc7180_driver);
2479 }
2480 core_initcall(gcc_sc7180_init);
2481
gcc_sc7180_exit(void)2482 static void __exit gcc_sc7180_exit(void)
2483 {
2484 platform_driver_unregister(&gcc_sc7180_driver);
2485 }
2486 module_exit(gcc_sc7180_exit);
2487
2488 MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
2489 MODULE_LICENSE("GPL v2");
2490