1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016, Linaro Limited
4 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/err.h>
9 #include <linux/export.h>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/soc/qcom/smd-rpm.h>
17
18 #include <dt-bindings/clock/qcom,rpmcc.h>
19
20 #define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \
21 type, r_id, key, ao_rate, ao_flags) \
22 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \
23 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \
24 .rpm_res_type = (type), \
25 .rpm_clk_id = (r_id), \
26 .rpm_key = (key), \
27 .peer = &clk_smd_rpm_##_prefix##_active, \
28 .rate = INT_MAX, \
29 .hw.init = &(struct clk_init_data){ \
30 .ops = &clk_smd_rpm_ops, \
31 .name = #_name, \
32 .parent_data = &(const struct clk_parent_data){ \
33 .fw_name = "xo", \
34 .name = "xo_board", \
35 }, \
36 .num_parents = 1, \
37 }, \
38 }; \
39 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \
40 .rpm_res_type = (type), \
41 .rpm_clk_id = (r_id), \
42 .active_only = true, \
43 .rpm_key = (key), \
44 .peer = &clk_smd_rpm_##_prefix##_name, \
45 .rate = (ao_rate), \
46 .hw.init = &(struct clk_init_data){ \
47 .ops = &clk_smd_rpm_ops, \
48 .name = #_active, \
49 .parent_data = &(const struct clk_parent_data){ \
50 .fw_name = "xo", \
51 .name = "xo_board", \
52 }, \
53 .num_parents = 1, \
54 .flags = (ao_flags), \
55 }, \
56 }
57
58 #define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key,\
59 ao_rate, ao_flags) \
60 __DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \
61 type, r_id, key, ao_rate, ao_flags)
62
63 #define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\
64 type, r_id, r, key, ao_flags) \
65 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \
66 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \
67 .rpm_res_type = (type), \
68 .rpm_clk_id = (r_id), \
69 .rpm_key = (key), \
70 .branch = true, \
71 .peer = &clk_smd_rpm_##_prefix##_active, \
72 .rate = (r), \
73 .hw.init = &(struct clk_init_data){ \
74 .ops = &clk_smd_rpm_branch_ops, \
75 .name = #_name, \
76 .parent_data = &(const struct clk_parent_data){ \
77 .fw_name = "xo", \
78 .name = "xo_board", \
79 }, \
80 .num_parents = 1, \
81 }, \
82 }; \
83 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \
84 .rpm_res_type = (type), \
85 .rpm_clk_id = (r_id), \
86 .active_only = true, \
87 .rpm_key = (key), \
88 .branch = true, \
89 .peer = &clk_smd_rpm_##_prefix##_name, \
90 .rate = (r), \
91 .hw.init = &(struct clk_init_data){ \
92 .ops = &clk_smd_rpm_branch_ops, \
93 .name = #_active, \
94 .parent_data = &(const struct clk_parent_data){ \
95 .fw_name = "xo", \
96 .name = "xo_board", \
97 }, \
98 .num_parents = 1, \
99 .flags = (ao_flags), \
100 }, \
101 }
102
103 #define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \
104 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \
105 _name, _active, type, r_id, r, key, 0)
106
107 #define DEFINE_CLK_SMD_RPM(_name, type, r_id) \
108 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
109 type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)
110
111 #define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \
112 __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \
113 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
114 QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)
115
116 #define DEFINE_CLK_SMD_RPM_BUS_A(_name, r_id, ao_rate, ao_flags) \
117 __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \
118 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
119 QCOM_RPM_SMD_KEY_RATE, ao_rate, ao_flags)
120
121 #define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \
122 __DEFINE_CLK_SMD_RPM( \
123 _name##_clk_src, _name##_a_clk_src, \
124 type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)
125
126 #define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \
127 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \
128 _name##_clk, _name##_a_clk, \
129 type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE, 0)
130
131 #define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r, ao_flags) \
132 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \
133 _name, _name##_a, type, \
134 r_id, r, QCOM_RPM_SMD_KEY_ENABLE, ao_flags)
135
136 #define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \
137 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
138 type, r_id, QCOM_RPM_SMD_KEY_STATE, INT_MAX, 0)
139
140 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \
141 __DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \
142 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \
143 QCOM_RPM_KEY_SOFTWARE_ENABLE)
144
145 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_prefix, _name, r_id, r) \
146 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \
147 _name, _name##_a, \
148 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \
149 QCOM_RPM_KEY_SOFTWARE_ENABLE, 0)
150
151 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \
152 DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \
153 __DEFINE_CLK_SMD_RPM_BRANCH(_name##_pin, _name##_a##_pin, \
154 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \
155 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
156
157 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
158
159 static struct qcom_smd_rpm *rpmcc_smd_rpm;
160
161 struct clk_smd_rpm {
162 const int rpm_res_type;
163 const int rpm_key;
164 const int rpm_clk_id;
165 const bool active_only;
166 bool enabled;
167 bool branch;
168 struct clk_smd_rpm *peer;
169 struct clk_hw hw;
170 unsigned long rate;
171 };
172
173 struct rpm_smd_clk_desc {
174 struct clk_smd_rpm **clks;
175 size_t num_clks;
176
177 /*
178 * Interconnect clocks are managed by the icc framework, this driver
179 * only kickstarts them so that they don't get gated between
180 * clk_smd_rpm_enable_scaling() and interconnect driver initialization.
181 */
182 const struct clk_smd_rpm ** const icc_clks;
183 size_t num_icc_clks;
184 bool scaling_before_handover;
185 };
186
187 static DEFINE_MUTEX(rpm_smd_clk_lock);
188
clk_smd_rpm_handoff(const struct clk_smd_rpm * r)189 static int clk_smd_rpm_handoff(const struct clk_smd_rpm *r)
190 {
191 int ret;
192 struct clk_smd_rpm_req req = {
193 .key = cpu_to_le32(r->rpm_key),
194 .nbytes = cpu_to_le32(sizeof(u32)),
195 .value = cpu_to_le32(r->branch ? 1 : INT_MAX),
196 };
197
198 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
199 r->rpm_res_type, r->rpm_clk_id, &req,
200 sizeof(req));
201 if (ret)
202 return ret;
203 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
204 r->rpm_res_type, r->rpm_clk_id, &req,
205 sizeof(req));
206 if (ret)
207 return ret;
208
209 return 0;
210 }
211
clk_smd_rpm_set_rate_active(struct clk_smd_rpm * r,unsigned long rate)212 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
213 unsigned long rate)
214 {
215 struct clk_smd_rpm_req req = {
216 .key = cpu_to_le32(r->rpm_key),
217 .nbytes = cpu_to_le32(sizeof(u32)),
218 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
219 };
220
221 return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
222 r->rpm_res_type, r->rpm_clk_id, &req,
223 sizeof(req));
224 }
225
clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm * r,unsigned long rate)226 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
227 unsigned long rate)
228 {
229 struct clk_smd_rpm_req req = {
230 .key = cpu_to_le32(r->rpm_key),
231 .nbytes = cpu_to_le32(sizeof(u32)),
232 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
233 };
234
235 return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
236 r->rpm_res_type, r->rpm_clk_id, &req,
237 sizeof(req));
238 }
239
to_active_sleep(struct clk_smd_rpm * r,unsigned long rate,unsigned long * active,unsigned long * sleep)240 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
241 unsigned long *active, unsigned long *sleep)
242 {
243 *active = rate;
244
245 /*
246 * Active-only clocks don't care what the rate is during sleep. So,
247 * they vote for zero.
248 */
249 if (r->active_only)
250 *sleep = 0;
251 else
252 *sleep = *active;
253 }
254
clk_smd_rpm_prepare(struct clk_hw * hw)255 static int clk_smd_rpm_prepare(struct clk_hw *hw)
256 {
257 struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
258 struct clk_smd_rpm *peer = r->peer;
259 unsigned long this_rate = 0, this_sleep_rate = 0;
260 unsigned long peer_rate = 0, peer_sleep_rate = 0;
261 unsigned long active_rate, sleep_rate;
262 int ret = 0;
263
264 mutex_lock(&rpm_smd_clk_lock);
265
266 /* Don't send requests to the RPM if the rate has not been set. */
267 if (!r->rate)
268 goto out;
269
270 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
271
272 /* Take peer clock's rate into account only if it's enabled. */
273 if (peer->enabled)
274 to_active_sleep(peer, peer->rate,
275 &peer_rate, &peer_sleep_rate);
276
277 active_rate = max(this_rate, peer_rate);
278
279 if (r->branch)
280 active_rate = !!active_rate;
281
282 ret = clk_smd_rpm_set_rate_active(r, active_rate);
283 if (ret)
284 goto out;
285
286 sleep_rate = max(this_sleep_rate, peer_sleep_rate);
287 if (r->branch)
288 sleep_rate = !!sleep_rate;
289
290 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
291 if (ret)
292 /* Undo the active set vote and restore it */
293 ret = clk_smd_rpm_set_rate_active(r, peer_rate);
294
295 out:
296 if (!ret)
297 r->enabled = true;
298
299 mutex_unlock(&rpm_smd_clk_lock);
300
301 return ret;
302 }
303
clk_smd_rpm_unprepare(struct clk_hw * hw)304 static void clk_smd_rpm_unprepare(struct clk_hw *hw)
305 {
306 struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
307 struct clk_smd_rpm *peer = r->peer;
308 unsigned long peer_rate = 0, peer_sleep_rate = 0;
309 unsigned long active_rate, sleep_rate;
310 int ret;
311
312 mutex_lock(&rpm_smd_clk_lock);
313
314 if (!r->rate)
315 goto out;
316
317 /* Take peer clock's rate into account only if it's enabled. */
318 if (peer->enabled)
319 to_active_sleep(peer, peer->rate, &peer_rate,
320 &peer_sleep_rate);
321
322 active_rate = r->branch ? !!peer_rate : peer_rate;
323 ret = clk_smd_rpm_set_rate_active(r, active_rate);
324 if (ret)
325 goto out;
326
327 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
328 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
329 if (ret)
330 goto out;
331
332 r->enabled = false;
333
334 out:
335 mutex_unlock(&rpm_smd_clk_lock);
336 }
337
clk_smd_rpm_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)338 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
339 unsigned long parent_rate)
340 {
341 struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
342 struct clk_smd_rpm *peer = r->peer;
343 unsigned long active_rate, sleep_rate;
344 unsigned long this_rate = 0, this_sleep_rate = 0;
345 unsigned long peer_rate = 0, peer_sleep_rate = 0;
346 int ret = 0;
347
348 mutex_lock(&rpm_smd_clk_lock);
349
350 if (!r->enabled)
351 goto out;
352
353 to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
354
355 /* Take peer clock's rate into account only if it's enabled. */
356 if (peer->enabled)
357 to_active_sleep(peer, peer->rate,
358 &peer_rate, &peer_sleep_rate);
359
360 active_rate = max(this_rate, peer_rate);
361 ret = clk_smd_rpm_set_rate_active(r, active_rate);
362 if (ret)
363 goto out;
364
365 sleep_rate = max(this_sleep_rate, peer_sleep_rate);
366 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
367 if (ret)
368 goto out;
369
370 r->rate = rate;
371
372 out:
373 mutex_unlock(&rpm_smd_clk_lock);
374
375 return ret;
376 }
377
clk_smd_rpm_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)378 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
379 unsigned long *parent_rate)
380 {
381 /*
382 * RPM handles rate rounding and we don't have a way to
383 * know what the rate will be, so just return whatever
384 * rate is requested.
385 */
386 return rate;
387 }
388
clk_smd_rpm_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)389 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
390 unsigned long parent_rate)
391 {
392 struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
393
394 /*
395 * RPM handles rate rounding and we don't have a way to
396 * know what the rate will be, so just return whatever
397 * rate was set.
398 */
399 return r->rate;
400 }
401
clk_smd_rpm_enable_scaling(void)402 static int clk_smd_rpm_enable_scaling(void)
403 {
404 int ret;
405 struct clk_smd_rpm_req req = {
406 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
407 .nbytes = cpu_to_le32(sizeof(u32)),
408 .value = cpu_to_le32(1),
409 };
410
411 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
412 QCOM_SMD_RPM_MISC_CLK,
413 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
414 if (ret) {
415 pr_err("RPM clock scaling (sleep set) not enabled!\n");
416 return ret;
417 }
418
419 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
420 QCOM_SMD_RPM_MISC_CLK,
421 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
422 if (ret) {
423 pr_err("RPM clock scaling (active set) not enabled!\n");
424 return ret;
425 }
426
427 pr_debug("%s: RPM clock scaling is enabled\n", __func__);
428 return 0;
429 }
430
431 static const struct clk_ops clk_smd_rpm_ops = {
432 .prepare = clk_smd_rpm_prepare,
433 .unprepare = clk_smd_rpm_unprepare,
434 .set_rate = clk_smd_rpm_set_rate,
435 .round_rate = clk_smd_rpm_round_rate,
436 .recalc_rate = clk_smd_rpm_recalc_rate,
437 };
438
439 static const struct clk_ops clk_smd_rpm_branch_ops = {
440 .prepare = clk_smd_rpm_prepare,
441 .unprepare = clk_smd_rpm_unprepare,
442 .recalc_rate = clk_smd_rpm_recalc_rate,
443 };
444
445 /* Disabling BI_TCXO_AO could gate the root clock source of the entire system. */
446 DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000, CLK_IS_CRITICAL);
447 DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000);
448 DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1);
449 DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1, 0);
450
451 DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);
452
453 DEFINE_CLK_SMD_RPM_BRANCH(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
454 DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
455 DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1);
456 DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2);
457
458 DEFINE_CLK_SMD_RPM_BUS_A(pcnoc, 0, 19200000, CLK_IS_CRITICAL);
459 DEFINE_CLK_SMD_RPM_BUS(snoc, 1);
460 DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2);
461 DEFINE_CLK_SMD_RPM_BUS(cnoc, 2);
462 DEFINE_CLK_SMD_RPM_BUS(mmssnoc_ahb, 3);
463 DEFINE_CLK_SMD_RPM_BUS(snoc_periph, 0);
464 DEFINE_CLK_SMD_RPM_BUS(cnoc, 1);
465 DEFINE_CLK_SMD_RPM_BUS(snoc, 2);
466 DEFINE_CLK_SMD_RPM_BUS(snoc_lpass, 5);
467
468 DEFINE_CLK_SMD_RPM(bimc, QCOM_SMD_RPM_MEM_CLK, 0);
469 DEFINE_CLK_SMD_RPM(cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1);
470 DEFINE_CLK_SMD_RPM_CLK_SRC(gfx3d, QCOM_SMD_RPM_MEM_CLK, 1);
471 DEFINE_CLK_SMD_RPM(ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2);
472 DEFINE_CLK_SMD_RPM(bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2);
473
474 DEFINE_CLK_SMD_RPM(ce1, QCOM_SMD_RPM_CE_CLK, 0);
475 DEFINE_CLK_SMD_RPM(ce2, QCOM_SMD_RPM_CE_CLK, 1);
476 DEFINE_CLK_SMD_RPM(ce3, QCOM_SMD_RPM_CE_CLK, 2);
477
478 DEFINE_CLK_SMD_RPM(ipa, QCOM_SMD_RPM_IPA_CLK, 0);
479
480 DEFINE_CLK_SMD_RPM(hwkm, QCOM_SMD_RPM_HWKM_CLK, 0);
481
482 DEFINE_CLK_SMD_RPM(mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0);
483 DEFINE_CLK_SMD_RPM(mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0);
484 DEFINE_CLK_SMD_RPM(mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1);
485
486 DEFINE_CLK_SMD_RPM(pka, QCOM_SMD_RPM_PKA_CLK, 0);
487
488 DEFINE_CLK_SMD_RPM(qpic, QCOM_SMD_RPM_QPIC_CLK, 0);
489
490 DEFINE_CLK_SMD_RPM(qup, QCOM_SMD_RPM_QUP_CLK, 0);
491
492 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1, 1, 19200000);
493 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2, 2, 19200000);
494 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk1, 1, 19200000);
495 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk2, 2, 19200000);
496 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk3, 3, 19200000);
497 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk1, 4, 19200000);
498 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2, 5, 19200000);
499 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk3, 6, 19200000);
500 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk, 8, 19200000);
501
502 DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk3, 6, 38400000);
503
504 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d0, 1, 19200000);
505 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d1, 2, 19200000);
506 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a0, 4, 19200000);
507 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a1, 5, 19200000);
508 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a2, 6, 19200000);
509
510 DEFINE_CLK_SMD_RPM_XO_BUFFER(diff_clk, 7, 19200000);
511 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000);
512 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000);
513 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000);
514
515 static const struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = {
516 &clk_smd_rpm_bimc_clk,
517 &clk_smd_rpm_bus_0_pcnoc_clk,
518 };
519
520 static const struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = {
521 &clk_smd_rpm_bimc_clk,
522 &clk_smd_rpm_bus_0_pcnoc_clk,
523 &clk_smd_rpm_bus_1_snoc_clk,
524 };
525
526 static const struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = {
527 &clk_smd_rpm_bimc_clk,
528 &clk_smd_rpm_bus_0_pcnoc_clk,
529 &clk_smd_rpm_bus_1_snoc_clk,
530 &clk_smd_rpm_bus_2_sysmmnoc_clk,
531 };
532
533 static const struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = {
534 &clk_smd_rpm_bimc_clk,
535 &clk_smd_rpm_bus_0_pcnoc_clk,
536 &clk_smd_rpm_bus_1_snoc_clk,
537 &clk_smd_rpm_bus_2_cnoc_clk,
538 &clk_smd_rpm_ocmemgx_clk,
539 };
540
541 static const struct clk_smd_rpm *msm8996_icc_clks[] = {
542 &clk_smd_rpm_bimc_clk,
543 &clk_smd_rpm_branch_aggre1_noc_clk,
544 &clk_smd_rpm_branch_aggre2_noc_clk,
545 &clk_smd_rpm_bus_0_pcnoc_clk,
546 &clk_smd_rpm_bus_1_snoc_clk,
547 &clk_smd_rpm_bus_2_cnoc_clk,
548 &clk_smd_rpm_mmssnoc_axi_rpm_clk,
549 };
550
551 static const struct clk_smd_rpm *msm8998_icc_clks[] = {
552 &clk_smd_rpm_aggre1_noc_clk,
553 &clk_smd_rpm_aggre2_noc_clk,
554 &clk_smd_rpm_bimc_clk,
555 &clk_smd_rpm_bus_1_snoc_clk,
556 &clk_smd_rpm_bus_2_cnoc_clk,
557 &clk_smd_rpm_mmssnoc_axi_rpm_clk,
558 };
559
560 static const struct clk_smd_rpm *sdm660_icc_clks[] = {
561 &clk_smd_rpm_aggre2_noc_clk,
562 &clk_smd_rpm_bimc_clk,
563 &clk_smd_rpm_bus_1_snoc_clk,
564 &clk_smd_rpm_bus_2_cnoc_clk,
565 &clk_smd_rpm_mmssnoc_axi_rpm_clk,
566 };
567
568 static const struct clk_smd_rpm *sm_qnoc_icc_clks[] = {
569 &clk_smd_rpm_bimc_clk,
570 &clk_smd_rpm_bus_1_cnoc_clk,
571 &clk_smd_rpm_mmnrt_clk,
572 &clk_smd_rpm_mmrt_clk,
573 &clk_smd_rpm_qup_clk,
574 &clk_smd_rpm_bus_2_snoc_clk,
575 };
576
577 static struct clk_smd_rpm *msm8909_clks[] = {
578 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
579 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
580 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
581 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
582 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
583 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
584 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
585 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
586 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
587 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
588 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
589 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
590 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
591 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
592 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
593 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
594 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
595 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
596 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
597 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
598 };
599
600 static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {
601 .clks = msm8909_clks,
602 .num_clks = ARRAY_SIZE(msm8909_clks),
603 .icc_clks = bimc_pcnoc_snoc_icc_clks,
604 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
605 };
606
607 static struct clk_smd_rpm *msm8916_clks[] = {
608 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
609 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
610 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
611 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
612 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
613 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
614 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
615 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
616 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
617 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
618 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
619 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
620 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
621 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
622 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
623 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
624 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
625 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
626 };
627
628 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
629 .clks = msm8916_clks,
630 .num_clks = ARRAY_SIZE(msm8916_clks),
631 .icc_clks = bimc_pcnoc_snoc_icc_clks,
632 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
633 };
634
635 static struct clk_smd_rpm *msm8917_clks[] = {
636 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
637 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
638 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,
639 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,
640 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
641 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
642 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
643 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
644 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
645 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
646 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
647 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
648 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
649 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
650 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
651 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
652 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
653 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
654 };
655
656 static const struct rpm_smd_clk_desc rpm_clk_msm8917 = {
657 .clks = msm8917_clks,
658 .num_clks = ARRAY_SIZE(msm8917_clks),
659 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
660 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
661 };
662
663 static struct clk_smd_rpm *msm8936_clks[] = {
664 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
665 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
666 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
667 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
668 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
669 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
670 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
671 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
672 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
673 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
674 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
675 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
676 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
677 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
678 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
679 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
680 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
681 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
682 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
683 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
684 };
685
686 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
687 .clks = msm8936_clks,
688 .num_clks = ARRAY_SIZE(msm8936_clks),
689 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
690 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
691 };
692
693 static struct clk_smd_rpm *msm8974_clks[] = {
694 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
695 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
696 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,
697 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,
698 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
699 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
700 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
701 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
702 [RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0,
703 [RPM_SMD_CXO_D0_A] = &clk_smd_rpm_cxo_d0_a,
704 [RPM_SMD_CXO_D1] = &clk_smd_rpm_cxo_d1,
705 [RPM_SMD_CXO_D1_A] = &clk_smd_rpm_cxo_d1_a,
706 [RPM_SMD_CXO_A0] = &clk_smd_rpm_cxo_a0,
707 [RPM_SMD_CXO_A0_A] = &clk_smd_rpm_cxo_a0_a,
708 [RPM_SMD_CXO_A1] = &clk_smd_rpm_cxo_a1,
709 [RPM_SMD_CXO_A1_A] = &clk_smd_rpm_cxo_a1_a,
710 [RPM_SMD_CXO_A2] = &clk_smd_rpm_cxo_a2,
711 [RPM_SMD_CXO_A2_A] = &clk_smd_rpm_cxo_a2_a,
712 [RPM_SMD_DIFF_CLK] = &clk_smd_rpm_diff_clk,
713 [RPM_SMD_DIFF_A_CLK] = &clk_smd_rpm_diff_clk_a,
714 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
715 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
716 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
717 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
718 [RPM_SMD_CXO_D0_PIN] = &clk_smd_rpm_cxo_d0_pin,
719 [RPM_SMD_CXO_D0_A_PIN] = &clk_smd_rpm_cxo_d0_a_pin,
720 [RPM_SMD_CXO_D1_PIN] = &clk_smd_rpm_cxo_d1_pin,
721 [RPM_SMD_CXO_D1_A_PIN] = &clk_smd_rpm_cxo_d1_a_pin,
722 [RPM_SMD_CXO_A0_PIN] = &clk_smd_rpm_cxo_a0_pin,
723 [RPM_SMD_CXO_A0_A_PIN] = &clk_smd_rpm_cxo_a0_a_pin,
724 [RPM_SMD_CXO_A1_PIN] = &clk_smd_rpm_cxo_a1_pin,
725 [RPM_SMD_CXO_A1_A_PIN] = &clk_smd_rpm_cxo_a1_a_pin,
726 [RPM_SMD_CXO_A2_PIN] = &clk_smd_rpm_cxo_a2_pin,
727 [RPM_SMD_CXO_A2_A_PIN] = &clk_smd_rpm_cxo_a2_a_pin,
728 };
729
730 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
731 .clks = msm8974_clks,
732 .num_clks = ARRAY_SIZE(msm8974_clks),
733 .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
734 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
735 .scaling_before_handover = true,
736 };
737
738 static struct clk_smd_rpm *msm8976_clks[] = {
739 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
740 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
741 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
742 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
743 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
744 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
745 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
746 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
747 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
748 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
749 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
750 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
751 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
752 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
753 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
754 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
755 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
756 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
757 };
758
759 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
760 .clks = msm8976_clks,
761 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
762 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
763 };
764
765 static struct clk_smd_rpm *msm8992_clks[] = {
766 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
767 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
768 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
769 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
770 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
771 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
772 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
773 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
774 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
775 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
776 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
777 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
778 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
779 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
780 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
781 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
782 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,
783 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,
784 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
785 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
786 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,
787 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,
788 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,
789 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,
790 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk,
791 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk,
792 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
793 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
794 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
795 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
796 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
797 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
798 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
799 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
800 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
801 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
802 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
803 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
804 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk,
805 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk,
806 };
807
808 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
809 .clks = msm8992_clks,
810 .num_clks = ARRAY_SIZE(msm8992_clks),
811 .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
812 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
813 };
814
815 static struct clk_smd_rpm *msm8994_clks[] = {
816 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
817 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
818 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
819 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
820 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
821 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
822 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
823 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
824 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
825 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
826 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
827 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
828 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
829 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
830 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
831 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
832 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,
833 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,
834 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
835 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
836 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,
837 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,
838 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,
839 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,
840 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk,
841 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk,
842 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
843 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
844 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
845 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
846 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
847 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
848 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
849 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
850 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
851 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
852 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
853 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
854 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk,
855 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk,
856 [RPM_SMD_CE3_CLK] = &clk_smd_rpm_ce3_clk,
857 [RPM_SMD_CE3_A_CLK] = &clk_smd_rpm_ce3_a_clk,
858 };
859
860 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
861 .clks = msm8994_clks,
862 .num_clks = ARRAY_SIZE(msm8994_clks),
863 .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
864 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
865 };
866
867 static struct clk_smd_rpm *msm8996_clks[] = {
868 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
869 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
870 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
871 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
872 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
873 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
874 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
875 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
876 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
877 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
878 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
879 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
880 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
881 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
882 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
883 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
884 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,
885 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,
886 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
887 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
888 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
889 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
890 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,
891 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,
892 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
893 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
894 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
895 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
896 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
897 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
898 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
899 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
900 };
901
902 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
903 .clks = msm8996_clks,
904 .num_clks = ARRAY_SIZE(msm8996_clks),
905 .icc_clks = msm8996_icc_clks,
906 .num_icc_clks = ARRAY_SIZE(msm8996_icc_clks),
907 };
908
909 static struct clk_smd_rpm *qcs404_clks[] = {
910 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
911 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
912 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
913 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
914 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
915 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
916 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
917 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
918 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,
919 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,
920 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
921 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
922 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
923 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
924 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
925 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
926 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,
927 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,
928 [RPM_SMD_LN_BB_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_pin,
929 [RPM_SMD_LN_BB_A_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_a_pin,
930 };
931
932 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
933 .clks = qcs404_clks,
934 .num_clks = ARRAY_SIZE(qcs404_clks),
935 .icc_clks = bimc_pcnoc_snoc_icc_clks,
936 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
937 };
938
939 static struct clk_smd_rpm *msm8998_clks[] = {
940 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
941 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
942 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
943 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
944 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
945 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
946 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
947 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
948 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
949 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
950 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,
951 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,
952 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
953 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
954 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1,
955 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a,
956 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
957 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
958 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,
959 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,
960 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin,
961 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin,
962 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin,
963 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin,
964 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin,
965 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin,
966 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
967 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
968 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
969 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
970 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
971 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
972 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_rf_clk3,
973 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_rf_clk3_a,
974 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
975 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
976 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
977 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
978 [RPM_SMD_RF_CLK3_PIN] = &clk_smd_rpm_rf_clk3_pin,
979 [RPM_SMD_RF_CLK3_A_PIN] = &clk_smd_rpm_rf_clk3_a_pin,
980 };
981
982 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
983 .clks = msm8998_clks,
984 .num_clks = ARRAY_SIZE(msm8998_clks),
985 .icc_clks = msm8998_icc_clks,
986 .num_icc_clks = ARRAY_SIZE(msm8998_icc_clks),
987 };
988
989 static struct clk_smd_rpm *sdm660_clks[] = {
990 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
991 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
992 [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
993 [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
994 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
995 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
996 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
997 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
998 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
999 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
1000 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
1001 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
1002 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
1003 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
1004 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk1,
1005 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk1_a,
1006 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
1007 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
1008 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,
1009 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,
1010 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
1011 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
1012 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin,
1013 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin,
1014 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin,
1015 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin,
1016 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin,
1017 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin,
1018 };
1019
1020 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
1021 .clks = sdm660_clks,
1022 .num_clks = ARRAY_SIZE(sdm660_clks),
1023 .icc_clks = sdm660_icc_clks,
1024 .num_icc_clks = ARRAY_SIZE(sdm660_icc_clks),
1025 };
1026
1027 static struct clk_smd_rpm *mdm9607_clks[] = {
1028 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
1029 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
1030 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
1031 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
1032 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
1033 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
1034 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
1035 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
1036 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
1037 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
1038 };
1039
1040 static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {
1041 .clks = mdm9607_clks,
1042 .num_clks = ARRAY_SIZE(mdm9607_clks),
1043 .icc_clks = bimc_pcnoc_icc_clks,
1044 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks),
1045 };
1046
1047 static struct clk_smd_rpm *msm8953_clks[] = {
1048 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
1049 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
1050 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
1051 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
1052 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
1053 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
1054 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
1055 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
1056 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
1057 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
1058 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
1059 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
1060 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_ln_bb_clk,
1061 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_ln_bb_clk_a,
1062 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
1063 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
1064 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
1065 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
1066 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
1067 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
1068 };
1069
1070 static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {
1071 .clks = msm8953_clks,
1072 .num_clks = ARRAY_SIZE(msm8953_clks),
1073 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
1074 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
1075 };
1076
1077 static struct clk_smd_rpm *sm6125_clks[] = {
1078 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
1079 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
1080 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
1081 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
1082 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
1083 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
1084 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
1085 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
1086 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
1087 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
1088 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
1089 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
1090 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1,
1091 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a,
1092 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
1093 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
1094 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,
1095 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,
1096 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
1097 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
1098 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
1099 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,
1100 };
1101
1102 static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {
1103 .clks = sm6125_clks,
1104 .num_clks = ARRAY_SIZE(sm6125_clks),
1105 .icc_clks = sm_qnoc_icc_clks,
1106 .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
1107 };
1108
1109 /* SM6115 */
1110 static struct clk_smd_rpm *sm6115_clks[] = {
1111 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
1112 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
1113 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
1114 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
1115 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
1116 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
1117 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
1118 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
1119 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
1120 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
1121 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
1122 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
1123 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
1124 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
1125 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
1126 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,
1127 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
1128 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
1129 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
1130 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
1131 };
1132
1133 static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
1134 .clks = sm6115_clks,
1135 .num_clks = ARRAY_SIZE(sm6115_clks),
1136 .icc_clks = sm_qnoc_icc_clks,
1137 .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
1138 };
1139
1140 static struct clk_smd_rpm *sm6375_clks[] = {
1141 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
1142 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
1143 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
1144 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
1145 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
1146 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
1147 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
1148 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
1149 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
1150 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,
1151 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
1152 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
1153 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk,
1154 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk,
1155 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk,
1156 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk,
1157 [RPM_SMD_BIMC_FREQ_LOG] = &clk_smd_rpm_branch_bimc_freq_log,
1158 };
1159
1160 static const struct rpm_smd_clk_desc rpm_clk_sm6375 = {
1161 .clks = sm6375_clks,
1162 .num_clks = ARRAY_SIZE(sm6375_clks),
1163 .icc_clks = sm_qnoc_icc_clks,
1164 .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
1165 };
1166
1167 static struct clk_smd_rpm *qcm2290_clks[] = {
1168 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
1169 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
1170 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
1171 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
1172 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
1173 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
1174 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3,
1175 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a,
1176 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
1177 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
1178 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
1179 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
1180 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
1181 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,
1182 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
1183 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
1184 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
1185 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
1186 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk,
1187 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk,
1188 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk,
1189 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk,
1190 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,
1191 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,
1192 [RPM_SMD_CPUSS_GNOC_CLK] = &clk_smd_rpm_cpuss_gnoc_clk,
1193 [RPM_SMD_CPUSS_GNOC_A_CLK] = &clk_smd_rpm_cpuss_gnoc_a_clk,
1194 };
1195
1196 static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
1197 .clks = qcm2290_clks,
1198 .num_clks = ARRAY_SIZE(qcm2290_clks),
1199 .icc_clks = sm_qnoc_icc_clks,
1200 .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
1201 };
1202
1203 static const struct of_device_id rpm_smd_clk_match_table[] = {
1204 { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },
1205 { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
1206 { .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 },
1207 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
1208 { .compatible = "qcom,rpmcc-msm8917", .data = &rpm_clk_msm8917 },
1209 { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
1210 { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },
1211 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
1212 { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
1213 { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
1214 { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
1215 { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
1216 { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
1217 { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 },
1218 { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
1219 { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 },
1220 { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 },
1221 { .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 },
1222 { .compatible = "qcom,rpmcc-sm6375", .data = &rpm_clk_sm6375 },
1223 { }
1224 };
1225 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
1226
qcom_smdrpm_clk_hw_get(struct of_phandle_args * clkspec,void * data)1227 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
1228 void *data)
1229 {
1230 const struct rpm_smd_clk_desc *desc = data;
1231 unsigned int idx = clkspec->args[0];
1232
1233 if (idx >= desc->num_clks) {
1234 pr_err("%s: invalid index %u\n", __func__, idx);
1235 return ERR_PTR(-EINVAL);
1236 }
1237
1238 return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);
1239 }
1240
rpm_smd_unregister_icc(void * data)1241 static void rpm_smd_unregister_icc(void *data)
1242 {
1243 struct platform_device *icc_pdev = data;
1244
1245 platform_device_unregister(icc_pdev);
1246 }
1247
rpm_smd_clk_probe(struct platform_device * pdev)1248 static int rpm_smd_clk_probe(struct platform_device *pdev)
1249 {
1250 int ret;
1251 size_t num_clks, i;
1252 struct clk_smd_rpm **rpm_smd_clks;
1253 const struct rpm_smd_clk_desc *desc;
1254 struct platform_device *icc_pdev;
1255
1256 rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent);
1257 if (!rpmcc_smd_rpm) {
1258 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
1259 return -ENODEV;
1260 }
1261
1262 desc = of_device_get_match_data(&pdev->dev);
1263 if (!desc)
1264 return -EINVAL;
1265
1266 rpm_smd_clks = desc->clks;
1267 num_clks = desc->num_clks;
1268
1269 if (desc->scaling_before_handover) {
1270 ret = clk_smd_rpm_enable_scaling();
1271 if (ret)
1272 goto err;
1273 }
1274
1275 for (i = 0; i < num_clks; i++) {
1276 if (!rpm_smd_clks[i])
1277 continue;
1278
1279 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
1280 if (ret)
1281 goto err;
1282 }
1283
1284 for (i = 0; i < desc->num_icc_clks; i++) {
1285 if (!desc->icc_clks[i])
1286 continue;
1287
1288 ret = clk_smd_rpm_handoff(desc->icc_clks[i]);
1289 if (ret)
1290 goto err;
1291 }
1292
1293 if (!desc->scaling_before_handover) {
1294 ret = clk_smd_rpm_enable_scaling();
1295 if (ret)
1296 goto err;
1297 }
1298
1299 for (i = 0; i < num_clks; i++) {
1300 if (!rpm_smd_clks[i])
1301 continue;
1302
1303 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
1304 if (ret)
1305 goto err;
1306 }
1307
1308 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
1309 (void *)desc);
1310 if (ret)
1311 goto err;
1312
1313 icc_pdev = platform_device_register_data(pdev->dev.parent,
1314 "icc_smd_rpm", -1, NULL, 0);
1315 if (IS_ERR(icc_pdev)) {
1316 dev_err(&pdev->dev, "Failed to register icc_smd_rpm device: %pE\n",
1317 icc_pdev);
1318 /* No need to unregister clocks because of this */
1319 } else {
1320 ret = devm_add_action_or_reset(&pdev->dev, rpm_smd_unregister_icc,
1321 icc_pdev);
1322 if (ret)
1323 goto err;
1324 }
1325
1326 return 0;
1327 err:
1328 dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
1329 return ret;
1330 }
1331
1332 static struct platform_driver rpm_smd_clk_driver = {
1333 .driver = {
1334 .name = "qcom-clk-smd-rpm",
1335 .of_match_table = rpm_smd_clk_match_table,
1336 },
1337 .probe = rpm_smd_clk_probe,
1338 };
1339
rpm_smd_clk_init(void)1340 static int __init rpm_smd_clk_init(void)
1341 {
1342 return platform_driver_register(&rpm_smd_clk_driver);
1343 }
1344 core_initcall(rpm_smd_clk_init);
1345
rpm_smd_clk_exit(void)1346 static void __exit rpm_smd_clk_exit(void)
1347 {
1348 platform_driver_unregister(&rpm_smd_clk_driver);
1349 }
1350 module_exit(rpm_smd_clk_exit);
1351
1352 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
1353 MODULE_LICENSE("GPL v2");
1354 MODULE_ALIAS("platform:qcom-clk-smd-rpm");
1355