1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * CHRP pci routines.
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/pci.h>
8 #include <linux/delay.h>
9 #include <linux/string.h>
10 #include <linux/init.h>
11 #include <linux/pgtable.h>
12 #include <linux/of_address.h>
13 
14 #include <asm/io.h>
15 #include <asm/irq.h>
16 #include <asm/hydra.h>
17 #include <asm/machdep.h>
18 #include <asm/sections.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/grackle.h>
21 #include <asm/rtas.h>
22 
23 #include "chrp.h"
24 #include "gg2.h"
25 
26 /* LongTrail */
27 void __iomem *gg2_pci_config_base;
28 
29 /*
30  * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
31  * limit the bus number to 3 bits
32  */
33 
gg2_read_config(struct pci_bus * bus,unsigned int devfn,int off,int len,u32 * val)34 static int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
35 			   int len, u32 *val)
36 {
37 	volatile void __iomem *cfg_data;
38 	struct pci_controller *hose = pci_bus_to_host(bus);
39 
40 	if (bus->number > 7)
41 		return PCIBIOS_DEVICE_NOT_FOUND;
42 	/*
43 	 * Note: the caller has already checked that off is
44 	 * suitably aligned and that len is 1, 2 or 4.
45 	 */
46 	cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
47 	switch (len) {
48 	case 1:
49 		*val =  in_8(cfg_data);
50 		break;
51 	case 2:
52 		*val = in_le16(cfg_data);
53 		break;
54 	default:
55 		*val = in_le32(cfg_data);
56 		break;
57 	}
58 	return PCIBIOS_SUCCESSFUL;
59 }
60 
gg2_write_config(struct pci_bus * bus,unsigned int devfn,int off,int len,u32 val)61 static int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
62 			    int len, u32 val)
63 {
64 	volatile void __iomem *cfg_data;
65 	struct pci_controller *hose = pci_bus_to_host(bus);
66 
67 	if (bus->number > 7)
68 		return PCIBIOS_DEVICE_NOT_FOUND;
69 	/*
70 	 * Note: the caller has already checked that off is
71 	 * suitably aligned and that len is 1, 2 or 4.
72 	 */
73 	cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
74 	switch (len) {
75 	case 1:
76 		out_8(cfg_data, val);
77 		break;
78 	case 2:
79 		out_le16(cfg_data, val);
80 		break;
81 	default:
82 		out_le32(cfg_data, val);
83 		break;
84 	}
85 	return PCIBIOS_SUCCESSFUL;
86 }
87 
88 static struct pci_ops gg2_pci_ops =
89 {
90 	.read = gg2_read_config,
91 	.write = gg2_write_config,
92 };
93 
94 /*
95  * Access functions for PCI config space using RTAS calls.
96  */
rtas_read_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 * val)97 static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
98 			    int len, u32 *val)
99 {
100 	struct pci_controller *hose = pci_bus_to_host(bus);
101 	unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
102 		| (((bus->number - hose->first_busno) & 0xff) << 16)
103 		| (hose->global_number << 24);
104         int ret = -1;
105 	int rval;
106 
107 	rval = rtas_call(rtas_function_token(RTAS_FN_READ_PCI_CONFIG), 2, 2, &ret, addr, len);
108 	*val = ret;
109 	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
110 }
111 
rtas_write_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 val)112 static int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
113 			     int len, u32 val)
114 {
115 	struct pci_controller *hose = pci_bus_to_host(bus);
116 	unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
117 		| (((bus->number - hose->first_busno) & 0xff) << 16)
118 		| (hose->global_number << 24);
119 	int rval;
120 
121 	rval = rtas_call(rtas_function_token(RTAS_FN_WRITE_PCI_CONFIG), 3, 1, NULL,
122 			 addr, len, val);
123 	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
124 }
125 
126 static struct pci_ops rtas_pci_ops =
127 {
128 	.read = rtas_read_config,
129 	.write = rtas_write_config,
130 };
131 
132 volatile struct Hydra __iomem *Hydra = NULL;
133 
hydra_init(void)134 static int __init hydra_init(void)
135 {
136 	struct device_node *np;
137 	struct resource r;
138 
139 	np = of_find_node_by_name(NULL, "mac-io");
140 	if (np == NULL || of_address_to_resource(np, 0, &r)) {
141 		of_node_put(np);
142 		return 0;
143 	}
144 	of_node_put(np);
145 	Hydra = ioremap(r.start, resource_size(&r));
146 	printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
147 	printk("Hydra Feature_Control was %x",
148 	       in_le32(&Hydra->Feature_Control));
149 	out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
150 					   HYDRA_FC_SCSI_CELL_EN |
151 					   HYDRA_FC_SCCA_ENABLE |
152 					   HYDRA_FC_SCCB_ENABLE |
153 					   HYDRA_FC_ARB_BYPASS |
154 					   HYDRA_FC_MPIC_ENABLE |
155 					   HYDRA_FC_SLOW_SCC_PCLK |
156 					   HYDRA_FC_MPIC_IS_MASTER));
157 	printk(", now %x\n", in_le32(&Hydra->Feature_Control));
158 	return 1;
159 }
160 
161 #define PRG_CL_RESET_VALID 0x00010000
162 
163 static void __init
setup_python(struct pci_controller * hose,struct device_node * dev)164 setup_python(struct pci_controller *hose, struct device_node *dev)
165 {
166 	u32 __iomem *reg;
167 	u32 val;
168 	struct resource r;
169 
170 	if (of_address_to_resource(dev, 0, &r)) {
171 		printk(KERN_ERR "No address for Python PCI controller\n");
172 		return;
173 	}
174 
175 	/* Clear the magic go-slow bit */
176 	reg = ioremap(r.start + 0xf6000, 0x40);
177 	BUG_ON(!reg);
178 	val = in_be32(&reg[12]);
179 	if (val & PRG_CL_RESET_VALID) {
180 		out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
181 		in_be32(&reg[12]);
182 	}
183 	iounmap(reg);
184 
185 	setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0);
186 }
187 
188 /* Marvell Discovery II based Pegasos 2 */
setup_peg2(struct pci_controller * hose,struct device_node * dev)189 static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
190 {
191 	struct device_node *root = of_find_node_by_path("/");
192 	struct device_node *rtas;
193 
194 	rtas = of_find_node_by_name (root, "rtas");
195 	if (rtas) {
196 		hose->ops = &rtas_pci_ops;
197 		of_node_put(rtas);
198 	} else {
199 		printk ("RTAS supporting Pegasos OF not found, please upgrade"
200 			" your firmware\n");
201 	}
202 	pci_add_flags(PCI_REASSIGN_ALL_BUS);
203 	/* keep the reference to the root node */
204 }
205 
206 void __init
chrp_find_bridges(void)207 chrp_find_bridges(void)
208 {
209 	struct device_node *dev;
210 	const int *bus_range;
211 	int len, index = -1;
212 	struct pci_controller *hose;
213 	const unsigned int *dma;
214 	const char *model, *machine;
215 	int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
216 	struct device_node *root = of_find_node_by_path("/");
217 	struct resource r;
218 	/*
219 	 * The PCI host bridge nodes on some machines don't have
220 	 * properties to adequately identify them, so we have to
221 	 * look at what sort of machine this is as well.
222 	 */
223 	machine = of_get_property(root, "model", NULL);
224 	if (machine != NULL) {
225 		is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
226 		is_mot = strncmp(machine, "MOT", 3) == 0;
227 		if (strncmp(machine, "Pegasos2", 8) == 0)
228 			is_pegasos = 2;
229 		else if (strncmp(machine, "Pegasos", 7) == 0)
230 			is_pegasos = 1;
231 	}
232 	for_each_child_of_node(root, dev) {
233 		if (!of_node_is_type(dev, "pci"))
234 			continue;
235 		++index;
236 		/* The GG2 bridge on the LongTrail doesn't have an address */
237 		if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
238 			printk(KERN_WARNING "Can't use %pOF: no address\n",
239 			       dev);
240 			continue;
241 		}
242 		bus_range = of_get_property(dev, "bus-range", &len);
243 		if (bus_range == NULL || len < 2 * sizeof(int)) {
244 			printk(KERN_WARNING "Can't get bus-range for %pOF\n",
245 				dev);
246 			continue;
247 		}
248 		if (bus_range[1] == bus_range[0])
249 			printk(KERN_INFO "PCI bus %d", bus_range[0]);
250 		else
251 			printk(KERN_INFO "PCI buses %d..%d",
252 			       bus_range[0], bus_range[1]);
253 		printk(" controlled by %pOF", dev);
254 		if (!is_longtrail)
255 			printk(" at %llx", (unsigned long long)r.start);
256 		printk("\n");
257 
258 		hose = pcibios_alloc_controller(dev);
259 		if (!hose) {
260 			printk("Can't allocate PCI controller structure for %pOF\n",
261 				dev);
262 			continue;
263 		}
264 		hose->first_busno = hose->self_busno = bus_range[0];
265 		hose->last_busno = bus_range[1];
266 
267 		model = of_get_property(dev, "model", NULL);
268 		if (model == NULL)
269 			model = "<none>";
270 		if (strncmp(model, "IBM, Python", 11) == 0) {
271 			setup_python(hose, dev);
272 		} else if (is_mot
273 			   || strncmp(model, "Motorola, Grackle", 17) == 0) {
274 			setup_grackle(hose);
275 		} else if (is_longtrail) {
276 			void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
277 			hose->ops = &gg2_pci_ops;
278 			hose->cfg_data = p;
279 			gg2_pci_config_base = p;
280 		} else if (is_pegasos == 1) {
281 			setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0);
282 		} else if (is_pegasos == 2) {
283 			setup_peg2(hose, dev);
284 		} else if (!strncmp(model, "IBM,CPC710", 10)) {
285 			setup_indirect_pci(hose,
286 					   r.start + 0x000f8000,
287 					   r.start + 0x000f8010,
288 					   0);
289 			if (index == 0) {
290 				dma = of_get_property(dev, "system-dma-base",
291 							&len);
292 				if (dma && len >= sizeof(*dma)) {
293 					dma = (unsigned int *)
294 						(((unsigned long)dma) +
295 						len - sizeof(*dma));
296 						pci_dram_offset = *dma;
297 				}
298 			}
299 		} else {
300 			printk("No methods for %pOF (model %s), using RTAS\n",
301 			       dev, model);
302 			hose->ops = &rtas_pci_ops;
303 		}
304 
305 		pci_process_bridge_OF_ranges(hose, dev, index == 0);
306 
307 		/* check the first bridge for a property that we can
308 		   use to set pci_dram_offset */
309 		dma = of_get_property(dev, "ibm,dma-ranges", &len);
310 		if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
311 			pci_dram_offset = dma[2] - dma[3];
312 			printk("pci_dram_offset = %lx\n", pci_dram_offset);
313 		}
314 	}
315 	of_node_put(root);
316 
317 	/*
318 	 *  "Temporary" fixes for PCI devices.
319 	 *  -- Geert
320 	 */
321 	hydra_init();		/* Mac I/O */
322 
323 	pci_create_OF_bus_map();
324 }
325 
326 /* SL82C105 IDE Control/Status Register */
327 #define SL82C105_IDECSR                0x40
328 
329 /* Fixup for Winbond ATA quirk, required for briq mostly because the
330  * 8259 is configured for level sensitive IRQ 14 and so wants the
331  * ATA controller to be set to fully native mode or bad things
332  * will happen.
333  */
chrp_pci_fixup_winbond_ata(struct pci_dev * sl82c105)334 static void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
335 {
336 	u8 progif;
337 
338 	/* If non-briq machines need that fixup too, please speak up */
339 	if (!machine_is(chrp) || _chrp_type != _CHRP_briq)
340 		return;
341 
342 	if ((sl82c105->class & 5) != 5) {
343 		printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
344 		/* Enable SL82C105 PCI native IDE mode */
345 		pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
346 		pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
347 		sl82c105->class |= 0x05;
348 		/* Disable SL82C105 second port */
349 		pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
350 		/* Clear IO BARs, they will be reassigned */
351 		pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_0, 0);
352 		pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_1, 0);
353 		pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_2, 0);
354 		pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_3, 0);
355 	}
356 }
357 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
358 			chrp_pci_fixup_winbond_ata);
359 
360 /* Pegasos2 firmware version 20040810 configures the built-in IDE controller
361  * in legacy mode, but sets the PCI registers to PCI native mode.
362  * The chip can only operate in legacy mode, so force the PCI class into legacy
363  * mode as well. The same fixup must be done to the class-code property in
364  * the IDE node /pci@80000000/ide@C,1
365  */
chrp_pci_fixup_vt8231_ata(struct pci_dev * viaide)366 static void chrp_pci_fixup_vt8231_ata(struct pci_dev *viaide)
367 {
368 	u8 progif;
369 	struct pci_dev *viaisa;
370 
371 	if (!machine_is(chrp) || _chrp_type != _CHRP_Pegasos)
372 		return;
373 	if (viaide->irq != 14)
374 		return;
375 
376 	viaisa = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
377 	if (!viaisa)
378 		return;
379 	dev_info(&viaide->dev, "Fixing VIA IDE, force legacy mode on\n");
380 
381 	pci_read_config_byte(viaide, PCI_CLASS_PROG, &progif);
382 	pci_write_config_byte(viaide, PCI_CLASS_PROG, progif & ~0x5);
383 	viaide->class &= ~0x5;
384 
385 	pci_dev_put(viaisa);
386 }
387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, chrp_pci_fixup_vt8231_ata);
388