1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2012,2013 - ARM Ltd
4  * Author: Marc Zyngier <marc.zyngier@arm.com>
5  *
6  * Derived from arch/arm/include/asm/kvm_host.h:
7  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9  */
10 
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
13 
14 #include <linux/arm-smccc.h>
15 #include <linux/bitmap.h>
16 #include <linux/types.h>
17 #include <linux/jump_label.h>
18 #include <linux/kvm_types.h>
19 #include <linux/maple_tree.h>
20 #include <linux/percpu.h>
21 #include <linux/psci.h>
22 #include <asm/arch_gicv3.h>
23 #include <asm/barrier.h>
24 #include <asm/cpufeature.h>
25 #include <asm/cputype.h>
26 #include <asm/daifflags.h>
27 #include <asm/fpsimd.h>
28 #include <asm/kvm.h>
29 #include <asm/kvm_asm.h>
30 
31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
32 
33 #define KVM_HALT_POLL_NS_DEFAULT 500000
34 
35 #include <kvm/arm_vgic.h>
36 #include <kvm/arm_arch_timer.h>
37 #include <kvm/arm_pmu.h>
38 
39 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
40 
41 #define KVM_VCPU_MAX_FEATURES 7
42 #define KVM_VCPU_VALID_FEATURES	(BIT(KVM_VCPU_MAX_FEATURES) - 1)
43 
44 #define KVM_REQ_SLEEP \
45 	KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
46 #define KVM_REQ_IRQ_PENDING	KVM_ARCH_REQ(1)
47 #define KVM_REQ_VCPU_RESET	KVM_ARCH_REQ(2)
48 #define KVM_REQ_RECORD_STEAL	KVM_ARCH_REQ(3)
49 #define KVM_REQ_RELOAD_GICv4	KVM_ARCH_REQ(4)
50 #define KVM_REQ_RELOAD_PMU	KVM_ARCH_REQ(5)
51 #define KVM_REQ_SUSPEND		KVM_ARCH_REQ(6)
52 #define KVM_REQ_RESYNC_PMU_EL0	KVM_ARCH_REQ(7)
53 
54 #define KVM_DIRTY_LOG_MANUAL_CAPS   (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
55 				     KVM_DIRTY_LOG_INITIALLY_SET)
56 
57 #define KVM_HAVE_MMU_RWLOCK
58 
59 /*
60  * Mode of operation configurable with kvm-arm.mode early param.
61  * See Documentation/admin-guide/kernel-parameters.txt for more information.
62  */
63 enum kvm_mode {
64 	KVM_MODE_DEFAULT,
65 	KVM_MODE_PROTECTED,
66 	KVM_MODE_NV,
67 	KVM_MODE_NONE,
68 };
69 #ifdef CONFIG_KVM
70 enum kvm_mode kvm_get_mode(void);
71 #else
kvm_get_mode(void)72 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
73 #endif
74 
75 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
76 
77 extern unsigned int __ro_after_init kvm_sve_max_vl;
78 int __init kvm_arm_init_sve(void);
79 
80 u32 __attribute_const__ kvm_target_cpu(void);
81 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
82 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
83 
84 struct kvm_hyp_memcache {
85 	phys_addr_t head;
86 	unsigned long nr_pages;
87 };
88 
push_hyp_memcache(struct kvm_hyp_memcache * mc,phys_addr_t * p,phys_addr_t (* to_pa)(void * virt))89 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
90 				     phys_addr_t *p,
91 				     phys_addr_t (*to_pa)(void *virt))
92 {
93 	*p = mc->head;
94 	mc->head = to_pa(p);
95 	mc->nr_pages++;
96 }
97 
pop_hyp_memcache(struct kvm_hyp_memcache * mc,void * (* to_va)(phys_addr_t phys))98 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
99 				     void *(*to_va)(phys_addr_t phys))
100 {
101 	phys_addr_t *p = to_va(mc->head);
102 
103 	if (!mc->nr_pages)
104 		return NULL;
105 
106 	mc->head = *p;
107 	mc->nr_pages--;
108 
109 	return p;
110 }
111 
__topup_hyp_memcache(struct kvm_hyp_memcache * mc,unsigned long min_pages,void * (* alloc_fn)(void * arg),phys_addr_t (* to_pa)(void * virt),void * arg)112 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
113 				       unsigned long min_pages,
114 				       void *(*alloc_fn)(void *arg),
115 				       phys_addr_t (*to_pa)(void *virt),
116 				       void *arg)
117 {
118 	while (mc->nr_pages < min_pages) {
119 		phys_addr_t *p = alloc_fn(arg);
120 
121 		if (!p)
122 			return -ENOMEM;
123 		push_hyp_memcache(mc, p, to_pa);
124 	}
125 
126 	return 0;
127 }
128 
__free_hyp_memcache(struct kvm_hyp_memcache * mc,void (* free_fn)(void * virt,void * arg),void * (* to_va)(phys_addr_t phys),void * arg)129 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
130 				       void (*free_fn)(void *virt, void *arg),
131 				       void *(*to_va)(phys_addr_t phys),
132 				       void *arg)
133 {
134 	while (mc->nr_pages)
135 		free_fn(pop_hyp_memcache(mc, to_va), arg);
136 }
137 
138 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
139 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
140 
141 struct kvm_vmid {
142 	atomic64_t id;
143 };
144 
145 struct kvm_s2_mmu {
146 	struct kvm_vmid vmid;
147 
148 	/*
149 	 * stage2 entry level table
150 	 *
151 	 * Two kvm_s2_mmu structures in the same VM can point to the same
152 	 * pgd here.  This happens when running a guest using a
153 	 * translation regime that isn't affected by its own stage-2
154 	 * translation, such as a non-VHE hypervisor running at vEL2, or
155 	 * for vEL1/EL0 with vHCR_EL2.VM == 0.  In that case, we use the
156 	 * canonical stage-2 page tables.
157 	 */
158 	phys_addr_t	pgd_phys;
159 	struct kvm_pgtable *pgt;
160 
161 	/* The last vcpu id that ran on each physical CPU */
162 	int __percpu *last_vcpu_ran;
163 
164 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0
165 	/*
166 	 * Memory cache used to split
167 	 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It
168 	 * is used to allocate stage2 page tables while splitting huge
169 	 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
170 	 * influences both the capacity of the split page cache, and
171 	 * how often KVM reschedules. Be wary of raising CHUNK_SIZE
172 	 * too high.
173 	 *
174 	 * Protected by kvm->slots_lock.
175 	 */
176 	struct kvm_mmu_memory_cache split_page_cache;
177 	uint64_t split_page_chunk_size;
178 
179 	struct kvm_arch *arch;
180 };
181 
182 struct kvm_arch_memory_slot {
183 };
184 
185 /**
186  * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
187  *
188  * @std_bmap: Bitmap of standard secure service calls
189  * @std_hyp_bmap: Bitmap of standard hypervisor service calls
190  * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
191  */
192 struct kvm_smccc_features {
193 	unsigned long std_bmap;
194 	unsigned long std_hyp_bmap;
195 	unsigned long vendor_hyp_bmap;
196 };
197 
198 typedef unsigned int pkvm_handle_t;
199 
200 struct kvm_protected_vm {
201 	pkvm_handle_t handle;
202 	struct kvm_hyp_memcache teardown_mc;
203 };
204 
205 struct kvm_arch {
206 	struct kvm_s2_mmu mmu;
207 
208 	/* VTCR_EL2 value for this VM */
209 	u64    vtcr;
210 
211 	/* Interrupt controller */
212 	struct vgic_dist	vgic;
213 
214 	/* Timers */
215 	struct arch_timer_vm_data timer_data;
216 
217 	/* Mandated version of PSCI */
218 	u32 psci_version;
219 
220 	/* Protects VM-scoped configuration data */
221 	struct mutex config_lock;
222 
223 	/*
224 	 * If we encounter a data abort without valid instruction syndrome
225 	 * information, report this to user space.  User space can (and
226 	 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
227 	 * supported.
228 	 */
229 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER	0
230 	/* Memory Tagging Extension enabled for the guest */
231 #define KVM_ARCH_FLAG_MTE_ENABLED			1
232 	/* At least one vCPU has ran in the VM */
233 #define KVM_ARCH_FLAG_HAS_RAN_ONCE			2
234 	/* The vCPU feature set for the VM is configured */
235 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED		3
236 	/* PSCI SYSTEM_SUSPEND enabled for the guest */
237 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED		4
238 	/* VM counter offset */
239 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET			5
240 	/* Timer PPIs made immutable */
241 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE		6
242 	/* SMCCC filter initialized for the VM */
243 #define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED		7
244 	/* Initial ID reg values loaded */
245 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED		8
246 	unsigned long flags;
247 
248 	/* VM-wide vCPU feature set */
249 	DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES);
250 
251 	/*
252 	 * VM-wide PMU filter, implemented as a bitmap and big enough for
253 	 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
254 	 */
255 	unsigned long *pmu_filter;
256 	struct arm_pmu *arm_pmu;
257 
258 	cpumask_var_t supported_cpus;
259 
260 	/* Hypercall features firmware registers' descriptor */
261 	struct kvm_smccc_features smccc_feat;
262 	struct maple_tree smccc_filter;
263 
264 	/*
265 	 * Emulated CPU ID registers per VM
266 	 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it
267 	 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
268 	 *
269 	 * These emulated idregs are VM-wide, but accessed from the context of a vCPU.
270 	 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock.
271 	 */
272 #define IDREG_IDX(id)		(((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id))
273 #define IDREG(kvm, id)		((kvm)->arch.id_regs[IDREG_IDX(id)])
274 #define KVM_ARM_ID_REG_NUM	(IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1)
275 	u64 id_regs[KVM_ARM_ID_REG_NUM];
276 
277 	/*
278 	 * For an untrusted host VM, 'pkvm.handle' is used to lookup
279 	 * the associated pKVM instance in the hypervisor.
280 	 */
281 	struct kvm_protected_vm pkvm;
282 };
283 
284 struct kvm_vcpu_fault_info {
285 	u64 esr_el2;		/* Hyp Syndrom Register */
286 	u64 far_el2;		/* Hyp Fault Address Register */
287 	u64 hpfar_el2;		/* Hyp IPA Fault Address Register */
288 	u64 disr_el1;		/* Deferred [SError] Status Register */
289 };
290 
291 enum vcpu_sysreg {
292 	__INVALID_SYSREG__,   /* 0 is reserved as an invalid value */
293 	MPIDR_EL1,	/* MultiProcessor Affinity Register */
294 	CLIDR_EL1,	/* Cache Level ID Register */
295 	CSSELR_EL1,	/* Cache Size Selection Register */
296 	SCTLR_EL1,	/* System Control Register */
297 	ACTLR_EL1,	/* Auxiliary Control Register */
298 	CPACR_EL1,	/* Coprocessor Access Control */
299 	ZCR_EL1,	/* SVE Control */
300 	TTBR0_EL1,	/* Translation Table Base Register 0 */
301 	TTBR1_EL1,	/* Translation Table Base Register 1 */
302 	TCR_EL1,	/* Translation Control Register */
303 	TCR2_EL1,	/* Extended Translation Control Register */
304 	ESR_EL1,	/* Exception Syndrome Register */
305 	AFSR0_EL1,	/* Auxiliary Fault Status Register 0 */
306 	AFSR1_EL1,	/* Auxiliary Fault Status Register 1 */
307 	FAR_EL1,	/* Fault Address Register */
308 	MAIR_EL1,	/* Memory Attribute Indirection Register */
309 	VBAR_EL1,	/* Vector Base Address Register */
310 	CONTEXTIDR_EL1,	/* Context ID Register */
311 	TPIDR_EL0,	/* Thread ID, User R/W */
312 	TPIDRRO_EL0,	/* Thread ID, User R/O */
313 	TPIDR_EL1,	/* Thread ID, Privileged */
314 	AMAIR_EL1,	/* Aux Memory Attribute Indirection Register */
315 	CNTKCTL_EL1,	/* Timer Control Register (EL1) */
316 	PAR_EL1,	/* Physical Address Register */
317 	MDSCR_EL1,	/* Monitor Debug System Control Register */
318 	MDCCINT_EL1,	/* Monitor Debug Comms Channel Interrupt Enable Reg */
319 	OSLSR_EL1,	/* OS Lock Status Register */
320 	DISR_EL1,	/* Deferred Interrupt Status Register */
321 
322 	/* Performance Monitors Registers */
323 	PMCR_EL0,	/* Control Register */
324 	PMSELR_EL0,	/* Event Counter Selection Register */
325 	PMEVCNTR0_EL0,	/* Event Counter Register (0-30) */
326 	PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
327 	PMCCNTR_EL0,	/* Cycle Counter Register */
328 	PMEVTYPER0_EL0,	/* Event Type Register (0-30) */
329 	PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
330 	PMCCFILTR_EL0,	/* Cycle Count Filter Register */
331 	PMCNTENSET_EL0,	/* Count Enable Set Register */
332 	PMINTENSET_EL1,	/* Interrupt Enable Set Register */
333 	PMOVSSET_EL0,	/* Overflow Flag Status Set Register */
334 	PMUSERENR_EL0,	/* User Enable Register */
335 
336 	/* Pointer Authentication Registers in a strict increasing order. */
337 	APIAKEYLO_EL1,
338 	APIAKEYHI_EL1,
339 	APIBKEYLO_EL1,
340 	APIBKEYHI_EL1,
341 	APDAKEYLO_EL1,
342 	APDAKEYHI_EL1,
343 	APDBKEYLO_EL1,
344 	APDBKEYHI_EL1,
345 	APGAKEYLO_EL1,
346 	APGAKEYHI_EL1,
347 
348 	ELR_EL1,
349 	SP_EL1,
350 	SPSR_EL1,
351 
352 	CNTVOFF_EL2,
353 	CNTV_CVAL_EL0,
354 	CNTV_CTL_EL0,
355 	CNTP_CVAL_EL0,
356 	CNTP_CTL_EL0,
357 
358 	/* Memory Tagging Extension registers */
359 	RGSR_EL1,	/* Random Allocation Tag Seed Register */
360 	GCR_EL1,	/* Tag Control Register */
361 	TFSR_EL1,	/* Tag Fault Status Register (EL1) */
362 	TFSRE0_EL1,	/* Tag Fault Status Register (EL0) */
363 
364 	/* Permission Indirection Extension registers */
365 	PIR_EL1,       /* Permission Indirection Register 1 (EL1) */
366 	PIRE0_EL1,     /*  Permission Indirection Register 0 (EL1) */
367 
368 	/* 32bit specific registers. */
369 	DACR32_EL2,	/* Domain Access Control Register */
370 	IFSR32_EL2,	/* Instruction Fault Status Register */
371 	FPEXC32_EL2,	/* Floating-Point Exception Control Register */
372 	DBGVCR32_EL2,	/* Debug Vector Catch Register */
373 
374 	/* EL2 registers */
375 	VPIDR_EL2,	/* Virtualization Processor ID Register */
376 	VMPIDR_EL2,	/* Virtualization Multiprocessor ID Register */
377 	SCTLR_EL2,	/* System Control Register (EL2) */
378 	ACTLR_EL2,	/* Auxiliary Control Register (EL2) */
379 	HCR_EL2,	/* Hypervisor Configuration Register */
380 	MDCR_EL2,	/* Monitor Debug Configuration Register (EL2) */
381 	CPTR_EL2,	/* Architectural Feature Trap Register (EL2) */
382 	HSTR_EL2,	/* Hypervisor System Trap Register */
383 	HACR_EL2,	/* Hypervisor Auxiliary Control Register */
384 	HCRX_EL2,	/* Extended Hypervisor Configuration Register */
385 	TTBR0_EL2,	/* Translation Table Base Register 0 (EL2) */
386 	TTBR1_EL2,	/* Translation Table Base Register 1 (EL2) */
387 	TCR_EL2,	/* Translation Control Register (EL2) */
388 	VTTBR_EL2,	/* Virtualization Translation Table Base Register */
389 	VTCR_EL2,	/* Virtualization Translation Control Register */
390 	SPSR_EL2,	/* EL2 saved program status register */
391 	ELR_EL2,	/* EL2 exception link register */
392 	AFSR0_EL2,	/* Auxiliary Fault Status Register 0 (EL2) */
393 	AFSR1_EL2,	/* Auxiliary Fault Status Register 1 (EL2) */
394 	ESR_EL2,	/* Exception Syndrome Register (EL2) */
395 	FAR_EL2,	/* Fault Address Register (EL2) */
396 	HPFAR_EL2,	/* Hypervisor IPA Fault Address Register */
397 	MAIR_EL2,	/* Memory Attribute Indirection Register (EL2) */
398 	AMAIR_EL2,	/* Auxiliary Memory Attribute Indirection Register (EL2) */
399 	VBAR_EL2,	/* Vector Base Address Register (EL2) */
400 	RVBAR_EL2,	/* Reset Vector Base Address Register */
401 	CONTEXTIDR_EL2,	/* Context ID Register (EL2) */
402 	TPIDR_EL2,	/* EL2 Software Thread ID Register */
403 	CNTHCTL_EL2,	/* Counter-timer Hypervisor Control register */
404 	SP_EL2,		/* EL2 Stack Pointer */
405 	HFGRTR_EL2,
406 	HFGWTR_EL2,
407 	HFGITR_EL2,
408 	HDFGRTR_EL2,
409 	HDFGWTR_EL2,
410 	CNTHP_CTL_EL2,
411 	CNTHP_CVAL_EL2,
412 	CNTHV_CTL_EL2,
413 	CNTHV_CVAL_EL2,
414 
415 	NR_SYS_REGS	/* Nothing after this line! */
416 };
417 
418 struct kvm_cpu_context {
419 	struct user_pt_regs regs;	/* sp = sp_el0 */
420 
421 	u64	spsr_abt;
422 	u64	spsr_und;
423 	u64	spsr_irq;
424 	u64	spsr_fiq;
425 
426 	struct user_fpsimd_state fp_regs;
427 
428 	u64 sys_regs[NR_SYS_REGS];
429 
430 	struct kvm_vcpu *__hyp_running_vcpu;
431 };
432 
433 struct kvm_host_data {
434 	struct kvm_cpu_context host_ctxt;
435 };
436 
437 struct kvm_host_psci_config {
438 	/* PSCI version used by host. */
439 	u32 version;
440 	u32 smccc_version;
441 
442 	/* Function IDs used by host if version is v0.1. */
443 	struct psci_0_1_function_ids function_ids_0_1;
444 
445 	bool psci_0_1_cpu_suspend_implemented;
446 	bool psci_0_1_cpu_on_implemented;
447 	bool psci_0_1_cpu_off_implemented;
448 	bool psci_0_1_migrate_implemented;
449 };
450 
451 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
452 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
453 
454 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
455 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
456 
457 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
458 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
459 
460 struct vcpu_reset_state {
461 	unsigned long	pc;
462 	unsigned long	r0;
463 	bool		be;
464 	bool		reset;
465 };
466 
467 struct kvm_vcpu_arch {
468 	struct kvm_cpu_context ctxt;
469 
470 	/*
471 	 * Guest floating point state
472 	 *
473 	 * The architecture has two main floating point extensions,
474 	 * the original FPSIMD and SVE.  These have overlapping
475 	 * register views, with the FPSIMD V registers occupying the
476 	 * low 128 bits of the SVE Z registers.  When the core
477 	 * floating point code saves the register state of a task it
478 	 * records which view it saved in fp_type.
479 	 */
480 	void *sve_state;
481 	enum fp_type fp_type;
482 	unsigned int sve_max_vl;
483 	u64 svcr;
484 
485 	/* Stage 2 paging state used by the hardware on next switch */
486 	struct kvm_s2_mmu *hw_mmu;
487 
488 	/* Values of trap registers for the guest. */
489 	u64 hcr_el2;
490 	u64 mdcr_el2;
491 	u64 cptr_el2;
492 
493 	/* Values of trap registers for the host before guest entry. */
494 	u64 mdcr_el2_host;
495 
496 	/* Exception Information */
497 	struct kvm_vcpu_fault_info fault;
498 
499 	/* Ownership of the FP regs */
500 	enum {
501 		FP_STATE_FREE,
502 		FP_STATE_HOST_OWNED,
503 		FP_STATE_GUEST_OWNED,
504 	} fp_state;
505 
506 	/* Configuration flags, set once and for all before the vcpu can run */
507 	u8 cflags;
508 
509 	/* Input flags to the hypervisor code, potentially cleared after use */
510 	u8 iflags;
511 
512 	/* State flags for kernel bookkeeping, unused by the hypervisor code */
513 	u8 sflags;
514 
515 	/*
516 	 * Don't run the guest (internal implementation need).
517 	 *
518 	 * Contrary to the flags above, this is set/cleared outside of
519 	 * a vcpu context, and thus cannot be mixed with the flags
520 	 * themselves (or the flag accesses need to be made atomic).
521 	 */
522 	bool pause;
523 
524 	/*
525 	 * We maintain more than a single set of debug registers to support
526 	 * debugging the guest from the host and to maintain separate host and
527 	 * guest state during world switches. vcpu_debug_state are the debug
528 	 * registers of the vcpu as the guest sees them.  host_debug_state are
529 	 * the host registers which are saved and restored during
530 	 * world switches. external_debug_state contains the debug
531 	 * values we want to debug the guest. This is set via the
532 	 * KVM_SET_GUEST_DEBUG ioctl.
533 	 *
534 	 * debug_ptr points to the set of debug registers that should be loaded
535 	 * onto the hardware when running the guest.
536 	 */
537 	struct kvm_guest_debug_arch *debug_ptr;
538 	struct kvm_guest_debug_arch vcpu_debug_state;
539 	struct kvm_guest_debug_arch external_debug_state;
540 
541 	struct user_fpsimd_state *host_fpsimd_state;	/* hyp VA */
542 	struct task_struct *parent_task;
543 
544 	struct {
545 		/* {Break,watch}point registers */
546 		struct kvm_guest_debug_arch regs;
547 		/* Statistical profiling extension */
548 		u64 pmscr_el1;
549 		/* Self-hosted trace */
550 		u64 trfcr_el1;
551 	} host_debug_state;
552 
553 	/* VGIC state */
554 	struct vgic_cpu vgic_cpu;
555 	struct arch_timer_cpu timer_cpu;
556 	struct kvm_pmu pmu;
557 
558 	/*
559 	 * Guest registers we preserve during guest debugging.
560 	 *
561 	 * These shadow registers are updated by the kvm_handle_sys_reg
562 	 * trap handler if the guest accesses or updates them while we
563 	 * are using guest debug.
564 	 */
565 	struct {
566 		u32	mdscr_el1;
567 		bool	pstate_ss;
568 	} guest_debug_preserved;
569 
570 	/* vcpu power state */
571 	struct kvm_mp_state mp_state;
572 	spinlock_t mp_state_lock;
573 
574 	/* Cache some mmu pages needed inside spinlock regions */
575 	struct kvm_mmu_memory_cache mmu_page_cache;
576 
577 	/* feature flags */
578 	DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
579 
580 	/* Virtual SError ESR to restore when HCR_EL2.VSE is set */
581 	u64 vsesr_el2;
582 
583 	/* Additional reset state */
584 	struct vcpu_reset_state	reset_state;
585 
586 	/* Guest PV state */
587 	struct {
588 		u64 last_steal;
589 		gpa_t base;
590 	} steal;
591 
592 	/* Per-vcpu CCSIDR override or NULL */
593 	u32 *ccsidr;
594 };
595 
596 /*
597  * Each 'flag' is composed of a comma-separated triplet:
598  *
599  * - the flag-set it belongs to in the vcpu->arch structure
600  * - the value for that flag
601  * - the mask for that flag
602  *
603  *  __vcpu_single_flag() builds such a triplet for a single-bit flag.
604  * unpack_vcpu_flag() extract the flag value from the triplet for
605  * direct use outside of the flag accessors.
606  */
607 #define __vcpu_single_flag(_set, _f)	_set, (_f), (_f)
608 
609 #define __unpack_flag(_set, _f, _m)	_f
610 #define unpack_vcpu_flag(...)		__unpack_flag(__VA_ARGS__)
611 
612 #define __build_check_flag(v, flagset, f, m)			\
613 	do {							\
614 		typeof(v->arch.flagset) *_fset;			\
615 								\
616 		/* Check that the flags fit in the mask */	\
617 		BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m)));	\
618 		/* Check that the flags fit in the type */	\
619 		BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m));	\
620 	} while (0)
621 
622 #define __vcpu_get_flag(v, flagset, f, m)			\
623 	({							\
624 		__build_check_flag(v, flagset, f, m);		\
625 								\
626 		READ_ONCE(v->arch.flagset) & (m);		\
627 	})
628 
629 /*
630  * Note that the set/clear accessors must be preempt-safe in order to
631  * avoid nesting them with load/put which also manipulate flags...
632  */
633 #ifdef __KVM_NVHE_HYPERVISOR__
634 /* the nVHE hypervisor is always non-preemptible */
635 #define __vcpu_flags_preempt_disable()
636 #define __vcpu_flags_preempt_enable()
637 #else
638 #define __vcpu_flags_preempt_disable()	preempt_disable()
639 #define __vcpu_flags_preempt_enable()	preempt_enable()
640 #endif
641 
642 #define __vcpu_set_flag(v, flagset, f, m)			\
643 	do {							\
644 		typeof(v->arch.flagset) *fset;			\
645 								\
646 		__build_check_flag(v, flagset, f, m);		\
647 								\
648 		fset = &v->arch.flagset;			\
649 		__vcpu_flags_preempt_disable();			\
650 		if (HWEIGHT(m) > 1)				\
651 			*fset &= ~(m);				\
652 		*fset |= (f);					\
653 		__vcpu_flags_preempt_enable();			\
654 	} while (0)
655 
656 #define __vcpu_clear_flag(v, flagset, f, m)			\
657 	do {							\
658 		typeof(v->arch.flagset) *fset;			\
659 								\
660 		__build_check_flag(v, flagset, f, m);		\
661 								\
662 		fset = &v->arch.flagset;			\
663 		__vcpu_flags_preempt_disable();			\
664 		*fset &= ~(m);					\
665 		__vcpu_flags_preempt_enable();			\
666 	} while (0)
667 
668 #define vcpu_get_flag(v, ...)	__vcpu_get_flag((v), __VA_ARGS__)
669 #define vcpu_set_flag(v, ...)	__vcpu_set_flag((v), __VA_ARGS__)
670 #define vcpu_clear_flag(v, ...)	__vcpu_clear_flag((v), __VA_ARGS__)
671 
672 /* SVE exposed to guest */
673 #define GUEST_HAS_SVE		__vcpu_single_flag(cflags, BIT(0))
674 /* SVE config completed */
675 #define VCPU_SVE_FINALIZED	__vcpu_single_flag(cflags, BIT(1))
676 /* PTRAUTH exposed to guest */
677 #define GUEST_HAS_PTRAUTH	__vcpu_single_flag(cflags, BIT(2))
678 /* KVM_ARM_VCPU_INIT completed */
679 #define VCPU_INITIALIZED	__vcpu_single_flag(cflags, BIT(3))
680 
681 /* Exception pending */
682 #define PENDING_EXCEPTION	__vcpu_single_flag(iflags, BIT(0))
683 /*
684  * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
685  * be set together with an exception...
686  */
687 #define INCREMENT_PC		__vcpu_single_flag(iflags, BIT(1))
688 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
689 #define EXCEPT_MASK		__vcpu_single_flag(iflags, GENMASK(3, 1))
690 
691 /* Helpers to encode exceptions with minimum fuss */
692 #define __EXCEPT_MASK_VAL	unpack_vcpu_flag(EXCEPT_MASK)
693 #define __EXCEPT_SHIFT		__builtin_ctzl(__EXCEPT_MASK_VAL)
694 #define __vcpu_except_flags(_f)	iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
695 
696 /*
697  * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
698  * values:
699  *
700  * For AArch32 EL1:
701  */
702 #define EXCEPT_AA32_UND		__vcpu_except_flags(0)
703 #define EXCEPT_AA32_IABT	__vcpu_except_flags(1)
704 #define EXCEPT_AA32_DABT	__vcpu_except_flags(2)
705 /* For AArch64: */
706 #define EXCEPT_AA64_EL1_SYNC	__vcpu_except_flags(0)
707 #define EXCEPT_AA64_EL1_IRQ	__vcpu_except_flags(1)
708 #define EXCEPT_AA64_EL1_FIQ	__vcpu_except_flags(2)
709 #define EXCEPT_AA64_EL1_SERR	__vcpu_except_flags(3)
710 /* For AArch64 with NV: */
711 #define EXCEPT_AA64_EL2_SYNC	__vcpu_except_flags(4)
712 #define EXCEPT_AA64_EL2_IRQ	__vcpu_except_flags(5)
713 #define EXCEPT_AA64_EL2_FIQ	__vcpu_except_flags(6)
714 #define EXCEPT_AA64_EL2_SERR	__vcpu_except_flags(7)
715 /* Guest debug is live */
716 #define DEBUG_DIRTY		__vcpu_single_flag(iflags, BIT(4))
717 /* Save SPE context if active  */
718 #define DEBUG_STATE_SAVE_SPE	__vcpu_single_flag(iflags, BIT(5))
719 /* Save TRBE context if active  */
720 #define DEBUG_STATE_SAVE_TRBE	__vcpu_single_flag(iflags, BIT(6))
721 /* vcpu running in HYP context */
722 #define VCPU_HYP_CONTEXT	__vcpu_single_flag(iflags, BIT(7))
723 
724 /* SVE enabled for host EL0 */
725 #define HOST_SVE_ENABLED	__vcpu_single_flag(sflags, BIT(0))
726 /* SME enabled for EL0 */
727 #define HOST_SME_ENABLED	__vcpu_single_flag(sflags, BIT(1))
728 /* Physical CPU not in supported_cpus */
729 #define ON_UNSUPPORTED_CPU	__vcpu_single_flag(sflags, BIT(2))
730 /* WFIT instruction trapped */
731 #define IN_WFIT			__vcpu_single_flag(sflags, BIT(3))
732 /* vcpu system registers loaded on physical CPU */
733 #define SYSREGS_ON_CPU		__vcpu_single_flag(sflags, BIT(4))
734 /* Software step state is Active-pending */
735 #define DBG_SS_ACTIVE_PENDING	__vcpu_single_flag(sflags, BIT(5))
736 /* PMUSERENR for the guest EL0 is on physical CPU */
737 #define PMUSERENR_ON_CPU	__vcpu_single_flag(sflags, BIT(6))
738 /* WFI instruction trapped */
739 #define IN_WFI			__vcpu_single_flag(sflags, BIT(7))
740 
741 
742 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
743 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) +	\
744 			     sve_ffr_offset((vcpu)->arch.sve_max_vl))
745 
746 #define vcpu_sve_max_vq(vcpu)	sve_vq_from_vl((vcpu)->arch.sve_max_vl)
747 
748 #define vcpu_sve_state_size(vcpu) ({					\
749 	size_t __size_ret;						\
750 	unsigned int __vcpu_vq;						\
751 									\
752 	if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) {		\
753 		__size_ret = 0;						\
754 	} else {							\
755 		__vcpu_vq = vcpu_sve_max_vq(vcpu);			\
756 		__size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq);		\
757 	}								\
758 									\
759 	__size_ret;							\
760 })
761 
762 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
763 				 KVM_GUESTDBG_USE_SW_BP | \
764 				 KVM_GUESTDBG_USE_HW | \
765 				 KVM_GUESTDBG_SINGLESTEP)
766 
767 #define vcpu_has_sve(vcpu) (system_supports_sve() &&			\
768 			    vcpu_get_flag(vcpu, GUEST_HAS_SVE))
769 
770 #ifdef CONFIG_ARM64_PTR_AUTH
771 #define vcpu_has_ptrauth(vcpu)						\
772 	((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) ||		\
773 	  cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) &&		\
774 	  vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH))
775 #else
776 #define vcpu_has_ptrauth(vcpu)		false
777 #endif
778 
779 #define vcpu_on_unsupported_cpu(vcpu)					\
780 	vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
781 
782 #define vcpu_set_on_unsupported_cpu(vcpu)				\
783 	vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
784 
785 #define vcpu_clear_on_unsupported_cpu(vcpu)				\
786 	vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
787 
788 #define vcpu_gp_regs(v)		(&(v)->arch.ctxt.regs)
789 
790 /*
791  * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
792  * memory backed version of a register, and not the one most recently
793  * accessed by a running VCPU.  For example, for userspace access or
794  * for system registers that are never context switched, but only
795  * emulated.
796  */
797 #define __ctxt_sys_reg(c,r)	(&(c)->sys_regs[(r)])
798 
799 #define ctxt_sys_reg(c,r)	(*__ctxt_sys_reg(c,r))
800 
801 #define __vcpu_sys_reg(v,r)	(ctxt_sys_reg(&(v)->arch.ctxt, (r)))
802 
803 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
804 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
805 
__vcpu_read_sys_reg_from_cpu(int reg,u64 * val)806 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
807 {
808 	/*
809 	 * *** VHE ONLY ***
810 	 *
811 	 * System registers listed in the switch are not saved on every
812 	 * exit from the guest but are only saved on vcpu_put.
813 	 *
814 	 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
815 	 * should never be listed below, because the guest cannot modify its
816 	 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
817 	 * thread when emulating cross-VCPU communication.
818 	 */
819 	if (!has_vhe())
820 		return false;
821 
822 	switch (reg) {
823 	case SCTLR_EL1:		*val = read_sysreg_s(SYS_SCTLR_EL12);	break;
824 	case CPACR_EL1:		*val = read_sysreg_s(SYS_CPACR_EL12);	break;
825 	case TTBR0_EL1:		*val = read_sysreg_s(SYS_TTBR0_EL12);	break;
826 	case TTBR1_EL1:		*val = read_sysreg_s(SYS_TTBR1_EL12);	break;
827 	case TCR_EL1:		*val = read_sysreg_s(SYS_TCR_EL12);	break;
828 	case ESR_EL1:		*val = read_sysreg_s(SYS_ESR_EL12);	break;
829 	case AFSR0_EL1:		*val = read_sysreg_s(SYS_AFSR0_EL12);	break;
830 	case AFSR1_EL1:		*val = read_sysreg_s(SYS_AFSR1_EL12);	break;
831 	case FAR_EL1:		*val = read_sysreg_s(SYS_FAR_EL12);	break;
832 	case MAIR_EL1:		*val = read_sysreg_s(SYS_MAIR_EL12);	break;
833 	case VBAR_EL1:		*val = read_sysreg_s(SYS_VBAR_EL12);	break;
834 	case CONTEXTIDR_EL1:	*val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
835 	case TPIDR_EL0:		*val = read_sysreg_s(SYS_TPIDR_EL0);	break;
836 	case TPIDRRO_EL0:	*val = read_sysreg_s(SYS_TPIDRRO_EL0);	break;
837 	case TPIDR_EL1:		*val = read_sysreg_s(SYS_TPIDR_EL1);	break;
838 	case AMAIR_EL1:		*val = read_sysreg_s(SYS_AMAIR_EL12);	break;
839 	case CNTKCTL_EL1:	*val = read_sysreg_s(SYS_CNTKCTL_EL12);	break;
840 	case ELR_EL1:		*val = read_sysreg_s(SYS_ELR_EL12);	break;
841 	case PAR_EL1:		*val = read_sysreg_par();		break;
842 	case DACR32_EL2:	*val = read_sysreg_s(SYS_DACR32_EL2);	break;
843 	case IFSR32_EL2:	*val = read_sysreg_s(SYS_IFSR32_EL2);	break;
844 	case DBGVCR32_EL2:	*val = read_sysreg_s(SYS_DBGVCR32_EL2);	break;
845 	default:		return false;
846 	}
847 
848 	return true;
849 }
850 
__vcpu_write_sys_reg_to_cpu(u64 val,int reg)851 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
852 {
853 	/*
854 	 * *** VHE ONLY ***
855 	 *
856 	 * System registers listed in the switch are not restored on every
857 	 * entry to the guest but are only restored on vcpu_load.
858 	 *
859 	 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
860 	 * should never be listed below, because the MPIDR should only be set
861 	 * once, before running the VCPU, and never changed later.
862 	 */
863 	if (!has_vhe())
864 		return false;
865 
866 	switch (reg) {
867 	case SCTLR_EL1:		write_sysreg_s(val, SYS_SCTLR_EL12);	break;
868 	case CPACR_EL1:		write_sysreg_s(val, SYS_CPACR_EL12);	break;
869 	case TTBR0_EL1:		write_sysreg_s(val, SYS_TTBR0_EL12);	break;
870 	case TTBR1_EL1:		write_sysreg_s(val, SYS_TTBR1_EL12);	break;
871 	case TCR_EL1:		write_sysreg_s(val, SYS_TCR_EL12);	break;
872 	case ESR_EL1:		write_sysreg_s(val, SYS_ESR_EL12);	break;
873 	case AFSR0_EL1:		write_sysreg_s(val, SYS_AFSR0_EL12);	break;
874 	case AFSR1_EL1:		write_sysreg_s(val, SYS_AFSR1_EL12);	break;
875 	case FAR_EL1:		write_sysreg_s(val, SYS_FAR_EL12);	break;
876 	case MAIR_EL1:		write_sysreg_s(val, SYS_MAIR_EL12);	break;
877 	case VBAR_EL1:		write_sysreg_s(val, SYS_VBAR_EL12);	break;
878 	case CONTEXTIDR_EL1:	write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
879 	case TPIDR_EL0:		write_sysreg_s(val, SYS_TPIDR_EL0);	break;
880 	case TPIDRRO_EL0:	write_sysreg_s(val, SYS_TPIDRRO_EL0);	break;
881 	case TPIDR_EL1:		write_sysreg_s(val, SYS_TPIDR_EL1);	break;
882 	case AMAIR_EL1:		write_sysreg_s(val, SYS_AMAIR_EL12);	break;
883 	case CNTKCTL_EL1:	write_sysreg_s(val, SYS_CNTKCTL_EL12);	break;
884 	case ELR_EL1:		write_sysreg_s(val, SYS_ELR_EL12);	break;
885 	case PAR_EL1:		write_sysreg_s(val, SYS_PAR_EL1);	break;
886 	case DACR32_EL2:	write_sysreg_s(val, SYS_DACR32_EL2);	break;
887 	case IFSR32_EL2:	write_sysreg_s(val, SYS_IFSR32_EL2);	break;
888 	case DBGVCR32_EL2:	write_sysreg_s(val, SYS_DBGVCR32_EL2);	break;
889 	default:		return false;
890 	}
891 
892 	return true;
893 }
894 
895 struct kvm_vm_stat {
896 	struct kvm_vm_stat_generic generic;
897 };
898 
899 struct kvm_vcpu_stat {
900 	struct kvm_vcpu_stat_generic generic;
901 	u64 hvc_exit_stat;
902 	u64 wfe_exit_stat;
903 	u64 wfi_exit_stat;
904 	u64 mmio_exit_user;
905 	u64 mmio_exit_kernel;
906 	u64 signal_exits;
907 	u64 exits;
908 };
909 
910 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
911 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
912 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
913 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
914 
915 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
916 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
917 
918 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
919 			      struct kvm_vcpu_events *events);
920 
921 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
922 			      struct kvm_vcpu_events *events);
923 
924 #define KVM_ARCH_WANT_MMU_NOTIFIER
925 
926 void kvm_arm_halt_guest(struct kvm *kvm);
927 void kvm_arm_resume_guest(struct kvm *kvm);
928 
929 #define vcpu_has_run_once(vcpu)	!!rcu_access_pointer((vcpu)->pid)
930 
931 #ifndef __KVM_NVHE_HYPERVISOR__
932 #define kvm_call_hyp_nvhe(f, ...)						\
933 	({								\
934 		struct arm_smccc_res res;				\
935 									\
936 		arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f),		\
937 				  ##__VA_ARGS__, &res);			\
938 		WARN_ON(res.a0 != SMCCC_RET_SUCCESS);			\
939 									\
940 		res.a1;							\
941 	})
942 
943 /*
944  * The couple of isb() below are there to guarantee the same behaviour
945  * on VHE as on !VHE, where the eret to EL1 acts as a context
946  * synchronization event.
947  */
948 #define kvm_call_hyp(f, ...)						\
949 	do {								\
950 		if (has_vhe()) {					\
951 			f(__VA_ARGS__);					\
952 			isb();						\
953 		} else {						\
954 			kvm_call_hyp_nvhe(f, ##__VA_ARGS__);		\
955 		}							\
956 	} while(0)
957 
958 #define kvm_call_hyp_ret(f, ...)					\
959 	({								\
960 		typeof(f(__VA_ARGS__)) ret;				\
961 									\
962 		if (has_vhe()) {					\
963 			ret = f(__VA_ARGS__);				\
964 			isb();						\
965 		} else {						\
966 			ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__);	\
967 		}							\
968 									\
969 		ret;							\
970 	})
971 #else /* __KVM_NVHE_HYPERVISOR__ */
972 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
973 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
974 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
975 #endif /* __KVM_NVHE_HYPERVISOR__ */
976 
977 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
978 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
979 
980 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
981 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
982 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
983 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
984 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
985 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
986 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
987 
988 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
989 
990 int __init kvm_sys_reg_table_init(void);
991 int __init populate_nv_trap_config(void);
992 
993 bool lock_all_vcpus(struct kvm *kvm);
994 void unlock_all_vcpus(struct kvm *kvm);
995 
996 /* MMIO helpers */
997 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
998 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
999 
1000 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
1001 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
1002 
1003 /*
1004  * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
1005  * arrived in guest context.  For arm64, any event that arrives while a vCPU is
1006  * loaded is considered to be "in guest".
1007  */
kvm_arch_pmi_in_guest(struct kvm_vcpu * vcpu)1008 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
1009 {
1010 	return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
1011 }
1012 
1013 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
1014 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
1015 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
1016 
1017 bool kvm_arm_pvtime_supported(void);
1018 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
1019 			    struct kvm_device_attr *attr);
1020 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
1021 			    struct kvm_device_attr *attr);
1022 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
1023 			    struct kvm_device_attr *attr);
1024 
1025 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
1026 int __init kvm_arm_vmid_alloc_init(void);
1027 void __init kvm_arm_vmid_alloc_free(void);
1028 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
1029 void kvm_arm_vmid_clear_active(void);
1030 
kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)1031 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
1032 {
1033 	vcpu_arch->steal.base = INVALID_GPA;
1034 }
1035 
kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)1036 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
1037 {
1038 	return (vcpu_arch->steal.base != INVALID_GPA);
1039 }
1040 
1041 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
1042 
1043 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
1044 
1045 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
1046 
kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)1047 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
1048 {
1049 	/* The host's MPIDR is immutable, so let's set it up at boot time */
1050 	ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
1051 }
1052 
kvm_system_needs_idmapped_vectors(void)1053 static inline bool kvm_system_needs_idmapped_vectors(void)
1054 {
1055 	return cpus_have_const_cap(ARM64_SPECTRE_V3A);
1056 }
1057 
kvm_arch_sync_events(struct kvm * kvm)1058 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)1059 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
1060 
1061 void kvm_arm_init_debug(void);
1062 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
1063 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
1064 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
1065 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
1066 
1067 #define kvm_vcpu_os_lock_enabled(vcpu)		\
1068 	(!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK))
1069 
1070 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1071 			       struct kvm_device_attr *attr);
1072 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1073 			       struct kvm_device_attr *attr);
1074 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1075 			       struct kvm_device_attr *attr);
1076 
1077 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1078 			       struct kvm_arm_copy_mte_tags *copy_tags);
1079 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
1080 				    struct kvm_arm_counter_offset *offset);
1081 
1082 /* Guest/host FPSIMD coordination helpers */
1083 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1084 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1085 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1086 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1087 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1088 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu);
1089 
kvm_pmu_counter_deferred(struct perf_event_attr * attr)1090 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1091 {
1092 	return (!has_vhe() && attr->exclude_host);
1093 }
1094 
1095 /* Flags for host debug state */
1096 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
1097 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
1098 
1099 #ifdef CONFIG_KVM
1100 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
1101 void kvm_clr_pmu_events(u32 clr);
1102 bool kvm_set_pmuserenr(u64 val);
1103 #else
kvm_set_pmu_events(u32 set,struct perf_event_attr * attr)1104 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
kvm_clr_pmu_events(u32 clr)1105 static inline void kvm_clr_pmu_events(u32 clr) {}
kvm_set_pmuserenr(u64 val)1106 static inline bool kvm_set_pmuserenr(u64 val)
1107 {
1108 	return false;
1109 }
1110 #endif
1111 
1112 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
1113 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
1114 
1115 int __init kvm_set_ipa_limit(void);
1116 
1117 #define __KVM_HAVE_ARCH_VM_ALLOC
1118 struct kvm *kvm_arch_alloc_vm(void);
1119 
1120 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS
1121 
1122 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE
1123 
kvm_vm_is_protected(struct kvm * kvm)1124 static inline bool kvm_vm_is_protected(struct kvm *kvm)
1125 {
1126 	return false;
1127 }
1128 
1129 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1130 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1131 
1132 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1133 
1134 #define kvm_has_mte(kvm)					\
1135 	(system_supports_mte() &&				\
1136 	 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1137 
1138 #define kvm_supports_32bit_el0()				\
1139 	(system_supports_32bit_el0() &&				\
1140 	 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1141 
1142 #define kvm_vm_has_ran_once(kvm)					\
1143 	(test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags))
1144 
1145 int kvm_trng_call(struct kvm_vcpu *vcpu);
1146 #ifdef CONFIG_KVM
1147 extern phys_addr_t hyp_mem_base;
1148 extern phys_addr_t hyp_mem_size;
1149 void __init kvm_hyp_reserve(void);
1150 #else
kvm_hyp_reserve(void)1151 static inline void kvm_hyp_reserve(void) { }
1152 #endif
1153 
1154 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1155 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1156 
1157 #endif /* __ARM64_KVM_HOST_H__ */
1158