1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * (C) 2018 MediaTek Inc. 4 * Copyright (C) 2022 BayLibre SAS 5 * Fabien Parent <fparent@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com> 7 */ 8#include <dt-bindings/clock/mediatek,mt8365-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12 13/ { 14 compatible = "mediatek,mt8365"; 15 interrupt-parent = <&sysirq>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cluster0_opp: opp-table-0 { 24 compatible = "operating-points-v2"; 25 opp-shared; 26 27 opp-850000000 { 28 opp-hz = /bits/ 64 <850000000>; 29 opp-microvolt = <650000>; 30 }; 31 32 opp-918000000 { 33 opp-hz = /bits/ 64 <918000000>; 34 opp-microvolt = <668750>; 35 }; 36 37 opp-987000000 { 38 opp-hz = /bits/ 64 <987000000>; 39 opp-microvolt = <687500>; 40 }; 41 42 opp-1056000000 { 43 opp-hz = /bits/ 64 <1056000000>; 44 opp-microvolt = <706250>; 45 }; 46 47 opp-1125000000 { 48 opp-hz = /bits/ 64 <1125000000>; 49 opp-microvolt = <725000>; 50 }; 51 52 opp-1216000000 { 53 opp-hz = /bits/ 64 <1216000000>; 54 opp-microvolt = <750000>; 55 }; 56 57 opp-1308000000 { 58 opp-hz = /bits/ 64 <1308000000>; 59 opp-microvolt = <775000>; 60 }; 61 62 opp-1400000000 { 63 opp-hz = /bits/ 64 <1400000000>; 64 opp-microvolt = <800000>; 65 }; 66 67 opp-1466000000 { 68 opp-hz = /bits/ 64 <1466000000>; 69 opp-microvolt = <825000>; 70 }; 71 72 opp-1533000000 { 73 opp-hz = /bits/ 64 <1533000000>; 74 opp-microvolt = <850000>; 75 }; 76 77 opp-1633000000 { 78 opp-hz = /bits/ 64 <1633000000>; 79 opp-microvolt = <887500>; 80 }; 81 82 opp-1700000000 { 83 opp-hz = /bits/ 64 <1700000000>; 84 opp-microvolt = <912500>; 85 }; 86 87 opp-1767000000 { 88 opp-hz = /bits/ 64 <1767000000>; 89 opp-microvolt = <937500>; 90 }; 91 92 opp-1834000000 { 93 opp-hz = /bits/ 64 <1834000000>; 94 opp-microvolt = <962500>; 95 }; 96 97 opp-1917000000 { 98 opp-hz = /bits/ 64 <1917000000>; 99 opp-microvolt = <993750>; 100 }; 101 102 opp-2001000000 { 103 opp-hz = /bits/ 64 <2001000000>; 104 opp-microvolt = <1025000>; 105 }; 106 }; 107 108 cpu-map { 109 cluster0 { 110 core0 { 111 cpu = <&cpu0>; 112 }; 113 core1 { 114 cpu = <&cpu1>; 115 }; 116 core2 { 117 cpu = <&cpu2>; 118 }; 119 core3 { 120 cpu = <&cpu3>; 121 }; 122 }; 123 }; 124 125 cpu0: cpu@0 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53"; 128 reg = <0x0>; 129 #cooling-cells = <2>; 130 enable-method = "psci"; 131 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 132 i-cache-size = <0x8000>; 133 i-cache-line-size = <64>; 134 i-cache-sets = <256>; 135 d-cache-size = <0x8000>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <256>; 138 next-level-cache = <&l2>; 139 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 140 <&apmixedsys CLK_APMIXED_MAINPLL>; 141 clock-names = "cpu", "intermediate"; 142 operating-points-v2 = <&cluster0_opp>; 143 }; 144 145 cpu1: cpu@1 { 146 device_type = "cpu"; 147 compatible = "arm,cortex-a53"; 148 reg = <0x1>; 149 #cooling-cells = <2>; 150 enable-method = "psci"; 151 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 152 i-cache-size = <0x8000>; 153 i-cache-line-size = <64>; 154 i-cache-sets = <256>; 155 d-cache-size = <0x8000>; 156 d-cache-line-size = <64>; 157 d-cache-sets = <256>; 158 next-level-cache = <&l2>; 159 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 160 <&apmixedsys CLK_APMIXED_MAINPLL>; 161 clock-names = "cpu", "intermediate", "armpll"; 162 operating-points-v2 = <&cluster0_opp>; 163 }; 164 165 cpu2: cpu@2 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a53"; 168 reg = <0x2>; 169 #cooling-cells = <2>; 170 enable-method = "psci"; 171 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 172 i-cache-size = <0x8000>; 173 i-cache-line-size = <64>; 174 i-cache-sets = <256>; 175 d-cache-size = <0x8000>; 176 d-cache-line-size = <64>; 177 d-cache-sets = <256>; 178 next-level-cache = <&l2>; 179 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 180 <&apmixedsys CLK_APMIXED_MAINPLL>; 181 clock-names = "cpu", "intermediate", "armpll"; 182 operating-points-v2 = <&cluster0_opp>; 183 }; 184 185 cpu3: cpu@3 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a53"; 188 reg = <0x3>; 189 #cooling-cells = <2>; 190 enable-method = "psci"; 191 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 192 i-cache-size = <0x8000>; 193 i-cache-line-size = <64>; 194 i-cache-sets = <256>; 195 d-cache-size = <0x8000>; 196 d-cache-line-size = <64>; 197 d-cache-sets = <256>; 198 next-level-cache = <&l2>; 199 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 200 <&apmixedsys CLK_APMIXED_MAINPLL>; 201 clock-names = "cpu", "intermediate", "armpll"; 202 operating-points-v2 = <&cluster0_opp>; 203 }; 204 205 idle-states { 206 entry-method = "psci"; 207 208 CPU_MCDI: cpu-mcdi { 209 compatible = "arm,idle-state"; 210 local-timer-stop; 211 arm,psci-suspend-param = <0x00010001>; 212 entry-latency-us = <300>; 213 exit-latency-us = <200>; 214 min-residency-us = <1000>; 215 }; 216 217 CLUSTER_MCDI: cluster-mcdi { 218 compatible = "arm,idle-state"; 219 local-timer-stop; 220 arm,psci-suspend-param = <0x01010001>; 221 entry-latency-us = <350>; 222 exit-latency-us = <250>; 223 min-residency-us = <1200>; 224 }; 225 226 CLUSTER_DPIDLE: cluster-dpidle { 227 compatible = "arm,idle-state"; 228 local-timer-stop; 229 arm,psci-suspend-param = <0x01010004>; 230 entry-latency-us = <300>; 231 exit-latency-us = <800>; 232 min-residency-us = <3300>; 233 }; 234 }; 235 236 l2: l2-cache { 237 compatible = "cache"; 238 cache-level = <2>; 239 cache-size = <0x80000>; 240 cache-line-size = <64>; 241 cache-sets = <512>; 242 cache-unified; 243 }; 244 }; 245 246 clk26m: oscillator { 247 compatible = "fixed-clock"; 248 #clock-cells = <0>; 249 clock-frequency = <26000000>; 250 clock-output-names = "clk26m"; 251 }; 252 253 psci { 254 compatible = "arm,psci-1.0"; 255 method = "smc"; 256 }; 257 258 soc { 259 #address-cells = <2>; 260 #size-cells = <2>; 261 compatible = "simple-bus"; 262 ranges; 263 264 gic: interrupt-controller@c000000 { 265 compatible = "arm,gic-v3"; 266 #interrupt-cells = <3>; 267 interrupt-parent = <&gic>; 268 interrupt-controller; 269 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 270 <0 0x0c080000 0 0x80000>, /* GICR */ 271 <0 0x0c400000 0 0x2000>, /* GICC */ 272 <0 0x0c410000 0 0x1000>, /* GICH */ 273 <0 0x0c420000 0 0x2000>; /* GICV */ 274 275 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 topckgen: syscon@10000000 { 279 compatible = "mediatek,mt8365-topckgen", "syscon"; 280 reg = <0 0x10000000 0 0x1000>; 281 #clock-cells = <1>; 282 }; 283 284 infracfg: syscon@10001000 { 285 compatible = "mediatek,mt8365-infracfg", "syscon"; 286 reg = <0 0x10001000 0 0x1000>; 287 #clock-cells = <1>; 288 }; 289 290 pericfg: syscon@10003000 { 291 compatible = "mediatek,mt8365-pericfg", "syscon"; 292 reg = <0 0x10003000 0 0x1000>; 293 #clock-cells = <1>; 294 }; 295 296 syscfg_pctl: syscfg-pctl@10005000 { 297 compatible = "mediatek,mt8365-syscfg", "syscon"; 298 reg = <0 0x10005000 0 0x1000>; 299 }; 300 301 watchdog: watchdog@10007000 { 302 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; 303 reg = <0 0x10007000 0 0x100>; 304 #reset-cells = <1>; 305 }; 306 307 pio: pinctrl@1000b000 { 308 compatible = "mediatek,mt8365-pinctrl"; 309 reg = <0 0x1000b000 0 0x1000>; 310 mediatek,pctl-regmap = <&syscfg_pctl>; 311 gpio-controller; 312 #gpio-cells = <2>; 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 316 }; 317 318 apmixedsys: syscon@1000c000 { 319 compatible = "mediatek,mt8365-apmixedsys", "syscon"; 320 reg = <0 0x1000c000 0 0x1000>; 321 #clock-cells = <1>; 322 }; 323 324 pwrap: pwrap@1000d000 { 325 compatible = "mediatek,mt8365-pwrap"; 326 reg = <0 0x1000d000 0 0x1000>; 327 reg-names = "pwrap"; 328 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&infracfg CLK_IFR_PWRAP_SPI>, 330 <&infracfg CLK_IFR_PMIC_AP>, 331 <&infracfg CLK_IFR_PWRAP_SYS>, 332 <&infracfg CLK_IFR_PWRAP_TMR>; 333 clock-names = "spi", "wrap", "sys", "tmr"; 334 }; 335 336 keypad: keypad@10010000 { 337 compatible = "mediatek,mt6779-keypad"; 338 reg = <0 0x10010000 0 0x1000>; 339 wakeup-source; 340 interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 341 clocks = <&clk26m>; 342 clock-names = "kpd"; 343 status = "disabled"; 344 }; 345 346 mcucfg: syscon@10200000 { 347 compatible = "mediatek,mt8365-mcucfg", "syscon"; 348 reg = <0 0x10200000 0 0x2000>; 349 #clock-cells = <1>; 350 }; 351 352 sysirq: interrupt-controller@10200a80 { 353 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 354 interrupt-controller; 355 #interrupt-cells = <3>; 356 interrupt-parent = <&gic>; 357 reg = <0 0x10200a80 0 0x20>; 358 }; 359 360 infracfg_nao: infracfg@1020e000 { 361 compatible = "mediatek,mt8365-infracfg", "syscon"; 362 reg = <0 0x1020e000 0 0x1000>; 363 #clock-cells = <1>; 364 }; 365 366 rng: rng@1020f000 { 367 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 368 reg = <0 0x1020f000 0 0x100>; 369 clocks = <&infracfg CLK_IFR_TRNG>; 370 clock-names = "rng"; 371 }; 372 373 apdma: dma-controller@11000280 { 374 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 375 reg = <0 0x11000280 0 0x80>, 376 <0 0x11000300 0 0x80>, 377 <0 0x11000380 0 0x80>, 378 <0 0x11000400 0 0x80>, 379 <0 0x11000580 0 0x80>, 380 <0 0x11000600 0 0x80>; 381 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 382 <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 383 <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 384 <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 385 <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 386 <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 387 dma-requests = <6>; 388 clocks = <&infracfg CLK_IFR_AP_DMA>; 389 clock-names = "apdma"; 390 #dma-cells = <1>; 391 }; 392 393 uart0: serial@11002000 { 394 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 395 reg = <0 0x11002000 0 0x1000>; 396 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 397 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 398 clock-names = "baud", "bus"; 399 dmas = <&apdma 0>, <&apdma 1>; 400 dma-names = "tx", "rx"; 401 status = "disabled"; 402 }; 403 404 uart1: serial@11003000 { 405 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 406 reg = <0 0x11003000 0 0x1000>; 407 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 408 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 409 clock-names = "baud", "bus"; 410 dmas = <&apdma 2>, <&apdma 3>; 411 dma-names = "tx", "rx"; 412 status = "disabled"; 413 }; 414 415 uart2: serial@11004000 { 416 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 417 reg = <0 0x11004000 0 0x1000>; 418 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 419 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 420 clock-names = "baud", "bus"; 421 dmas = <&apdma 4>, <&apdma 5>; 422 dma-names = "tx", "rx"; 423 status = "disabled"; 424 }; 425 426 pwm: pwm@11006000 { 427 compatible = "mediatek,mt8365-pwm"; 428 reg = <0 0x11006000 0 0x1000>; 429 #pwm-cells = <2>; 430 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 431 clocks = <&infracfg CLK_IFR_PWM_HCLK>, 432 <&infracfg CLK_IFR_PWM>, 433 <&infracfg CLK_IFR_PWM1>, 434 <&infracfg CLK_IFR_PWM2>, 435 <&infracfg CLK_IFR_PWM3>; 436 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 437 }; 438 439 i2c0: i2c@11007000 { 440 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 441 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 442 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 443 clock-div = <1>; 444 clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 445 clock-names = "main", "dma"; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 status = "disabled"; 449 }; 450 451 i2c1: i2c@11008000 { 452 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 453 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 454 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 455 clock-div = <1>; 456 clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 457 clock-names = "main", "dma"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 status = "disabled"; 461 }; 462 463 i2c2: i2c@11009000 { 464 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 465 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 466 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 467 clock-div = <1>; 468 clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 469 clock-names = "main", "dma"; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 status = "disabled"; 473 }; 474 475 spi: spi@1100a000 { 476 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 477 reg = <0 0x1100a000 0 0x100>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 481 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 482 <&topckgen CLK_TOP_SPI_SEL>, 483 <&infracfg CLK_IFR_SPI0>; 484 clock-names = "parent-clk", "sel-clk", "spi-clk"; 485 status = "disabled"; 486 }; 487 488 i2c3: i2c@1100f000 { 489 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 490 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 491 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 492 clock-div = <1>; 493 clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 494 clock-names = "main", "dma"; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 status = "disabled"; 498 }; 499 500 ssusb: usb@11201000 { 501 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 502 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 503 reg-names = "mac", "ippc"; 504 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 505 phys = <&u2port0 PHY_TYPE_USB2>, 506 <&u2port1 PHY_TYPE_USB2>; 507 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 508 <&infracfg CLK_IFR_SSUSB_REF>, 509 <&infracfg CLK_IFR_SSUSB_SYS>, 510 <&infracfg CLK_IFR_ICUSB>; 511 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 512 #address-cells = <2>; 513 #size-cells = <2>; 514 ranges; 515 status = "disabled"; 516 517 usb_host: usb@11200000 { 518 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 519 reg = <0 0x11200000 0 0x1000>; 520 reg-names = "mac"; 521 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 522 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 523 <&infracfg CLK_IFR_SSUSB_REF>, 524 <&infracfg CLK_IFR_SSUSB_SYS>, 525 <&infracfg CLK_IFR_ICUSB>, 526 <&infracfg CLK_IFR_SSUSB_XHCI>; 527 clock-names = "sys_ck", "ref_ck", "mcu_ck", 528 "dma_ck", "xhci_ck"; 529 status = "disabled"; 530 }; 531 }; 532 533 mmc0: mmc@11230000 { 534 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 535 reg = <0 0x11230000 0 0x1000>, 536 <0 0x11cd0000 0 0x1000>; 537 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; 538 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 539 <&infracfg CLK_IFR_MSDC0_HCLK>, 540 <&infracfg CLK_IFR_MSDC0_SRC>; 541 clock-names = "source", "hclk", "source_cg"; 542 status = "disabled"; 543 }; 544 545 mmc1: mmc@11240000 { 546 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 547 reg = <0 0x11240000 0 0x1000>, 548 <0 0x11c90000 0 0x1000>; 549 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; 550 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 551 <&infracfg CLK_IFR_MSDC1_HCLK>, 552 <&infracfg CLK_IFR_MSDC1_SRC>; 553 clock-names = "source", "hclk", "source_cg"; 554 status = "disabled"; 555 }; 556 557 mmc2: mmc@11250000 { 558 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 559 reg = <0 0x11250000 0 0x1000>, 560 <0 0x11c60000 0 0x1000>; 561 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; 562 clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, 563 <&infracfg CLK_IFR_MSDC2_HCLK>, 564 <&infracfg CLK_IFR_MSDC2_SRC>, 565 <&infracfg CLK_IFR_MSDC2_BK>, 566 <&infracfg CLK_IFR_AP_MSDC0>; 567 clock-names = "source", "hclk", "source_cg", 568 "bus_clk", "sys_cg"; 569 status = "disabled"; 570 }; 571 572 ethernet: ethernet@112a0000 { 573 compatible = "mediatek,mt8365-eth"; 574 reg = <0 0x112a0000 0 0x1000>; 575 mediatek,pericfg = <&infracfg>; 576 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&topckgen CLK_TOP_ETH_SEL>, 578 <&infracfg CLK_IFR_NIC_AXI>, 579 <&infracfg CLK_IFR_NIC_SLV_AXI>; 580 clock-names = "core", "reg", "trans"; 581 status = "disabled"; 582 }; 583 584 u3phy: t-phy@11cc0000 { 585 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 586 #address-cells = <1>; 587 #size-cells = <1>; 588 ranges = <0 0 0x11cc0000 0x9000>; 589 590 u2port0: usb-phy@0 { 591 reg = <0x0 0x400>; 592 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 593 <&topckgen CLK_TOP_USB20_48M_EN>; 594 clock-names = "ref", "da_ref"; 595 #phy-cells = <1>; 596 }; 597 598 u2port1: usb-phy@1000 { 599 reg = <0x1000 0x400>; 600 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 601 <&topckgen CLK_TOP_USB20_48M_EN>; 602 clock-names = "ref", "da_ref"; 603 #phy-cells = <1>; 604 }; 605 }; 606 }; 607 608 timer { 609 compatible = "arm,armv8-timer"; 610 interrupt-parent = <&gic>; 611 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 612 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 613 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 614 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 615 }; 616 617 system_clk: dummy13m { 618 compatible = "fixed-clock"; 619 clock-frequency = <13000000>; 620 #clock-cells = <0>; 621 }; 622 623 systimer: timer@10017000 { 624 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 625 reg = <0 0x10017000 0 0x100>; 626 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&system_clk>; 628 clock-names = "clk13m"; 629 }; 630}; 631