1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	compatible = "brcm,bcm6858", "brcm,bcmbca";
11	#address-cells = <2>;
12	#size-cells = <2>;
13
14	interrupt-parent = <&gic>;
15
16	cpus {
17		#address-cells = <2>;
18		#size-cells = <0>;
19
20		B53_0: cpu@0 {
21			compatible = "brcm,brahma-b53";
22			device_type = "cpu";
23			reg = <0x0 0x0>;
24			next-level-cache = <&L2_0>;
25			enable-method = "psci";
26		};
27
28		B53_1: cpu@1 {
29			compatible = "brcm,brahma-b53";
30			device_type = "cpu";
31			reg = <0x0 0x1>;
32			next-level-cache = <&L2_0>;
33			enable-method = "psci";
34		};
35
36		B53_2: cpu@2 {
37			compatible = "brcm,brahma-b53";
38			device_type = "cpu";
39			reg = <0x0 0x2>;
40			next-level-cache = <&L2_0>;
41			enable-method = "psci";
42		};
43
44		B53_3: cpu@3 {
45			compatible = "brcm,brahma-b53";
46			device_type = "cpu";
47			reg = <0x0 0x3>;
48			next-level-cache = <&L2_0>;
49			enable-method = "psci";
50		};
51		L2_0: l2-cache0 {
52			compatible = "cache";
53			cache-level = <2>;
54			cache-unified;
55		};
56	};
57
58	timer {
59		compatible = "arm,armv8-timer";
60		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
64	};
65
66	pmu: pmu {
67		compatible = "arm,armv8-pmuv3";
68		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
69			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
70			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
71			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
72		interrupt-affinity = <&B53_0>, <&B53_1>,
73			<&B53_2>, <&B53_3>;
74	};
75
76	clocks: clocks {
77		periph_clk:periph-clk {
78			compatible = "fixed-clock";
79			#clock-cells = <0>;
80			clock-frequency = <200000000>;
81		};
82
83		hsspi_pll: hsspi-pll {
84			compatible = "fixed-clock";
85			#clock-cells = <0>;
86			clock-frequency = <400000000>;
87		};
88	};
89
90	psci {
91		compatible = "arm,psci-0.2";
92		method = "smc";
93	};
94
95	axi@81000000 {
96		compatible = "simple-bus";
97		#address-cells = <1>;
98		#size-cells = <1>;
99		ranges = <0x0 0x0 0x81000000 0x8000>;
100
101		gic: interrupt-controller@1000 {
102			compatible = "arm,gic-400";
103			#interrupt-cells = <3>;
104			interrupt-controller;
105			reg = <0x1000 0x1000>, /* GICD */
106				<0x2000 0x2000>, /* GICC */
107				<0x4000 0x2000>, /* GICH */
108				<0x6000 0x2000>; /* GICV */
109			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
110					IRQ_TYPE_LEVEL_HIGH)>;
111		};
112	};
113
114	bus@ff800000 {
115		compatible = "simple-bus";
116		#address-cells = <1>;
117		#size-cells = <1>;
118		ranges = <0x0 0x0 0xff800000 0x62000>;
119
120		twd: timer-mfd@400 {
121			compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
122			reg = <0x400 0x4c>;
123			ranges = <0x0 0x400 0x4c>;
124
125			#address-cells = <1>;
126			#size-cells = <1>;
127
128			timer@0 {
129				compatible = "brcm,bcm63138-timer";
130				reg = <0x0 0x28>;
131			};
132
133			watchdog@28 {
134				compatible = "brcm,bcm6345-wdt";
135				reg = <0x28 0x8>;
136			};
137		};
138
139		uart0: serial@640 {
140			compatible = "brcm,bcm6345-uart";
141			reg = <0x640 0x18>;
142			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
143			clocks = <&periph_clk>;
144			clock-names = "refclk";
145			status = "disabled";
146		};
147
148		hsspi: spi@1000 {
149			#address-cells = <1>;
150			#size-cells = <0>;
151			compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
152			reg = <0x1000 0x600>;
153			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
154			clocks = <&hsspi_pll &hsspi_pll>;
155			clock-names = "hsspi", "pll";
156			num-cs = <8>;
157			status = "disabled";
158		};
159	};
160};
161