1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
4  */
5 
6 #ifndef __MACH_TEGRA_SLEEP_H
7 #define __MACH_TEGRA_SLEEP_H
8 
9 #include "iomap.h"
10 #include "irammap.h"
11 
12 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
13 					+ IO_CPU_VIRT)
14 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
15 					+ IO_PPSB_VIRT)
16 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
17 					+ IO_PPSB_VIRT)
18 #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
19 					+ IO_APB_VIRT)
20 #define TEGRA_PMC_VIRT	(TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
21 
22 #define TEGRA_IRAM_RESET_BASE_VIRT (IO_IRAM_VIRT + \
23 				TEGRA_IRAM_RESET_HANDLER_OFFSET)
24 
25 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
26 #define PMC_SCRATCH37	0x130
27 #define PMC_SCRATCH38	0x134
28 #define PMC_SCRATCH39	0x138
29 #define PMC_SCRATCH41	0x140
30 
31 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
32 #define CPU_RESETTABLE		2
33 #define CPU_RESETTABLE_SOON	1
34 #define CPU_NOT_RESETTABLE	0
35 #endif
36 
37 /* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
38 #define TEGRA_FLUSH_CACHE_LOUIS	0
39 #define TEGRA_FLUSH_CACHE_ALL	1
40 
41 #ifdef __ASSEMBLY__
42 /* waits until the microsecond counter (base) is > rn */
43 .macro wait_until, rn, base, tmp
44 	add	\rn, \rn, #1
45 1001:	ldr	\tmp, [\base]
46 	cmp	\tmp, \rn
47 	bmi	1001b
48 .endm
49 
50 /* returns the offset of the flow controller halt register for a cpu */
51 .macro cpu_to_halt_reg rd, rcpu
52 	cmp	\rcpu, #0
53 	subne	\rd, \rcpu, #1
54 	movne	\rd, \rd, lsl #3
55 	addne	\rd, \rd, #0x14
56 	moveq	\rd, #0
57 .endm
58 
59 /* returns the offset of the flow controller csr register for a cpu */
60 .macro cpu_to_csr_reg rd, rcpu
61 	cmp	\rcpu, #0
62 	subne	\rd, \rcpu, #1
63 	movne	\rd, \rd, lsl #3
64 	addne	\rd, \rd, #0x18
65 	moveq	\rd, #8
66 .endm
67 
68 /* returns the ID of the current processor */
69 .macro cpu_id, rd
70 	mrc	p15, 0, \rd, c0, c0, 5
71 	and	\rd, \rd, #0xF
72 .endm
73 
74 /* loads a 32-bit value into a register without a data access */
75 .macro mov32, reg, val
76 	movw	\reg, #:lower16:\val
77 	movt	\reg, #:upper16:\val
78 .endm
79 
80 /* Marco to check CPU part num */
81 .macro check_cpu_part_num part_num, tmp1, tmp2
82 	mrc	p15, 0, \tmp1, c0, c0, 0
83 	ubfx	\tmp1, \tmp1, #4, #12
84 	mov32	\tmp2, \part_num
85 	cmp	\tmp1, \tmp2
86 .endm
87 
88 /* Macro to exit SMP coherency. */
89 .macro exit_smp, tmp1, tmp2
90 	mrc	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
91 	bic	\tmp1, \tmp1, #(1<<6) | (1<<0)	@ clear ACTLR.SMP | ACTLR.FW
92 	mcr	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
93 	isb
94 #ifdef CONFIG_HAVE_ARM_SCU
95 	check_cpu_part_num 0xc09, \tmp1, \tmp2
96 	mrceq	p15, 0, \tmp1, c0, c0, 5
97 	andeq	\tmp1, \tmp1, #0xF
98 	moveq	\tmp1, \tmp1, lsl #2
99 	moveq	\tmp2, #0xf
100 	moveq	\tmp2, \tmp2, lsl \tmp1
101 	ldreq	\tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
102 	streq	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU
103 	dsb
104 #endif
105 .endm
106 
107 /* Macro to check Tegra revision */
108 #define APB_MISC_GP_HIDREV	0x804
109 .macro tegra_get_soc_id base, tmp1
110 	mov32	\tmp1, \base
111 	ldr	\tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
112 	and	\tmp1, \tmp1, #0xff00
113 	mov	\tmp1, \tmp1, lsr #8
114 .endm
115 
116 #else
117 void tegra_resume(void);
118 int tegra_sleep_cpu_finish(unsigned long);
119 void tegra_disable_clean_inv_dcache(u32 flag);
120 
121 void tegra20_hotplug_shutdown(void);
122 void tegra30_hotplug_shutdown(void);
123 
124 void tegra20_tear_down_cpu(void);
125 void tegra30_tear_down_cpu(void);
126 
127 #endif
128 #endif
129