1# SPDX-License-Identifier: GPL-2.0+ 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mfd/allwinner,sun8i-a23-prcm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner A23 PRCM 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13deprecated: true 14 15properties: 16 compatible: 17 const: allwinner,sun8i-a23-prcm 18 19 reg: 20 maxItems: 1 21 22patternProperties: 23 "^.*(clk|rst|codec).*$": 24 type: object 25 unevaluatedProperties: false 26 27 properties: 28 compatible: 29 enum: 30 - fixed-factor-clock 31 - allwinner,sun8i-a23-apb0-clk 32 - allwinner,sun8i-a23-apb0-gates-clk 33 - allwinner,sun6i-a31-clock-reset 34 - allwinner,sun8i-a23-codec-analog 35 36 required: 37 - compatible 38 39 allOf: 40 - if: 41 properties: 42 compatible: 43 contains: 44 const: fixed-factor-clock 45 46 then: 47 $ref: /schemas/clock/fixed-factor-clock.yaml# 48 49 - if: 50 properties: 51 compatible: 52 contains: 53 const: allwinner,sun8i-a23-apb0-clk 54 55 then: 56 properties: 57 "#clock-cells": 58 const: 0 59 60 clocks: 61 maxItems: 1 62 63 clock-output-names: 64 maxItems: 1 65 66 required: 67 - "#clock-cells" 68 - clocks 69 - clock-output-names 70 71 - if: 72 properties: 73 compatible: 74 contains: 75 const: allwinner,sun8i-a23-apb0-gates-clk 76 77 then: 78 properties: 79 "#clock-cells": 80 const: 1 81 description: > 82 This additional argument passed to that clock is the 83 offset of the bit controlling this particular gate in 84 the register. 85 86 clocks: 87 maxItems: 1 88 89 clock-output-names: 90 minItems: 1 91 maxItems: 32 92 93 required: 94 - "#clock-cells" 95 - clocks 96 - clock-output-names 97 98 - if: 99 properties: 100 compatible: 101 contains: 102 const: allwinner,sun6i-a31-clock-reset 103 104 then: 105 properties: 106 "#reset-cells": 107 const: 1 108 109 required: 110 - "#reset-cells" 111 112required: 113 - compatible 114 - reg 115 116additionalProperties: false 117 118examples: 119 - | 120 prcm@1f01400 { 121 compatible = "allwinner,sun8i-a23-prcm"; 122 reg = <0x01f01400 0x200>; 123 124 ar100: ar100_clk { 125 compatible = "fixed-factor-clock"; 126 #clock-cells = <0>; 127 clock-div = <1>; 128 clock-mult = <1>; 129 clocks = <&osc24M>; 130 clock-output-names = "ar100"; 131 }; 132 133 ahb0: ahb0_clk { 134 compatible = "fixed-factor-clock"; 135 #clock-cells = <0>; 136 clock-div = <1>; 137 clock-mult = <1>; 138 clocks = <&ar100>; 139 clock-output-names = "ahb0"; 140 }; 141 142 apb0: apb0_clk { 143 compatible = "allwinner,sun8i-a23-apb0-clk"; 144 #clock-cells = <0>; 145 clocks = <&ahb0>; 146 clock-output-names = "apb0"; 147 }; 148 149 apb0_gates: apb0_gates_clk { 150 compatible = "allwinner,sun8i-a23-apb0-gates-clk"; 151 #clock-cells = <1>; 152 clocks = <&apb0>; 153 clock-output-names = "apb0_pio", "apb0_timer", 154 "apb0_rsb", "apb0_uart", 155 "apb0_i2c"; 156 }; 157 158 apb0_rst: apb0_rst { 159 compatible = "allwinner,sun6i-a31-clock-reset"; 160 #reset-cells = <1>; 161 }; 162 163 codec_analog: codec-analog { 164 compatible = "allwinner,sun8i-a23-codec-analog"; 165 }; 166 }; 167 168... 169