1MediaTek sysirq
2
3MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
4interrupt.
5
6Required properties:
7- compatible: should be
8	"mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
9	"mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
10	"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
11	"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
12	"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
13	"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
14	"mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
15	"mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
16	"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
17	"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
18	"mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq": for MT6779
19	"mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
20	"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
21	"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
22	"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
23	"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
24	"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
25	"mediatek,mt6577-sysirq": for MT6577
26	"mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
27	"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
28	"mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365
29- interrupt-controller : Identifies the node as an interrupt controller
30- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
31- reg: Physical base address of the intpol registers and length of memory
32  mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
33  need 1.
34
35Example:
36	sysirq: intpol-controller@10200620 {
37		compatible = "mediatek,mt6797-sysirq",
38			     "mediatek,mt6577-sysirq";
39		interrupt-controller;
40		#interrupt-cells = <3>;
41		interrupt-parent = <&gic>;
42		reg = <0 0x10220620 0 0x20>,
43		      <0 0x10220690 0 0x10>;
44	};
45