1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8550 Display MDSS
8
9maintainers:
10  - Neil Armstrong <neil.armstrong@linaro.org>
11
12description:
13  SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8550-mdss
21
22  clocks:
23    items:
24      - description: Display MDSS AHB
25      - description: Display AHB
26      - description: Display hf AXI
27      - description: Display core
28
29  iommus:
30    maxItems: 1
31
32  interconnects:
33    maxItems: 2
34
35  interconnect-names:
36    maxItems: 2
37
38patternProperties:
39  "^display-controller@[0-9a-f]+$":
40    type: object
41    properties:
42      compatible:
43        const: qcom,sm8550-dpu
44
45  "^displayport-controller@[0-9a-f]+$":
46    type: object
47    properties:
48      compatible:
49        items:
50          - const: qcom,sm8550-dp
51          - const: qcom,sm8350-dp
52
53  "^dsi@[0-9a-f]+$":
54    type: object
55    properties:
56      compatible:
57        items:
58          - const: qcom,sm8550-dsi-ctrl
59          - const: qcom,mdss-dsi-ctrl
60
61  "^phy@[0-9a-f]+$":
62    type: object
63    properties:
64      compatible:
65        const: qcom,sm8550-dsi-phy-4nm
66
67required:
68  - compatible
69
70unevaluatedProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
75    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
76    #include <dt-bindings/clock/qcom,rpmh.h>
77    #include <dt-bindings/interrupt-controller/arm-gic.h>
78    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
79    #include <dt-bindings/power/qcom,rpmhpd.h>
80
81    display-subsystem@ae00000 {
82        compatible = "qcom,sm8550-mdss";
83        reg = <0x0ae00000 0x1000>;
84        reg-names = "mdss";
85
86        interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
87                        <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
88        interconnect-names = "mdp0-mem", "mdp1-mem";
89
90        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
91
92        power-domains = <&dispcc MDSS_GDSC>;
93
94        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
95                 <&gcc GCC_DISP_AHB_CLK>,
96                 <&gcc GCC_DISP_HF_AXI_CLK>,
97                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
98        clock-names = "iface", "bus", "nrt_bus", "core";
99
100        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
101        interrupt-controller;
102        #interrupt-cells = <1>;
103
104        iommus = <&apps_smmu 0x1c00 0x2>;
105
106        #address-cells = <1>;
107        #size-cells = <1>;
108        ranges;
109
110        display-controller@ae01000 {
111            compatible = "qcom,sm8550-dpu";
112            reg = <0x0ae01000 0x8f000>,
113                  <0x0aeb0000 0x2008>;
114            reg-names = "mdp", "vbif";
115
116            clocks = <&gcc GCC_DISP_AHB_CLK>,
117                    <&gcc GCC_DISP_HF_AXI_CLK>,
118                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
119                    <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
120                    <&dispcc DISP_CC_MDSS_MDP_CLK>,
121                    <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
122            clock-names = "bus",
123                          "nrt_bus",
124                          "iface",
125                          "lut",
126                          "core",
127                          "vsync";
128
129            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
130            assigned-clock-rates = <19200000>;
131
132            operating-points-v2 = <&mdp_opp_table>;
133            power-domains = <&rpmhpd RPMHPD_MMCX>;
134
135            interrupt-parent = <&mdss>;
136            interrupts = <0>;
137
138            ports {
139                #address-cells = <1>;
140                #size-cells = <0>;
141
142                port@0 {
143                    reg = <0>;
144                    dpu_intf1_out: endpoint {
145                        remote-endpoint = <&dsi0_in>;
146                    };
147                };
148
149                port@1 {
150                    reg = <1>;
151                    dpu_intf2_out: endpoint {
152                        remote-endpoint = <&dsi1_in>;
153                    };
154                };
155            };
156
157            mdp_opp_table: opp-table {
158                compatible = "operating-points-v2";
159
160                opp-200000000 {
161                    opp-hz = /bits/ 64 <200000000>;
162                    required-opps = <&rpmhpd_opp_low_svs>;
163                };
164
165                opp-325000000 {
166                    opp-hz = /bits/ 64 <325000000>;
167                    required-opps = <&rpmhpd_opp_svs>;
168                };
169
170                opp-375000000 {
171                    opp-hz = /bits/ 64 <375000000>;
172                    required-opps = <&rpmhpd_opp_svs_l1>;
173                };
174
175                opp-514000000 {
176                    opp-hz = /bits/ 64 <514000000>;
177                    required-opps = <&rpmhpd_opp_nom>;
178                };
179            };
180        };
181
182        dsi@ae94000 {
183            compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
184            reg = <0x0ae94000 0x400>;
185            reg-names = "dsi_ctrl";
186
187            interrupt-parent = <&mdss>;
188            interrupts = <4>;
189
190            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
191                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
192                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
193                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
194                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
195                     <&gcc GCC_DISP_HF_AXI_CLK>;
196            clock-names = "byte",
197                          "byte_intf",
198                          "pixel",
199                          "core",
200                          "iface",
201                          "bus";
202
203            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
204                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
205            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
206
207            operating-points-v2 = <&dsi_opp_table>;
208            power-domains = <&rpmhpd RPMHPD_MMCX>;
209
210            phys = <&dsi0_phy>;
211            phy-names = "dsi";
212
213            #address-cells = <1>;
214            #size-cells = <0>;
215
216            ports {
217                #address-cells = <1>;
218                #size-cells = <0>;
219
220                port@0 {
221                    reg = <0>;
222                    dsi0_in: endpoint {
223                        remote-endpoint = <&dpu_intf1_out>;
224                    };
225                };
226
227                port@1 {
228                    reg = <1>;
229                    dsi0_out: endpoint {
230                    };
231                };
232            };
233
234            dsi_opp_table: opp-table {
235                compatible = "operating-points-v2";
236
237                opp-187500000 {
238                    opp-hz = /bits/ 64 <187500000>;
239                    required-opps = <&rpmhpd_opp_low_svs>;
240                };
241
242                opp-300000000 {
243                    opp-hz = /bits/ 64 <300000000>;
244                    required-opps = <&rpmhpd_opp_svs>;
245                };
246
247                opp-358000000 {
248                    opp-hz = /bits/ 64 <358000000>;
249                    required-opps = <&rpmhpd_opp_svs_l1>;
250                };
251            };
252        };
253
254        dsi0_phy: phy@ae94400 {
255            compatible = "qcom,sm8550-dsi-phy-4nm";
256            reg = <0x0ae95000 0x200>,
257                  <0x0ae95200 0x280>,
258                  <0x0ae95500 0x400>;
259            reg-names = "dsi_phy",
260                        "dsi_phy_lane",
261                        "dsi_pll";
262
263            #clock-cells = <1>;
264            #phy-cells = <0>;
265
266            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
267                     <&rpmhcc RPMH_CXO_CLK>;
268            clock-names = "iface", "ref";
269        };
270
271        dsi@ae96000 {
272            compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
273            reg = <0x0ae96000 0x400>;
274            reg-names = "dsi_ctrl";
275
276            interrupt-parent = <&mdss>;
277            interrupts = <5>;
278
279            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
280                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
281                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
282                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
283                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
284                     <&gcc GCC_DISP_HF_AXI_CLK>;
285            clock-names = "byte",
286                          "byte_intf",
287                          "pixel",
288                          "core",
289                          "iface",
290                          "bus";
291
292            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
293                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
294            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
295
296            operating-points-v2 = <&dsi_opp_table>;
297            power-domains = <&rpmhpd RPMHPD_MMCX>;
298
299            phys = <&dsi1_phy>;
300            phy-names = "dsi";
301
302            #address-cells = <1>;
303            #size-cells = <0>;
304
305            ports {
306                #address-cells = <1>;
307                #size-cells = <0>;
308
309                port@0 {
310                    reg = <0>;
311                    dsi1_in: endpoint {
312                        remote-endpoint = <&dpu_intf2_out>;
313                    };
314                };
315
316                port@1 {
317                    reg = <1>;
318                    dsi1_out: endpoint {
319                    };
320                };
321            };
322        };
323
324        dsi1_phy: phy@ae96400 {
325            compatible = "qcom,sm8550-dsi-phy-4nm";
326            reg = <0x0ae97000 0x200>,
327                  <0x0ae97200 0x280>,
328                  <0x0ae97500 0x400>;
329            reg-names = "dsi_phy",
330                        "dsi_phy_lane",
331                        "dsi_pll";
332
333            #clock-cells = <1>;
334            #phy-cells = <0>;
335
336            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
337                     <&rpmhcc RPMH_CXO_CLK>;
338            clock-names = "iface", "ref";
339        };
340    };
341...
342