1[
2    {
3        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3",
6        "CounterMask": "6",
7        "EventCode": "0xa3",
8        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
9        "PEBScounters": "0,1,2,3",
10        "SampleAfterValue": "1000003",
11        "UMask": "0x6"
12    },
13    {
14        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
15        "CollectPEBSRecord": "2",
16        "Counter": "0,1,2,3,4,5,6,7",
17        "EventCode": "0xc3",
18        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
19        "PEBScounters": "0,1,2,3,4,5,6,7",
20        "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
21        "SampleAfterValue": "100003",
22        "UMask": "0x2"
23    },
24    {
25        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
26        "CollectPEBSRecord": "2",
27        "Counter": "0,1,2,3,4,5,6,7",
28        "Data_LA": "1",
29        "EventCode": "0xcd",
30        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
31        "MSRIndex": "0x3F6",
32        "MSRValue": "0x80",
33        "PEBS": "2",
34        "PEBScounters": "0,1,2,3,4,5,6,7",
35        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
36        "SampleAfterValue": "1009",
37        "TakenAlone": "1",
38        "UMask": "0x1"
39    },
40    {
41        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
42        "CollectPEBSRecord": "2",
43        "Counter": "0,1,2,3,4,5,6,7",
44        "Data_LA": "1",
45        "EventCode": "0xcd",
46        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
47        "MSRIndex": "0x3F6",
48        "MSRValue": "0x10",
49        "PEBS": "2",
50        "PEBScounters": "0,1,2,3,4,5,6,7",
51        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
52        "SampleAfterValue": "20011",
53        "TakenAlone": "1",
54        "UMask": "0x1"
55    },
56    {
57        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
58        "CollectPEBSRecord": "2",
59        "Counter": "0,1,2,3,4,5,6,7",
60        "Data_LA": "1",
61        "EventCode": "0xcd",
62        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
63        "MSRIndex": "0x3F6",
64        "MSRValue": "0x100",
65        "PEBS": "2",
66        "PEBScounters": "0,1,2,3,4,5,6,7",
67        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
68        "SampleAfterValue": "503",
69        "TakenAlone": "1",
70        "UMask": "0x1"
71    },
72    {
73        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
74        "CollectPEBSRecord": "2",
75        "Counter": "0,1,2,3,4,5,6,7",
76        "Data_LA": "1",
77        "EventCode": "0xcd",
78        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
79        "MSRIndex": "0x3F6",
80        "MSRValue": "0x20",
81        "PEBS": "2",
82        "PEBScounters": "0,1,2,3,4,5,6,7",
83        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
84        "SampleAfterValue": "100007",
85        "TakenAlone": "1",
86        "UMask": "0x1"
87    },
88    {
89        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
90        "CollectPEBSRecord": "2",
91        "Counter": "0,1,2,3,4,5,6,7",
92        "Data_LA": "1",
93        "EventCode": "0xcd",
94        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
95        "MSRIndex": "0x3F6",
96        "MSRValue": "0x4",
97        "PEBS": "2",
98        "PEBScounters": "0,1,2,3,4,5,6,7",
99        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
100        "SampleAfterValue": "100003",
101        "TakenAlone": "1",
102        "UMask": "0x1"
103    },
104    {
105        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
106        "CollectPEBSRecord": "2",
107        "Counter": "0,1,2,3,4,5,6,7",
108        "Data_LA": "1",
109        "EventCode": "0xcd",
110        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
111        "MSRIndex": "0x3F6",
112        "MSRValue": "0x200",
113        "PEBS": "2",
114        "PEBScounters": "0,1,2,3,4,5,6,7",
115        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
116        "SampleAfterValue": "101",
117        "TakenAlone": "1",
118        "UMask": "0x1"
119    },
120    {
121        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
122        "CollectPEBSRecord": "2",
123        "Counter": "0,1,2,3,4,5,6,7",
124        "Data_LA": "1",
125        "EventCode": "0xcd",
126        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
127        "MSRIndex": "0x3F6",
128        "MSRValue": "0x40",
129        "PEBS": "2",
130        "PEBScounters": "0,1,2,3,4,5,6,7",
131        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
132        "SampleAfterValue": "2003",
133        "TakenAlone": "1",
134        "UMask": "0x1"
135    },
136    {
137        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
138        "CollectPEBSRecord": "2",
139        "Counter": "0,1,2,3,4,5,6,7",
140        "Data_LA": "1",
141        "EventCode": "0xcd",
142        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
143        "MSRIndex": "0x3F6",
144        "MSRValue": "0x8",
145        "PEBS": "2",
146        "PEBScounters": "0,1,2,3,4,5,6,7",
147        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
148        "SampleAfterValue": "50021",
149        "TakenAlone": "1",
150        "UMask": "0x1"
151    },
152    {
153        "BriefDescription": "Demand Data Read requests who miss L3 cache",
154        "CollectPEBSRecord": "2",
155        "Counter": "0,1,2,3",
156        "EventCode": "0xb0",
157        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
158        "PEBScounters": "0,1,2,3",
159        "PublicDescription": "Demand Data Read requests who miss L3 cache.",
160        "SampleAfterValue": "100003",
161        "UMask": "0x10"
162    },
163    {
164        "BriefDescription": "Number of times an RTM execution aborted.",
165        "CollectPEBSRecord": "2",
166        "Counter": "0,1,2,3,4,5,6,7",
167        "EventCode": "0xc9",
168        "EventName": "RTM_RETIRED.ABORTED",
169        "PEBScounters": "0,1,2,3,4,5,6,7",
170        "PublicDescription": "Counts the number of times RTM abort was triggered.",
171        "SampleAfterValue": "100003",
172        "UMask": "0x4"
173    },
174    {
175        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
176        "CollectPEBSRecord": "2",
177        "Counter": "0,1,2,3,4,5,6,7",
178        "EventCode": "0xc9",
179        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
180        "PEBScounters": "0,1,2,3,4,5,6,7",
181        "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
182        "SampleAfterValue": "100003",
183        "UMask": "0x80"
184    },
185    {
186        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
187        "CollectPEBSRecord": "2",
188        "Counter": "0,1,2,3,4,5,6,7",
189        "EventCode": "0xc9",
190        "EventName": "RTM_RETIRED.ABORTED_MEM",
191        "PEBScounters": "0,1,2,3,4,5,6,7",
192        "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
193        "SampleAfterValue": "100003",
194        "UMask": "0x8"
195    },
196    {
197        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
198        "CollectPEBSRecord": "2",
199        "Counter": "0,1,2,3,4,5,6,7",
200        "EventCode": "0xc9",
201        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
202        "PEBScounters": "0,1,2,3,4,5,6,7",
203        "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
204        "SampleAfterValue": "100003",
205        "UMask": "0x40"
206    },
207    {
208        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
209        "CollectPEBSRecord": "2",
210        "Counter": "0,1,2,3,4,5,6,7",
211        "EventCode": "0xc9",
212        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
213        "PEBScounters": "0,1,2,3,4,5,6,7",
214        "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
215        "SampleAfterValue": "100003",
216        "UMask": "0x20"
217    },
218    {
219        "BriefDescription": "Number of times an RTM execution successfully committed",
220        "CollectPEBSRecord": "2",
221        "Counter": "0,1,2,3,4,5,6,7",
222        "EventCode": "0xc9",
223        "EventName": "RTM_RETIRED.COMMIT",
224        "PEBScounters": "0,1,2,3,4,5,6,7",
225        "PublicDescription": "Counts the number of times RTM commit succeeded.",
226        "SampleAfterValue": "100003",
227        "UMask": "0x2"
228    },
229    {
230        "BriefDescription": "Number of times an RTM execution started.",
231        "CollectPEBSRecord": "2",
232        "Counter": "0,1,2,3,4,5,6,7",
233        "EventCode": "0xc9",
234        "EventName": "RTM_RETIRED.START",
235        "PEBScounters": "0,1,2,3,4,5,6,7",
236        "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
237        "SampleAfterValue": "100003",
238        "UMask": "0x1"
239    },
240    {
241        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
242        "CollectPEBSRecord": "2",
243        "Counter": "0,1,2,3,4,5,6,7",
244        "EventCode": "0x5d",
245        "EventName": "TX_EXEC.MISC2",
246        "PEBScounters": "0,1,2,3,4,5,6,7",
247        "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
248        "SampleAfterValue": "100003",
249        "UMask": "0x2"
250    },
251    {
252        "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
253        "CollectPEBSRecord": "2",
254        "Counter": "0,1,2,3,4,5,6,7",
255        "EventCode": "0x5d",
256        "EventName": "TX_EXEC.MISC3",
257        "PEBScounters": "0,1,2,3,4,5,6,7",
258        "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
259        "SampleAfterValue": "100003",
260        "UMask": "0x4"
261    },
262    {
263        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
264        "CollectPEBSRecord": "2",
265        "Counter": "0,1,2,3",
266        "EventCode": "0x54",
267        "EventName": "TX_MEM.ABORT_CAPACITY_READ",
268        "PEBScounters": "0,1,2,3",
269        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
270        "SampleAfterValue": "100003",
271        "UMask": "0x80"
272    },
273    {
274        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
275        "CollectPEBSRecord": "2",
276        "Counter": "0,1,2,3",
277        "EventCode": "0x54",
278        "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
279        "PEBScounters": "0,1,2,3",
280        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
281        "SampleAfterValue": "100003",
282        "UMask": "0x2"
283    },
284    {
285        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
286        "CollectPEBSRecord": "2",
287        "Counter": "0,1,2,3",
288        "EventCode": "0x54",
289        "EventName": "TX_MEM.ABORT_CONFLICT",
290        "PEBScounters": "0,1,2,3",
291        "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
292        "SampleAfterValue": "100003",
293        "UMask": "0x1"
294    }
295]
296