1[
2    {
3        "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
4        "Counter": "0,1",
5        "EventCode": "0x84",
6        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
7        "PerPkg": "1",
8        "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
9        "UMask": "0x01",
10        "Unit": "ARB"
11    },
12    {
13        "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
14        "EventCode": "0x80",
15        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
16        "PerPkg": "1",
17        "PublicDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
18        "UMask": "0x01",
19        "Unit": "ARB"
20    },
21    {
22        "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
23        "CounterMask": "1",
24        "EventCode": "0x80",
25        "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
26        "PerPkg": "1",
27        "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
28        "UMask": "0x01",
29        "Unit": "ARB"
30    },
31    {
32        "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
33        "EventCode": "0x80",
34        "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
35        "PerPkg": "1",
36        "PublicDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
37        "UMask": "0x02",
38        "Unit": "ARB"
39    },
40    {
41        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
42        "Counter": "0,1",
43        "EventCode": "0x81",
44        "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
45        "PerPkg": "1",
46        "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
47        "UMask": "0x02",
48        "Unit": "ARB"
49    },
50    {
51        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
52        "Counter": "0,1",
53        "EventCode": "0x81",
54        "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
55        "PerPkg": "1",
56        "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
57        "UMask": "0x02",
58        "Unit": "ARB"
59    },
60    {
61        "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
62        "Counter": "0,1",
63        "EventCode": "0x81",
64        "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
65        "PerPkg": "1",
66        "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
67        "UMask": "0x20",
68        "Unit": "ARB"
69    },
70    {
71        "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
72        "Counter": "FIXED",
73        "EventCode": "0xff",
74        "EventName": "UNC_CLOCK.SOCKET",
75        "PerPkg": "1",
76        "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
77        "Unit": "CLOCK"
78    }
79]
80