1[ 2 { 3 "BriefDescription": "IMC Clockticks at DCLK frequency", 4 "Counter": "0,1,2,3", 5 "CounterType": "PGMABLE", 6 "EventCode": "0x01", 7 "EventName": "UNC_M_CLOCKTICKS", 8 "PerPkg": "1", 9 "UMask": "0x0000000001", 10 "UMaskExt": "0x00000000", 11 "Unit": "iMC" 12 }, 13 { 14 "BriefDescription": "IMC Clockticks at HCLK frequency", 15 "Counter": "0,1,2,3", 16 "CounterType": "PGMABLE", 17 "EventCode": "0x01", 18 "EventName": "UNC_M_HCLOCKTICKS", 19 "PerPkg": "1", 20 "Unit": "iMC" 21 }, 22 { 23 "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)", 24 "Counter": "0,1,2,3", 25 "CounterType": "PGMABLE", 26 "EventCode": "0x05", 27 "EventName": "UNC_M_CAS_COUNT.RD_REG", 28 "PerPkg": "1", 29 "UMask": "0x00000000c1", 30 "UMaskExt": "0x00000000", 31 "Unit": "iMC" 32 }, 33 { 34 "BriefDescription": "DRAM underfill read CAS commands issued", 35 "Counter": "0,1,2,3", 36 "CounterType": "PGMABLE", 37 "EventCode": "0x05", 38 "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", 39 "PerPkg": "1", 40 "UMask": "0x00000000c4", 41 "UMaskExt": "0x00000000", 42 "Unit": "iMC" 43 }, 44 { 45 "BriefDescription": "All DRAM read CAS commands issued (including underfills)", 46 "Counter": "0,1,2,3", 47 "CounterType": "PGMABLE", 48 "EventCode": "0x05", 49 "EventName": "UNC_M_CAS_COUNT.RD", 50 "PerPkg": "1", 51 "UMask": "0x00000000cf", 52 "UMaskExt": "0x00000000", 53 "Unit": "iMC" 54 }, 55 { 56 "BriefDescription": "All DRAM write CAS commands issued", 57 "Counter": "0,1,2,3", 58 "CounterType": "PGMABLE", 59 "EventCode": "0x05", 60 "EventName": "UNC_M_CAS_COUNT.WR", 61 "PerPkg": "1", 62 "UMask": "0x00000000f0", 63 "UMaskExt": "0x00000000", 64 "Unit": "iMC" 65 }, 66 { 67 "BriefDescription": "Read Pending Queue Allocations", 68 "Counter": "0,1,2,3", 69 "CounterType": "PGMABLE", 70 "EventCode": "0x10", 71 "EventName": "UNC_M_RPQ_INSERTS.PCH0", 72 "PerPkg": "1", 73 "UMask": "0x0000000001", 74 "UMaskExt": "0x00000000", 75 "Unit": "iMC" 76 }, 77 { 78 "BriefDescription": "Read Pending Queue Allocations", 79 "Counter": "0,1,2,3", 80 "CounterType": "PGMABLE", 81 "EventCode": "0x10", 82 "EventName": "UNC_M_RPQ_INSERTS.PCH1", 83 "PerPkg": "1", 84 "UMask": "0x0000000002", 85 "UMaskExt": "0x00000000", 86 "Unit": "iMC" 87 }, 88 { 89 "BriefDescription": "Write Pending Queue Allocations", 90 "Counter": "0,1,2,3", 91 "CounterType": "PGMABLE", 92 "EventCode": "0x20", 93 "EventName": "UNC_M_WPQ_INSERTS.PCH0", 94 "PerPkg": "1", 95 "UMask": "0x0000000001", 96 "UMaskExt": "0x00000000", 97 "Unit": "iMC" 98 }, 99 { 100 "BriefDescription": "Write Pending Queue Allocations", 101 "Counter": "0,1,2,3", 102 "CounterType": "PGMABLE", 103 "EventCode": "0x20", 104 "EventName": "UNC_M_WPQ_INSERTS.PCH1", 105 "PerPkg": "1", 106 "UMask": "0x0000000002", 107 "UMaskExt": "0x00000000", 108 "Unit": "iMC" 109 }, 110 { 111 "BriefDescription": "Read Pending Queue Occupancy", 112 "Counter": "0,1,2,3", 113 "CounterType": "PGMABLE", 114 "EventCode": "0x80", 115 "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", 116 "PerPkg": "1", 117 "UMaskExt": "0x00000000", 118 "Unit": "iMC" 119 }, 120 { 121 "BriefDescription": "Read Pending Queue Occupancy", 122 "Counter": "0,1,2,3", 123 "CounterType": "PGMABLE", 124 "EventCode": "0x81", 125 "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", 126 "PerPkg": "1", 127 "UMaskExt": "0x00000000", 128 "Unit": "iMC" 129 }, 130 { 131 "BriefDescription": "Write Pending Queue Occupancy", 132 "Counter": "0,1,2,3", 133 "CounterType": "PGMABLE", 134 "EventCode": "0x82", 135 "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", 136 "PerPkg": "1", 137 "UMaskExt": "0x00000000", 138 "Unit": "iMC" 139 }, 140 { 141 "BriefDescription": "Write Pending Queue Occupancy", 142 "Counter": "0,1,2,3", 143 "CounterType": "PGMABLE", 144 "EventCode": "0x83", 145 "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", 146 "PerPkg": "1", 147 "UMaskExt": "0x00000000", 148 "Unit": "iMC" 149 }, 150 { 151 "BriefDescription": "PMM Read Pending Queue occupancy", 152 "Counter": "0,1,2,3", 153 "CounterType": "PGMABLE", 154 "EventCode": "0xe0", 155 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0", 156 "PerPkg": "1", 157 "UMask": "0x0000000001", 158 "UMaskExt": "0x00000000", 159 "Unit": "iMC" 160 }, 161 { 162 "BriefDescription": "PMM Read Pending Queue occupancy", 163 "Counter": "0,1,2,3", 164 "CounterType": "PGMABLE", 165 "EventCode": "0xe0", 166 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1", 167 "PerPkg": "1", 168 "UMask": "0x0000000002", 169 "UMaskExt": "0x00000000", 170 "Unit": "iMC" 171 }, 172 { 173 "BriefDescription": "PMM Read Pending Queue inserts", 174 "Counter": "0,1,2,3", 175 "CounterType": "PGMABLE", 176 "EventCode": "0xe3", 177 "EventName": "UNC_M_PMM_RPQ_INSERTS", 178 "PerPkg": "1", 179 "UMaskExt": "0x00000000", 180 "Unit": "iMC" 181 }, 182 { 183 "BriefDescription": "PMM Write Pending Queue Occupancy", 184 "Counter": "0,1,2,3", 185 "CounterType": "PGMABLE", 186 "EventCode": "0xe4", 187 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", 188 "PerPkg": "1", 189 "UMask": "0x03", 190 "Unit": "iMC" 191 }, 192 { 193 "BriefDescription": "PMM Write Pending Queue inserts", 194 "Counter": "0,1,2,3", 195 "CounterType": "PGMABLE", 196 "EventCode": "0xe7", 197 "EventName": "UNC_M_PMM_WPQ_INSERTS", 198 "PerPkg": "1", 199 "UMaskExt": "0x00000000", 200 "Unit": "iMC" 201 }, 202 { 203 "BriefDescription": "PMM Write Pending Queue Occupancy", 204 "Counter": "0,1,2,3", 205 "CounterType": "PGMABLE", 206 "EventCode": "0xE4", 207 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0", 208 "PerPkg": "1", 209 "UMask": "0x0000000001", 210 "UMaskExt": "0x00000000", 211 "Unit": "iMC" 212 }, 213 { 214 "BriefDescription": "PMM Write Pending Queue Occupancy", 215 "Counter": "0,1,2,3", 216 "CounterType": "PGMABLE", 217 "EventCode": "0xE4", 218 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1", 219 "PerPkg": "1", 220 "UMask": "0x0000000002", 221 "UMaskExt": "0x00000000", 222 "Unit": "iMC" 223 }, 224 { 225 "BriefDescription": "Activate due to read, write, underfill, or bypass", 226 "Counter": "0,1,2,3", 227 "CounterType": "PGMABLE", 228 "EventCode": "0x02", 229 "EventName": "UNC_M_ACT_COUNT.ALL", 230 "PerPkg": "1", 231 "UMask": "0x00000000ff", 232 "UMaskExt": "0x00000000", 233 "Unit": "iMC" 234 }, 235 { 236 "BriefDescription": "Precharge due to read on page miss", 237 "Counter": "0,1,2,3", 238 "CounterType": "PGMABLE", 239 "EventCode": "0x03", 240 "EventName": "UNC_M_PRE_COUNT.RD", 241 "PerPkg": "1", 242 "UMask": "0x0000000011", 243 "UMaskExt": "0x00000000", 244 "Unit": "iMC" 245 }, 246 { 247 "BriefDescription": "Precharge due to write on page miss", 248 "Counter": "0,1,2,3", 249 "CounterType": "PGMABLE", 250 "EventCode": "0x03", 251 "EventName": "UNC_M_PRE_COUNT.WR", 252 "PerPkg": "1", 253 "UMask": "0x0000000022", 254 "UMaskExt": "0x00000000", 255 "Unit": "iMC" 256 }, 257 { 258 "BriefDescription": "DRAM Precharge commands. : Precharge due to (?)", 259 "Counter": "0,1,2,3", 260 "CounterType": "PGMABLE", 261 "EventCode": "0x03", 262 "EventName": "UNC_M_PRE_COUNT.PGT", 263 "PerPkg": "1", 264 "UMask": "0x0000000088", 265 "UMaskExt": "0x00000000", 266 "Unit": "iMC" 267 }, 268 { 269 "BriefDescription": "Precharge due to read, write, underfill, or PGT", 270 "Counter": "0,1,2,3", 271 "CounterType": "PGMABLE", 272 "EventCode": "0x03", 273 "EventName": "UNC_M_PRE_COUNT.ALL", 274 "PerPkg": "1", 275 "UMask": "0x00000000ff", 276 "UMaskExt": "0x00000000", 277 "Unit": "iMC" 278 }, 279 { 280 "BriefDescription": "All DRAM CAS commands issued", 281 "Counter": "0,1,2,3", 282 "CounterType": "PGMABLE", 283 "EventCode": "0x05", 284 "EventName": "UNC_M_CAS_COUNT.ALL", 285 "PerPkg": "1", 286 "UMask": "0x00000000ff", 287 "UMaskExt": "0x00000000", 288 "Unit": "iMC" 289 }, 290 { 291 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands", 292 "Counter": "0,1,2,3", 293 "CounterType": "PGMABLE", 294 "EventCode": "0x05", 295 "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", 296 "PerPkg": "1", 297 "UMask": "0x00000000c2", 298 "UMaskExt": "0x00000000", 299 "Unit": "iMC" 300 }, 301 { 302 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands", 303 "Counter": "0,1,2,3", 304 "CounterType": "PGMABLE", 305 "EventCode": "0x05", 306 "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", 307 "PerPkg": "1", 308 "UMask": "0x00000000c8", 309 "UMaskExt": "0x00000000", 310 "Unit": "iMC" 311 }, 312 { 313 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands", 314 "Counter": "0,1,2,3", 315 "CounterType": "PGMABLE", 316 "EventCode": "0x05", 317 "EventName": "UNC_M_CAS_COUNT.WR_PRE", 318 "PerPkg": "1", 319 "UMask": "0x00000000e0", 320 "UMaskExt": "0x00000000", 321 "Unit": "iMC" 322 }, 323 { 324 "BriefDescription": "PMM Read Pending Queue Occupancy", 325 "Counter": "0,1,2,3", 326 "CounterType": "PGMABLE", 327 "EventCode": "0xe0", 328 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0", 329 "PerPkg": "1", 330 "UMask": "0x0000000004", 331 "UMaskExt": "0x00000000", 332 "Unit": "iMC" 333 }, 334 { 335 "BriefDescription": "PMM Read Pending Queue Occupancy", 336 "Counter": "0,1,2,3", 337 "CounterType": "PGMABLE", 338 "EventCode": "0xe0", 339 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1", 340 "PerPkg": "1", 341 "UMask": "0x0000000008", 342 "UMaskExt": "0x00000000", 343 "Unit": "iMC" 344 }, 345 { 346 "BriefDescription": "DRAM Precharge commands. : Precharge due to read", 347 "Counter": "0,1,2,3", 348 "CounterType": "PGMABLE", 349 "EventCode": "0x03", 350 "EventName": "UNC_M_PRE_COUNT.RD_PCH0", 351 "PerPkg": "1", 352 "UMask": "0x0000000001", 353 "UMaskExt": "0x00000000", 354 "Unit": "iMC" 355 }, 356 { 357 "BriefDescription": "DRAM Precharge commands. : Precharge due to write", 358 "Counter": "0,1,2,3", 359 "CounterType": "PGMABLE", 360 "EventCode": "0x03", 361 "EventName": "UNC_M_PRE_COUNT.WR_PCH0", 362 "PerPkg": "1", 363 "UMask": "0x0000000002", 364 "UMaskExt": "0x00000000", 365 "Unit": "iMC" 366 }, 367 { 368 "BriefDescription": "DRAM Precharge commands", 369 "Counter": "0,1,2,3", 370 "CounterType": "PGMABLE", 371 "EventCode": "0x03", 372 "EventName": "UNC_M_PRE_COUNT.UFILL_PCH0", 373 "PerPkg": "1", 374 "UMask": "0x0000000004", 375 "UMaskExt": "0x00000000", 376 "Unit": "iMC" 377 }, 378 { 379 "BriefDescription": "DRAM Precharge commands. : Prechages from Page Table", 380 "Counter": "0,1,2,3", 381 "CounterType": "PGMABLE", 382 "EventCode": "0x03", 383 "EventName": "UNC_M_PRE_COUNT.PGT_PCH0", 384 "PerPkg": "1", 385 "UMask": "0x0000000008", 386 "UMaskExt": "0x00000000", 387 "Unit": "iMC" 388 }, 389 { 390 "BriefDescription": "DRAM Precharge commands", 391 "Counter": "0,1,2,3", 392 "CounterType": "PGMABLE", 393 "EventCode": "0x03", 394 "EventName": "UNC_M_PRE_COUNT.RD_PCH1", 395 "PerPkg": "1", 396 "UMask": "0x0000000010", 397 "UMaskExt": "0x00000000", 398 "Unit": "iMC" 399 }, 400 { 401 "BriefDescription": "DRAM Precharge commands", 402 "Counter": "0,1,2,3", 403 "CounterType": "PGMABLE", 404 "EventCode": "0x03", 405 "EventName": "UNC_M_PRE_COUNT.WR_PCH1", 406 "PerPkg": "1", 407 "UMask": "0x0000000020", 408 "UMaskExt": "0x00000000", 409 "Unit": "iMC" 410 }, 411 { 412 "BriefDescription": "DRAM Precharge commands", 413 "Counter": "0,1,2,3", 414 "CounterType": "PGMABLE", 415 "EventCode": "0x03", 416 "EventName": "UNC_M_PRE_COUNT.UFILL_PCH1", 417 "PerPkg": "1", 418 "UMask": "0x0000000040", 419 "UMaskExt": "0x00000000", 420 "Unit": "iMC" 421 }, 422 { 423 "BriefDescription": "DRAM Precharge commands", 424 "Counter": "0,1,2,3", 425 "CounterType": "PGMABLE", 426 "EventCode": "0x03", 427 "EventName": "UNC_M_PRE_COUNT.PGT_PCH1", 428 "PerPkg": "1", 429 "UMask": "0x0000000080", 430 "UMaskExt": "0x00000000", 431 "Unit": "iMC" 432 }, 433 { 434 "BriefDescription": "DRAM Precharge commands", 435 "Counter": "0,1,2,3", 436 "CounterType": "PGMABLE", 437 "EventCode": "0x03", 438 "EventName": "UNC_M_PRE_COUNT.UFILL", 439 "PerPkg": "1", 440 "UMask": "0x0000000044", 441 "UMaskExt": "0x00000000", 442 "Unit": "iMC" 443 }, 444 { 445 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre", 446 "Counter": "0,1,2,3", 447 "CounterType": "PGMABLE", 448 "EventCode": "0x05", 449 "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", 450 "PerPkg": "1", 451 "UMask": "0x00000000D0", 452 "UMaskExt": "0x00000000", 453 "Unit": "iMC" 454 }, 455 { 456 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0", 457 "Counter": "0,1,2,3", 458 "CounterType": "PGMABLE", 459 "EventCode": "0x05", 460 "EventName": "UNC_M_CAS_COUNT.PCH0", 461 "PerPkg": "1", 462 "UMask": "0x0000000040", 463 "UMaskExt": "0x00000000", 464 "Unit": "iMC" 465 }, 466 { 467 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1", 468 "Counter": "0,1,2,3", 469 "CounterType": "PGMABLE", 470 "EventCode": "0x05", 471 "EventName": "UNC_M_CAS_COUNT.PCH1", 472 "PerPkg": "1", 473 "UMask": "0x0000000080", 474 "UMaskExt": "0x00000000", 475 "Unit": "iMC" 476 }, 477 { 478 "BriefDescription": "PMM Read Pending Queue Occupancy", 479 "Counter": "0,1,2,3", 480 "CounterType": "PGMABLE", 481 "EventCode": "0xE0", 482 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0", 483 "PerPkg": "1", 484 "UMask": "0x0000000010", 485 "UMaskExt": "0x00000000", 486 "Unit": "iMC" 487 }, 488 { 489 "BriefDescription": "PMM Read Pending Queue Occupancy", 490 "Counter": "0,1,2,3", 491 "CounterType": "PGMABLE", 492 "EventCode": "0xE0", 493 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1", 494 "PerPkg": "1", 495 "UMask": "0x0000000020", 496 "UMaskExt": "0x00000000", 497 "Unit": "iMC" 498 } 499] 500