1[
2    {
3        "BriefDescription": "Cycles code-fetch stalled due to any reason.",
4        "CollectPEBSRecord": "1",
5        "Counter": "0,1,2,3",
6        "EventCode": "0x86",
7        "EventName": "FETCH_STALL.ALL",
8        "PDIR_COUNTER": "na",
9        "PEBScounters": "0,1,2,3",
10        "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
11        "SampleAfterValue": "200003"
12    },
13    {
14        "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss is outstanding.",
15        "CollectPEBSRecord": "1",
16        "Counter": "0,1,2,3",
17        "EventCode": "0x86",
18        "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
19        "PDIR_COUNTER": "na",
20        "PEBScounters": "0,1,2,3",
21        "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
22        "SampleAfterValue": "200003",
23        "UMask": "0x1"
24    },
25    {
26        "BriefDescription": "Cycles hardware interrupts are masked",
27        "CollectPEBSRecord": "2",
28        "Counter": "0,1,2,3",
29        "EventCode": "0xCB",
30        "EventName": "HW_INTERRUPTS.MASKED",
31        "PDIR_COUNTER": "na",
32        "PEBScounters": "0,1,2,3",
33        "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
34        "SampleAfterValue": "200003",
35        "UMask": "0x2"
36    },
37    {
38        "BriefDescription": "Cycles pending interrupts are masked",
39        "CollectPEBSRecord": "2",
40        "Counter": "0,1,2,3",
41        "EventCode": "0xCB",
42        "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
43        "PDIR_COUNTER": "na",
44        "PEBScounters": "0,1,2,3",
45        "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
46        "SampleAfterValue": "200003",
47        "UMask": "0x4"
48    },
49    {
50        "BriefDescription": "Hardware interrupts received",
51        "CollectPEBSRecord": "2",
52        "Counter": "0,1,2,3",
53        "EventCode": "0xCB",
54        "EventName": "HW_INTERRUPTS.RECEIVED",
55        "PDIR_COUNTER": "na",
56        "PEBScounters": "0,1,2,3",
57        "PublicDescription": "Counts hardware interrupts received by the processor.",
58        "SampleAfterValue": "203",
59        "UMask": "0x1"
60    }
61]
62