1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
4 //
5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 //          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
7 //
8 
9 #include <linux/devcoredump.h>
10 #include <linux/slab.h>
11 #include "avs.h"
12 #include "messages.h"
13 #include "path.h"
14 #include "topology.h"
15 
apl_enable_logs(struct avs_dev * adev,enum avs_log_enable enable,u32 aging_period,u32 fifo_full_period,unsigned long resource_mask,u32 * priorities)16 static int apl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
17 			   u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
18 {
19 	struct apl_log_state_info *info;
20 	u32 size, num_cores = adev->hw_cfg.dsp_cores;
21 	int ret, i;
22 
23 	if (fls_long(resource_mask) > num_cores)
24 		return -EINVAL;
25 	size = struct_size(info, logs_core, num_cores);
26 	info = kzalloc(size, GFP_KERNEL);
27 	if (!info)
28 		return -ENOMEM;
29 
30 	info->aging_timer_period = aging_period;
31 	info->fifo_full_timer_period = fifo_full_period;
32 	info->core_mask = resource_mask;
33 	if (enable)
34 		for_each_set_bit(i, &resource_mask, num_cores) {
35 			info->logs_core[i].enable = enable;
36 			info->logs_core[i].min_priority = *priorities++;
37 		}
38 	else
39 		for_each_set_bit(i, &resource_mask, num_cores)
40 			info->logs_core[i].enable = enable;
41 
42 	ret = avs_ipc_set_enable_logs(adev, (u8 *)info, size);
43 	kfree(info);
44 	if (ret)
45 		return AVS_IPC_RET(ret);
46 
47 	return 0;
48 }
49 
apl_log_buffer_status(struct avs_dev * adev,union avs_notify_msg * msg)50 static int apl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
51 {
52 	struct apl_log_buffer_layout layout;
53 	unsigned long flags;
54 	void __iomem *addr, *buf;
55 
56 	addr = avs_log_buffer_addr(adev, msg->log.core);
57 	if (!addr)
58 		return -ENXIO;
59 
60 	memcpy_fromio(&layout, addr, sizeof(layout));
61 
62 	spin_lock_irqsave(&adev->dbg.trace_lock, flags);
63 	if (!kfifo_initialized(&adev->dbg.trace_fifo))
64 		/* consume the logs regardless of consumer presence */
65 		goto update_read_ptr;
66 
67 	buf = apl_log_payload_addr(addr);
68 
69 	if (layout.read_ptr > layout.write_ptr) {
70 		__kfifo_fromio_locked(&adev->dbg.trace_fifo, buf + layout.read_ptr,
71 				      apl_log_payload_size(adev) - layout.read_ptr,
72 				      &adev->dbg.fifo_lock);
73 		layout.read_ptr = 0;
74 	}
75 	__kfifo_fromio_locked(&adev->dbg.trace_fifo, buf + layout.read_ptr,
76 			      layout.write_ptr - layout.read_ptr, &adev->dbg.fifo_lock);
77 
78 	wake_up(&adev->dbg.trace_waitq);
79 
80 update_read_ptr:
81 	spin_unlock_irqrestore(&adev->dbg.trace_lock, flags);
82 	writel(layout.write_ptr, addr);
83 	return 0;
84 }
85 
apl_wait_log_entry(struct avs_dev * adev,u32 core,struct apl_log_buffer_layout * layout)86 static int apl_wait_log_entry(struct avs_dev *adev, u32 core, struct apl_log_buffer_layout *layout)
87 {
88 	unsigned long timeout;
89 	void __iomem *addr;
90 
91 	addr = avs_log_buffer_addr(adev, core);
92 	if (!addr)
93 		return -ENXIO;
94 
95 	timeout = jiffies + msecs_to_jiffies(10);
96 
97 	do {
98 		memcpy_fromio(layout, addr, sizeof(*layout));
99 		if (layout->read_ptr != layout->write_ptr)
100 			return 0;
101 		usleep_range(500, 1000);
102 	} while (!time_after(jiffies, timeout));
103 
104 	return -ETIMEDOUT;
105 }
106 
107 /* reads log header and tests its type */
108 #define apl_is_entry_stackdump(addr) ((readl(addr) >> 30) & 0x1)
109 
apl_coredump(struct avs_dev * adev,union avs_notify_msg * msg)110 static int apl_coredump(struct avs_dev *adev, union avs_notify_msg *msg)
111 {
112 	struct apl_log_buffer_layout layout;
113 	void __iomem *addr, *buf;
114 	size_t dump_size;
115 	u16 offset = 0;
116 	u8 *dump, *pos;
117 
118 	dump_size = AVS_FW_REGS_SIZE + msg->ext.coredump.stack_dump_size;
119 	dump = vzalloc(dump_size);
120 	if (!dump)
121 		return -ENOMEM;
122 
123 	memcpy_fromio(dump, avs_sram_addr(adev, AVS_FW_REGS_WINDOW), AVS_FW_REGS_SIZE);
124 
125 	if (!msg->ext.coredump.stack_dump_size)
126 		goto exit;
127 
128 	/* Dump the registers even if an external error prevents gathering the stack. */
129 	addr = avs_log_buffer_addr(adev, msg->ext.coredump.core_id);
130 	if (!addr)
131 		goto exit;
132 
133 	buf = apl_log_payload_addr(addr);
134 	memcpy_fromio(&layout, addr, sizeof(layout));
135 	if (!apl_is_entry_stackdump(buf + layout.read_ptr)) {
136 		/*
137 		 * DSP awaits the remaining logs to be
138 		 * gathered before dumping stack
139 		 */
140 		msg->log.core = msg->ext.coredump.core_id;
141 		avs_dsp_op(adev, log_buffer_status, msg);
142 	}
143 
144 	pos = dump + AVS_FW_REGS_SIZE;
145 	/* gather the stack */
146 	do {
147 		u32 count;
148 
149 		if (apl_wait_log_entry(adev, msg->ext.coredump.core_id, &layout))
150 			break;
151 
152 		if (layout.read_ptr > layout.write_ptr) {
153 			count = apl_log_payload_size(adev) - layout.read_ptr;
154 			memcpy_fromio(pos + offset, buf + layout.read_ptr, count);
155 			layout.read_ptr = 0;
156 			offset += count;
157 		}
158 		count = layout.write_ptr - layout.read_ptr;
159 		memcpy_fromio(pos + offset, buf + layout.read_ptr, count);
160 		offset += count;
161 
162 		/* update read pointer */
163 		writel(layout.write_ptr, addr);
164 	} while (offset < msg->ext.coredump.stack_dump_size);
165 
166 exit:
167 	dev_coredumpv(adev->dev, dump, dump_size, GFP_KERNEL);
168 
169 	return 0;
170 }
171 
apl_lp_streaming(struct avs_dev * adev)172 static bool apl_lp_streaming(struct avs_dev *adev)
173 {
174 	struct avs_path *path;
175 
176 	/* Any gateway without buffer allocated in LP area disqualifies D0IX. */
177 	list_for_each_entry(path, &adev->path_list, node) {
178 		struct avs_path_pipeline *ppl;
179 
180 		list_for_each_entry(ppl, &path->ppl_list, node) {
181 			struct avs_path_module *mod;
182 
183 			list_for_each_entry(mod, &ppl->mod_list, node) {
184 				struct avs_tplg_modcfg_ext *cfg;
185 
186 				cfg = mod->template->cfg_ext;
187 
188 				/* only copiers have gateway attributes */
189 				if (!guid_equal(&cfg->type, &AVS_COPIER_MOD_UUID))
190 					continue;
191 				/* non-gateway copiers do not prevent PG */
192 				if (cfg->copier.dma_type == INVALID_OBJECT_ID)
193 					continue;
194 
195 				if (!mod->gtw_attrs.lp_buffer_alloc)
196 					return false;
197 			}
198 		}
199 	}
200 
201 	return true;
202 }
203 
apl_d0ix_toggle(struct avs_dev * adev,struct avs_ipc_msg * tx,bool wake)204 static bool apl_d0ix_toggle(struct avs_dev *adev, struct avs_ipc_msg *tx, bool wake)
205 {
206 	/* wake in all cases */
207 	if (wake)
208 		return true;
209 
210 	/*
211 	 * If no pipelines are running, allow for d0ix schedule.
212 	 * If all gateways have lp=1, allow for d0ix schedule.
213 	 * If any gateway with lp=0 is allocated, abort scheduling d0ix.
214 	 *
215 	 * Note: for cAVS 1.5+ and 1.8, D0IX is LP-firmware transition,
216 	 * not the power-gating mechanism known from cAVS 2.0.
217 	 */
218 	return apl_lp_streaming(adev);
219 }
220 
apl_set_d0ix(struct avs_dev * adev,bool enable)221 static int apl_set_d0ix(struct avs_dev *adev, bool enable)
222 {
223 	bool streaming = false;
224 	int ret;
225 
226 	if (enable)
227 		/* Either idle or all gateways with lp=1. */
228 		streaming = !list_empty(&adev->path_list);
229 
230 	ret = avs_ipc_set_d0ix(adev, enable, streaming);
231 	return AVS_IPC_RET(ret);
232 }
233 
234 const struct avs_dsp_ops apl_dsp_ops = {
235 	.power = avs_dsp_core_power,
236 	.reset = avs_dsp_core_reset,
237 	.stall = avs_dsp_core_stall,
238 	.irq_handler = avs_dsp_irq_handler,
239 	.irq_thread = avs_dsp_irq_thread,
240 	.int_control = avs_dsp_interrupt_control,
241 	.load_basefw = avs_hda_load_basefw,
242 	.load_lib = avs_hda_load_library,
243 	.transfer_mods = avs_hda_transfer_modules,
244 	.enable_logs = apl_enable_logs,
245 	.log_buffer_offset = skl_log_buffer_offset,
246 	.log_buffer_status = apl_log_buffer_status,
247 	.coredump = apl_coredump,
248 	.d0ix_toggle = apl_d0ix_toggle,
249 	.set_d0ix = apl_set_d0ix,
250 };
251