1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * cs35l33.c -- CS35L33 ALSA SoC audio driver
4  *
5  * Copyright 2016 Cirrus Logic, Inc.
6  *
7  * Author: Paul Handrigan <paul.handrigan@cirrus.com>
8  */
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/i2c.h>
15 #include <linux/slab.h>
16 #include <linux/workqueue.h>
17 #include <linux/platform_device.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/soc-dapm.h>
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
25 #include <linux/gpio.h>
26 #include <linux/gpio/consumer.h>
27 #include <sound/cs35l33.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/regulator/machine.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 
36 #include "cs35l33.h"
37 #include "cirrus_legacy.h"
38 
39 #define CS35L33_BOOT_DELAY	50
40 
41 struct cs35l33_private {
42 	struct snd_soc_component *component;
43 	struct cs35l33_pdata pdata;
44 	struct regmap *regmap;
45 	struct gpio_desc *reset_gpio;
46 	bool amp_cal;
47 	int mclk_int;
48 	struct regulator_bulk_data core_supplies[2];
49 	int num_core_supplies;
50 	bool is_tdm_mode;
51 	bool enable_soft_ramp;
52 };
53 
54 static const struct reg_default cs35l33_reg[] = {
55 	{CS35L33_PWRCTL1, 0x85},
56 	{CS35L33_PWRCTL2, 0xFE},
57 	{CS35L33_CLK_CTL, 0x0C},
58 	{CS35L33_BST_PEAK_CTL, 0x90},
59 	{CS35L33_PROTECT_CTL, 0x55},
60 	{CS35L33_BST_CTL1, 0x00},
61 	{CS35L33_BST_CTL2, 0x01},
62 	{CS35L33_ADSP_CTL, 0x00},
63 	{CS35L33_ADC_CTL, 0xC8},
64 	{CS35L33_DAC_CTL, 0x14},
65 	{CS35L33_DIG_VOL_CTL, 0x00},
66 	{CS35L33_CLASSD_CTL, 0x04},
67 	{CS35L33_AMP_CTL, 0x90},
68 	{CS35L33_INT_MASK_1, 0xFF},
69 	{CS35L33_INT_MASK_2, 0xFF},
70 	{CS35L33_DIAG_LOCK, 0x00},
71 	{CS35L33_DIAG_CTRL_1, 0x40},
72 	{CS35L33_DIAG_CTRL_2, 0x00},
73 	{CS35L33_HG_MEMLDO_CTL, 0x62},
74 	{CS35L33_HG_REL_RATE, 0x03},
75 	{CS35L33_LDO_DEL, 0x12},
76 	{CS35L33_HG_HEAD, 0x0A},
77 	{CS35L33_HG_EN, 0x05},
78 	{CS35L33_TX_VMON, 0x00},
79 	{CS35L33_TX_IMON, 0x03},
80 	{CS35L33_TX_VPMON, 0x02},
81 	{CS35L33_TX_VBSTMON, 0x05},
82 	{CS35L33_TX_FLAG, 0x06},
83 	{CS35L33_TX_EN1, 0x00},
84 	{CS35L33_TX_EN2, 0x00},
85 	{CS35L33_TX_EN3, 0x00},
86 	{CS35L33_TX_EN4, 0x00},
87 	{CS35L33_RX_AUD, 0x40},
88 	{CS35L33_RX_SPLY, 0x03},
89 	{CS35L33_RX_ALIVE, 0x04},
90 	{CS35L33_BST_CTL4, 0x63},
91 };
92 
93 static const struct reg_sequence cs35l33_patch[] = {
94 	{ 0x00,  0x99, 0 },
95 	{ 0x59,  0x02, 0 },
96 	{ 0x52,  0x30, 0 },
97 	{ 0x39,  0x45, 0 },
98 	{ 0x57,  0x30, 0 },
99 	{ 0x2C,  0x68, 0 },
100 	{ 0x00,  0x00, 0 },
101 };
102 
cs35l33_volatile_register(struct device * dev,unsigned int reg)103 static bool cs35l33_volatile_register(struct device *dev, unsigned int reg)
104 {
105 	switch (reg) {
106 	case CS35L33_DEVID_AB:
107 	case CS35L33_DEVID_CD:
108 	case CS35L33_DEVID_E:
109 	case CS35L33_REV_ID:
110 	case CS35L33_INT_STATUS_1:
111 	case CS35L33_INT_STATUS_2:
112 	case CS35L33_HG_STATUS:
113 		return true;
114 	default:
115 		return false;
116 	}
117 }
118 
cs35l33_writeable_register(struct device * dev,unsigned int reg)119 static bool cs35l33_writeable_register(struct device *dev, unsigned int reg)
120 {
121 	switch (reg) {
122 	/* these are read only registers */
123 	case CS35L33_DEVID_AB:
124 	case CS35L33_DEVID_CD:
125 	case CS35L33_DEVID_E:
126 	case CS35L33_REV_ID:
127 	case CS35L33_INT_STATUS_1:
128 	case CS35L33_INT_STATUS_2:
129 	case CS35L33_HG_STATUS:
130 		return false;
131 	default:
132 		return true;
133 	}
134 }
135 
cs35l33_readable_register(struct device * dev,unsigned int reg)136 static bool cs35l33_readable_register(struct device *dev, unsigned int reg)
137 {
138 	switch (reg) {
139 	case CS35L33_DEVID_AB:
140 	case CS35L33_DEVID_CD:
141 	case CS35L33_DEVID_E:
142 	case CS35L33_REV_ID:
143 	case CS35L33_PWRCTL1:
144 	case CS35L33_PWRCTL2:
145 	case CS35L33_CLK_CTL:
146 	case CS35L33_BST_PEAK_CTL:
147 	case CS35L33_PROTECT_CTL:
148 	case CS35L33_BST_CTL1:
149 	case CS35L33_BST_CTL2:
150 	case CS35L33_ADSP_CTL:
151 	case CS35L33_ADC_CTL:
152 	case CS35L33_DAC_CTL:
153 	case CS35L33_DIG_VOL_CTL:
154 	case CS35L33_CLASSD_CTL:
155 	case CS35L33_AMP_CTL:
156 	case CS35L33_INT_MASK_1:
157 	case CS35L33_INT_MASK_2:
158 	case CS35L33_INT_STATUS_1:
159 	case CS35L33_INT_STATUS_2:
160 	case CS35L33_DIAG_LOCK:
161 	case CS35L33_DIAG_CTRL_1:
162 	case CS35L33_DIAG_CTRL_2:
163 	case CS35L33_HG_MEMLDO_CTL:
164 	case CS35L33_HG_REL_RATE:
165 	case CS35L33_LDO_DEL:
166 	case CS35L33_HG_HEAD:
167 	case CS35L33_HG_EN:
168 	case CS35L33_TX_VMON:
169 	case CS35L33_TX_IMON:
170 	case CS35L33_TX_VPMON:
171 	case CS35L33_TX_VBSTMON:
172 	case CS35L33_TX_FLAG:
173 	case CS35L33_TX_EN1:
174 	case CS35L33_TX_EN2:
175 	case CS35L33_TX_EN3:
176 	case CS35L33_TX_EN4:
177 	case CS35L33_RX_AUD:
178 	case CS35L33_RX_SPLY:
179 	case CS35L33_RX_ALIVE:
180 	case CS35L33_BST_CTL4:
181 		return true;
182 	default:
183 		return false;
184 	}
185 }
186 
187 static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0);
188 static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0);
189 
190 static const struct snd_kcontrol_new cs35l33_snd_controls[] = {
191 
192 	SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL,
193 		       4, 0x09, 0, classd_ctl_tlv),
194 	SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL,
195 			0, 0x34, 0xE4, dac_tlv),
196 };
197 
cs35l33_spkrdrv_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)198 static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w,
199 	struct snd_kcontrol *kcontrol, int event)
200 {
201 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
202 	struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
203 
204 	switch (event) {
205 	case SND_SOC_DAPM_POST_PMU:
206 		if (!priv->amp_cal) {
207 			usleep_range(8000, 9000);
208 			priv->amp_cal = true;
209 			regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
210 				    CS35L33_AMP_CAL, 0);
211 			dev_dbg(component->dev, "Amp calibration done\n");
212 		}
213 		dev_dbg(component->dev, "Amp turned on\n");
214 		break;
215 	case SND_SOC_DAPM_POST_PMD:
216 		dev_dbg(component->dev, "Amp turned off\n");
217 		break;
218 	default:
219 		dev_err(component->dev, "Invalid event = 0x%x\n", event);
220 		break;
221 	}
222 
223 	return 0;
224 }
225 
cs35l33_sdin_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)226 static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w,
227 	struct snd_kcontrol *kcontrol, int event)
228 {
229 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
230 	struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
231 	unsigned int val;
232 
233 	switch (event) {
234 	case SND_SOC_DAPM_PRE_PMU:
235 		regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
236 				    CS35L33_PDN_BST, 0);
237 		val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM;
238 		regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
239 				    CS35L33_PDN_TDM, val);
240 		dev_dbg(component->dev, "BST turned on\n");
241 		break;
242 	case SND_SOC_DAPM_POST_PMU:
243 		dev_dbg(component->dev, "SDIN turned on\n");
244 		if (!priv->amp_cal) {
245 			regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
246 				    CS35L33_AMP_CAL, CS35L33_AMP_CAL);
247 			dev_dbg(component->dev, "Amp calibration started\n");
248 			usleep_range(10000, 11000);
249 		}
250 		break;
251 	case SND_SOC_DAPM_POST_PMD:
252 		regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
253 				    CS35L33_PDN_TDM, CS35L33_PDN_TDM);
254 		usleep_range(4000, 4100);
255 		regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
256 				    CS35L33_PDN_BST, CS35L33_PDN_BST);
257 		dev_dbg(component->dev, "BST and SDIN turned off\n");
258 		break;
259 	default:
260 		dev_err(component->dev, "Invalid event = 0x%x\n", event);
261 
262 	}
263 
264 	return 0;
265 }
266 
cs35l33_sdout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)267 static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w,
268 	struct snd_kcontrol *kcontrol, int event)
269 {
270 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
271 	struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
272 	unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
273 	unsigned int mask2 = CS35L33_SDOUT_3ST_TDM;
274 	unsigned int val, val2;
275 
276 	switch (event) {
277 	case SND_SOC_DAPM_PRE_PMU:
278 		if (priv->is_tdm_mode) {
279 			/* set sdout_3st_i2s and reset pdn_tdm */
280 			val = CS35L33_SDOUT_3ST_I2S;
281 			/* reset sdout_3st_tdm */
282 			val2 = 0;
283 		} else {
284 			/* reset sdout_3st_i2s and set pdn_tdm */
285 			val = CS35L33_PDN_TDM;
286 			/* set sdout_3st_tdm */
287 			val2 = CS35L33_SDOUT_3ST_TDM;
288 		}
289 		dev_dbg(component->dev, "SDOUT turned on\n");
290 		break;
291 	case SND_SOC_DAPM_PRE_PMD:
292 		val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
293 		val2 = CS35L33_SDOUT_3ST_TDM;
294 		dev_dbg(component->dev, "SDOUT turned off\n");
295 		break;
296 	default:
297 		dev_err(component->dev, "Invalid event = 0x%x\n", event);
298 		return 0;
299 	}
300 
301 	regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
302 		mask, val);
303 	regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
304 		mask2, val2);
305 
306 	return 0;
307 }
308 
309 static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = {
310 
311 	SND_SOC_DAPM_OUTPUT("SPK"),
312 	SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0,
313 		cs35l33_spkrdrv_event,
314 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
315 	SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2,
316 		2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU |
317 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
318 
319 	SND_SOC_DAPM_INPUT("MON"),
320 
321 	SND_SOC_DAPM_ADC("VMON", NULL,
322 		CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1),
323 	SND_SOC_DAPM_ADC("IMON", NULL,
324 		CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1),
325 	SND_SOC_DAPM_ADC("VPMON", NULL,
326 		CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1),
327 	SND_SOC_DAPM_ADC("VBSTMON", NULL,
328 		CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1),
329 
330 	SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0,
331 		cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU |
332 		SND_SOC_DAPM_PRE_PMD),
333 };
334 
335 static const struct snd_soc_dapm_route cs35l33_audio_map[] = {
336 	{"SDIN", NULL, "CS35L33 Playback"},
337 	{"SPKDRV", NULL, "SDIN"},
338 	{"SPK", NULL, "SPKDRV"},
339 
340 	{"VMON", NULL, "MON"},
341 	{"IMON", NULL, "MON"},
342 
343 	{"SDOUT", NULL, "VMON"},
344 	{"SDOUT", NULL, "IMON"},
345 	{"CS35L33 Capture", NULL, "SDOUT"},
346 };
347 
348 static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = {
349 	{"SPKDRV", NULL, "VPMON"},
350 	{"VPMON", NULL, "CS35L33 Playback"},
351 };
352 
353 static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = {
354 	{"SDOUT", NULL, "VPMON"},
355 	{"VPMON", NULL, "MON"},
356 	{"SDOUT", NULL, "VBSTMON"},
357 	{"VBSTMON", NULL, "MON"},
358 };
359 
cs35l33_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)360 static int cs35l33_set_bias_level(struct snd_soc_component *component,
361 				  enum snd_soc_bias_level level)
362 {
363 	unsigned int val;
364 	struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
365 
366 	switch (level) {
367 	case SND_SOC_BIAS_ON:
368 		break;
369 	case SND_SOC_BIAS_PREPARE:
370 		regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
371 				    CS35L33_PDN_ALL, 0);
372 		regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
373 				    CS35L33_MCLKDIS, 0);
374 		break;
375 	case SND_SOC_BIAS_STANDBY:
376 		regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
377 				    CS35L33_PDN_ALL, CS35L33_PDN_ALL);
378 		regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val);
379 		usleep_range(1000, 1100);
380 		if (val & CS35L33_PDN_DONE)
381 			regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
382 					    CS35L33_MCLKDIS, CS35L33_MCLKDIS);
383 		break;
384 	case SND_SOC_BIAS_OFF:
385 		break;
386 	default:
387 		return -EINVAL;
388 	}
389 
390 	return 0;
391 }
392 
393 struct cs35l33_mclk_div {
394 	int mclk;
395 	int srate;
396 	u8 adsp_rate;
397 	u8 int_fs_ratio;
398 };
399 
400 static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = {
401 	/* MCLK, Sample Rate, adsp_rate, int_fs_ratio */
402 	{5644800, 11025, 0x4, CS35L33_INT_FS_RATE},
403 	{5644800, 22050, 0x8, CS35L33_INT_FS_RATE},
404 	{5644800, 44100, 0xC, CS35L33_INT_FS_RATE},
405 
406 	{6000000,  8000, 0x1, 0},
407 	{6000000, 11025, 0x2, 0},
408 	{6000000, 11029, 0x3, 0},
409 	{6000000, 12000, 0x4, 0},
410 	{6000000, 16000, 0x5, 0},
411 	{6000000, 22050, 0x6, 0},
412 	{6000000, 22059, 0x7, 0},
413 	{6000000, 24000, 0x8, 0},
414 	{6000000, 32000, 0x9, 0},
415 	{6000000, 44100, 0xA, 0},
416 	{6000000, 44118, 0xB, 0},
417 	{6000000, 48000, 0xC, 0},
418 
419 	{6144000,  8000, 0x1, CS35L33_INT_FS_RATE},
420 	{6144000, 12000, 0x4, CS35L33_INT_FS_RATE},
421 	{6144000, 16000, 0x5, CS35L33_INT_FS_RATE},
422 	{6144000, 24000, 0x8, CS35L33_INT_FS_RATE},
423 	{6144000, 32000, 0x9, CS35L33_INT_FS_RATE},
424 	{6144000, 48000, 0xC, CS35L33_INT_FS_RATE},
425 };
426 
cs35l33_get_mclk_coeff(int mclk,int srate)427 static int cs35l33_get_mclk_coeff(int mclk, int srate)
428 {
429 	int i;
430 
431 	for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) {
432 		if (cs35l33_mclk_coeffs[i].mclk == mclk &&
433 			cs35l33_mclk_coeffs[i].srate == srate)
434 			return i;
435 	}
436 	return -EINVAL;
437 }
438 
cs35l33_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)439 static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
440 {
441 	struct snd_soc_component *component = codec_dai->component;
442 	struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
443 
444 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
445 	case SND_SOC_DAIFMT_CBM_CFM:
446 		regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
447 			CS35L33_MS_MASK, CS35L33_MS_MASK);
448 		dev_dbg(component->dev, "Audio port in master mode\n");
449 		break;
450 	case SND_SOC_DAIFMT_CBS_CFS:
451 		regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
452 			CS35L33_MS_MASK, 0);
453 		dev_dbg(component->dev, "Audio port in slave mode\n");
454 		break;
455 	default:
456 		return -EINVAL;
457 	}
458 
459 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
460 	case SND_SOC_DAIFMT_DSP_A:
461 		/*
462 		 * tdm mode in cs35l33 resembles dsp-a mode very
463 		 * closely, it is dsp-a with fsync shifted left by half bclk
464 		 */
465 		priv->is_tdm_mode = true;
466 		dev_dbg(component->dev, "Audio port in TDM mode\n");
467 		break;
468 	case SND_SOC_DAIFMT_I2S:
469 		priv->is_tdm_mode = false;
470 		dev_dbg(component->dev, "Audio port in I2S mode\n");
471 		break;
472 	default:
473 		return -EINVAL;
474 	}
475 
476 	return 0;
477 }
478 
cs35l33_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)479 static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream,
480 				 struct snd_pcm_hw_params *params,
481 				 struct snd_soc_dai *dai)
482 {
483 	struct snd_soc_component *component = dai->component;
484 	struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
485 	int sample_size = params_width(params);
486 	int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params));
487 
488 	if (coeff < 0)
489 		return coeff;
490 
491 	regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
492 		CS35L33_ADSP_FS | CS35L33_INT_FS_RATE,
493 		cs35l33_mclk_coeffs[coeff].int_fs_ratio
494 		| cs35l33_mclk_coeffs[coeff].adsp_rate);
495 
496 	if (priv->is_tdm_mode) {
497 		sample_size = (sample_size / 8) - 1;
498 		if (sample_size > 2)
499 			sample_size = 2;
500 		regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
501 			CS35L33_AUDIN_RX_DEPTH,
502 			sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT);
503 	}
504 
505 	dev_dbg(component->dev, "sample rate=%d, bits per sample=%d\n",
506 		params_rate(params), params_width(params));
507 
508 	return 0;
509 }
510 
511 static const unsigned int cs35l33_src_rates[] = {
512 	8000, 11025, 11029, 12000, 16000, 22050,
513 	22059, 24000, 32000, 44100, 44118, 48000
514 };
515 
516 static const struct snd_pcm_hw_constraint_list cs35l33_constraints = {
517 	.count  = ARRAY_SIZE(cs35l33_src_rates),
518 	.list   = cs35l33_src_rates,
519 };
520 
cs35l33_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)521 static int cs35l33_pcm_startup(struct snd_pcm_substream *substream,
522 			       struct snd_soc_dai *dai)
523 {
524 	snd_pcm_hw_constraint_list(substream->runtime, 0,
525 					SNDRV_PCM_HW_PARAM_RATE,
526 					&cs35l33_constraints);
527 	return 0;
528 }
529 
cs35l33_set_tristate(struct snd_soc_dai * dai,int tristate)530 static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate)
531 {
532 	struct snd_soc_component *component = dai->component;
533 	struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
534 
535 	if (tristate) {
536 		regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
537 			CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S);
538 		regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
539 			CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM);
540 	} else {
541 		regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
542 			CS35L33_SDOUT_3ST_I2S, 0);
543 		regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
544 			CS35L33_SDOUT_3ST_TDM, 0);
545 	}
546 
547 	return 0;
548 }
549 
cs35l33_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)550 static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
551 				unsigned int rx_mask, int slots, int slot_width)
552 {
553 	struct snd_soc_component *component = dai->component;
554 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
555 	struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
556 	unsigned int reg, bit_pos, i;
557 	int slot, slot_num;
558 
559 	if (slot_width != 8)
560 		return -EINVAL;
561 
562 	/* scan rx_mask for aud slot */
563 	slot = ffs(rx_mask) - 1;
564 	if (slot >= 0) {
565 		regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
566 			CS35L33_X_LOC, slot);
567 		dev_dbg(component->dev, "Audio starts from slots %d", slot);
568 	}
569 
570 	/*
571 	 * scan tx_mask: vmon(2 slots); imon (2 slots);
572 	 * vpmon (1 slot) vbstmon (1 slot)
573 	 */
574 	slot = ffs(tx_mask) - 1;
575 	slot_num = 0;
576 
577 	for (i = 0; i < 2 ; i++) {
578 		/* disable vpmon/vbstmon: enable later if set in tx_mask */
579 		regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i,
580 			CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE
581 			| CS35L33_X_LOC);
582 	}
583 
584 	/* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
585 	snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route,
586 		ARRAY_SIZE(cs35l33_vp_vbst_mon_route));
587 
588 	while (slot >= 0) {
589 		/* configure VMON_TX_LOC */
590 		if (slot_num == 0) {
591 			regmap_update_bits(priv->regmap, CS35L33_TX_VMON,
592 				CS35L33_X_STATE | CS35L33_X_LOC, slot);
593 			dev_dbg(component->dev, "VMON enabled in slots %d-%d",
594 				slot, slot + 1);
595 		}
596 
597 		/* configure IMON_TX_LOC */
598 		if (slot_num == 3) {
599 			regmap_update_bits(priv->regmap, CS35L33_TX_IMON,
600 				CS35L33_X_STATE | CS35L33_X_LOC, slot);
601 			dev_dbg(component->dev, "IMON enabled in slots %d-%d",
602 				slot, slot + 1);
603 		}
604 
605 		/* configure VPMON_TX_LOC */
606 		if (slot_num == 4) {
607 			regmap_update_bits(priv->regmap, CS35L33_TX_VPMON,
608 				CS35L33_X_STATE | CS35L33_X_LOC, slot);
609 			snd_soc_dapm_add_routes(dapm,
610 				&cs35l33_vp_vbst_mon_route[0], 2);
611 			dev_dbg(component->dev, "VPMON enabled in slots %d", slot);
612 		}
613 
614 		/* configure VBSTMON_TX_LOC */
615 		if (slot_num == 5) {
616 			regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON,
617 				CS35L33_X_STATE | CS35L33_X_LOC, slot);
618 			snd_soc_dapm_add_routes(dapm,
619 				&cs35l33_vp_vbst_mon_route[2], 2);
620 			dev_dbg(component->dev,
621 				"VBSTMON enabled in slots %d", slot);
622 		}
623 
624 		/* Enable the relevant tx slot */
625 		reg = CS35L33_TX_EN4 - (slot/8);
626 		bit_pos = slot - ((slot / 8) * (8));
627 		regmap_update_bits(priv->regmap, reg,
628 			1 << bit_pos, 1 << bit_pos);
629 
630 		tx_mask &= ~(1 << slot);
631 		slot = ffs(tx_mask) - 1;
632 		slot_num++;
633 	}
634 
635 	return 0;
636 }
637 
cs35l33_component_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)638 static int cs35l33_component_set_sysclk(struct snd_soc_component *component,
639 		int clk_id, int source, unsigned int freq, int dir)
640 {
641 	struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
642 
643 	switch (freq) {
644 	case CS35L33_MCLK_5644:
645 	case CS35L33_MCLK_6:
646 	case CS35L33_MCLK_6144:
647 		regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
648 			CS35L33_MCLKDIV2, 0);
649 		cs35l33->mclk_int = freq;
650 		break;
651 	case CS35L33_MCLK_11289:
652 	case CS35L33_MCLK_12:
653 	case CS35L33_MCLK_12288:
654 		regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
655 			CS35L33_MCLKDIV2, CS35L33_MCLKDIV2);
656 		cs35l33->mclk_int = freq/2;
657 		break;
658 	default:
659 		cs35l33->mclk_int = 0;
660 		return -EINVAL;
661 	}
662 
663 	dev_dbg(component->dev, "external mclk freq=%d, internal mclk freq=%d\n",
664 		freq, cs35l33->mclk_int);
665 
666 	return 0;
667 }
668 
669 static const struct snd_soc_dai_ops cs35l33_ops = {
670 	.startup = cs35l33_pcm_startup,
671 	.set_tristate = cs35l33_set_tristate,
672 	.set_fmt = cs35l33_set_dai_fmt,
673 	.hw_params = cs35l33_pcm_hw_params,
674 	.set_tdm_slot = cs35l33_set_tdm_slot,
675 };
676 
677 static struct snd_soc_dai_driver cs35l33_dai = {
678 		.name = "cs35l33-dai",
679 		.id = 0,
680 		.playback = {
681 			.stream_name = "CS35L33 Playback",
682 			.channels_min = 1,
683 			.channels_max = 1,
684 			.rates = CS35L33_RATES,
685 			.formats = CS35L33_FORMATS,
686 		},
687 		.capture = {
688 			.stream_name = "CS35L33 Capture",
689 			.channels_min = 2,
690 			.channels_max = 2,
691 			.rates = CS35L33_RATES,
692 			.formats = CS35L33_FORMATS,
693 		},
694 		.ops = &cs35l33_ops,
695 		.symmetric_rate = 1,
696 };
697 
cs35l33_set_hg_data(struct snd_soc_component * component,struct cs35l33_pdata * pdata)698 static int cs35l33_set_hg_data(struct snd_soc_component *component,
699 			       struct cs35l33_pdata *pdata)
700 {
701 	struct cs35l33_hg *hg_config = &pdata->hg_config;
702 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
703 	struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
704 
705 	if (hg_config->enable_hg_algo) {
706 		regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
707 			CS35L33_MEM_DEPTH_MASK,
708 			hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT);
709 		regmap_write(priv->regmap, CS35L33_HG_REL_RATE,
710 			hg_config->release_rate);
711 		regmap_update_bits(priv->regmap, CS35L33_HG_HEAD,
712 			CS35L33_HD_RM_MASK,
713 			hg_config->hd_rm << CS35L33_HD_RM_SHIFT);
714 		regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
715 			CS35L33_LDO_THLD_MASK,
716 			hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT);
717 		regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
718 			CS35L33_LDO_DISABLE_MASK,
719 			hg_config->ldo_path_disable <<
720 				CS35L33_LDO_DISABLE_SHIFT);
721 		regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
722 			CS35L33_LDO_ENTRY_DELAY_MASK,
723 			hg_config->ldo_entry_delay <<
724 				CS35L33_LDO_ENTRY_DELAY_SHIFT);
725 		if (hg_config->vp_hg_auto) {
726 			regmap_update_bits(priv->regmap, CS35L33_HG_EN,
727 				CS35L33_VP_HG_AUTO_MASK,
728 				CS35L33_VP_HG_AUTO_MASK);
729 			snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route,
730 				ARRAY_SIZE(cs35l33_vphg_auto_route));
731 		}
732 		regmap_update_bits(priv->regmap, CS35L33_HG_EN,
733 			CS35L33_VP_HG_MASK,
734 			hg_config->vp_hg << CS35L33_VP_HG_SHIFT);
735 		regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
736 			CS35L33_VP_HG_RATE_MASK,
737 			hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT);
738 		regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
739 			CS35L33_VP_HG_VA_MASK,
740 			hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT);
741 		regmap_update_bits(priv->regmap, CS35L33_HG_EN,
742 			CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK);
743 	}
744 	return 0;
745 }
746 
cs35l33_set_bst_ipk(struct snd_soc_component * component,unsigned int bst)747 static int cs35l33_set_bst_ipk(struct snd_soc_component *component, unsigned int bst)
748 {
749 	struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
750 	int ret = 0, steps = 0;
751 
752 	/* Boost current in uA */
753 	if (bst > 3600000 || bst < 1850000) {
754 		dev_err(component->dev, "Invalid boost current %d\n", bst);
755 		ret = -EINVAL;
756 		goto err;
757 	}
758 
759 	if (bst % 15625) {
760 		dev_err(component->dev, "Current not a multiple of 15625uA (%d)\n",
761 			bst);
762 		ret = -EINVAL;
763 		goto err;
764 	}
765 
766 	while (bst > 1850000) {
767 		bst -= 15625;
768 		steps++;
769 	}
770 
771 	regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL,
772 		steps+0x70);
773 
774 err:
775 	return ret;
776 }
777 
cs35l33_probe(struct snd_soc_component * component)778 static int cs35l33_probe(struct snd_soc_component *component)
779 {
780 	struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
781 
782 	cs35l33->component = component;
783 	pm_runtime_get_sync(component->dev);
784 
785 	regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL,
786 		CS35L33_ALIVE_WD_DIS, 0x8);
787 	regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2,
788 				CS35L33_ALIVE_WD_DIS2,
789 				CS35L33_ALIVE_WD_DIS2);
790 
791 	/* Set Platform Data */
792 	regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1,
793 		CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl);
794 	regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL,
795 		CS35L33_AMP_DRV_SEL_MASK,
796 		cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT);
797 
798 	if (cs35l33->pdata.boost_ipk)
799 		cs35l33_set_bst_ipk(component, cs35l33->pdata.boost_ipk);
800 
801 	if (cs35l33->enable_soft_ramp) {
802 		snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
803 			CS35L33_DIGSFT, CS35L33_DIGSFT);
804 		snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
805 			CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate);
806 	} else {
807 		snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
808 			CS35L33_DIGSFT, 0);
809 	}
810 
811 	/* update IMON scaling rate if different from default of 0x8 */
812 	if (cs35l33->pdata.imon_adc_scale != 0x8)
813 		snd_soc_component_update_bits(component, CS35L33_ADC_CTL,
814 			CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale);
815 
816 	cs35l33_set_hg_data(component, &(cs35l33->pdata));
817 
818 	/*
819 	 * unmask important interrupts that causes the chip to enter
820 	 * speaker safe mode and hence deserves user attention
821 	 */
822 	regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1,
823 		CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT |
824 		CS35L33_M_CAL_ERR, 0);
825 
826 	pm_runtime_put_sync(component->dev);
827 
828 	return 0;
829 }
830 
831 static const struct snd_soc_component_driver soc_component_dev_cs35l33 = {
832 	.probe			= cs35l33_probe,
833 	.set_bias_level		= cs35l33_set_bias_level,
834 	.set_sysclk		= cs35l33_component_set_sysclk,
835 	.controls		= cs35l33_snd_controls,
836 	.num_controls		= ARRAY_SIZE(cs35l33_snd_controls),
837 	.dapm_widgets		= cs35l33_dapm_widgets,
838 	.num_dapm_widgets	= ARRAY_SIZE(cs35l33_dapm_widgets),
839 	.dapm_routes		= cs35l33_audio_map,
840 	.num_dapm_routes	= ARRAY_SIZE(cs35l33_audio_map),
841 	.use_pmdown_time	= 1,
842 	.endianness		= 1,
843 };
844 
845 static const struct regmap_config cs35l33_regmap = {
846 	.reg_bits = 8,
847 	.val_bits = 8,
848 
849 	.max_register = CS35L33_MAX_REGISTER,
850 	.reg_defaults = cs35l33_reg,
851 	.num_reg_defaults = ARRAY_SIZE(cs35l33_reg),
852 	.volatile_reg = cs35l33_volatile_register,
853 	.readable_reg = cs35l33_readable_register,
854 	.writeable_reg = cs35l33_writeable_register,
855 	.cache_type = REGCACHE_RBTREE,
856 	.use_single_read = true,
857 	.use_single_write = true,
858 };
859 
cs35l33_runtime_resume(struct device * dev)860 static int __maybe_unused cs35l33_runtime_resume(struct device *dev)
861 {
862 	struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
863 	int ret;
864 
865 	dev_dbg(dev, "%s\n", __func__);
866 
867 	gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
868 
869 	ret = regulator_bulk_enable(cs35l33->num_core_supplies,
870 		cs35l33->core_supplies);
871 	if (ret != 0) {
872 		dev_err(dev, "Failed to enable core supplies: %d\n", ret);
873 		return ret;
874 	}
875 
876 	regcache_cache_only(cs35l33->regmap, false);
877 
878 	gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
879 
880 	msleep(CS35L33_BOOT_DELAY);
881 
882 	ret = regcache_sync(cs35l33->regmap);
883 	if (ret != 0) {
884 		dev_err(dev, "Failed to restore register cache\n");
885 		goto err;
886 	}
887 
888 	return 0;
889 
890 err:
891 	regcache_cache_only(cs35l33->regmap, true);
892 	regulator_bulk_disable(cs35l33->num_core_supplies,
893 		cs35l33->core_supplies);
894 
895 	return ret;
896 }
897 
cs35l33_runtime_suspend(struct device * dev)898 static int __maybe_unused cs35l33_runtime_suspend(struct device *dev)
899 {
900 	struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
901 
902 	dev_dbg(dev, "%s\n", __func__);
903 
904 	/* redo the calibration in next power up */
905 	cs35l33->amp_cal = false;
906 
907 	regcache_cache_only(cs35l33->regmap, true);
908 	regcache_mark_dirty(cs35l33->regmap);
909 	regulator_bulk_disable(cs35l33->num_core_supplies,
910 		cs35l33->core_supplies);
911 
912 	return 0;
913 }
914 
915 static const struct dev_pm_ops cs35l33_pm_ops = {
916 	SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend,
917 			   cs35l33_runtime_resume,
918 			   NULL)
919 };
920 
cs35l33_get_hg_data(const struct device_node * np,struct cs35l33_pdata * pdata)921 static int cs35l33_get_hg_data(const struct device_node *np,
922 			       struct cs35l33_pdata *pdata)
923 {
924 	struct device_node *hg;
925 	struct cs35l33_hg *hg_config = &pdata->hg_config;
926 	u32 val32;
927 
928 	hg = of_get_child_by_name(np, "cirrus,hg-algo");
929 	hg_config->enable_hg_algo = hg ? true : false;
930 
931 	if (hg_config->enable_hg_algo) {
932 		if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0)
933 			hg_config->mem_depth = val32;
934 		if (of_property_read_u32(hg, "cirrus,release-rate",
935 				&val32) >= 0)
936 			hg_config->release_rate = val32;
937 		if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0)
938 			hg_config->ldo_thld = val32;
939 		if (of_property_read_u32(hg, "cirrus,ldo-path-disable",
940 				&val32) >= 0)
941 			hg_config->ldo_path_disable = val32;
942 		if (of_property_read_u32(hg, "cirrus,ldo-entry-delay",
943 				&val32) >= 0)
944 			hg_config->ldo_entry_delay = val32;
945 
946 		hg_config->vp_hg_auto = of_property_read_bool(hg,
947 			"cirrus,vp-hg-auto");
948 
949 		if (of_property_read_u32(hg, "cirrus,vp-hg", &val32) >= 0)
950 			hg_config->vp_hg = val32;
951 		if (of_property_read_u32(hg, "cirrus,vp-hg-rate", &val32) >= 0)
952 			hg_config->vp_hg_rate = val32;
953 		if (of_property_read_u32(hg, "cirrus,vp-hg-va", &val32) >= 0)
954 			hg_config->vp_hg_va = val32;
955 	}
956 
957 	of_node_put(hg);
958 
959 	return 0;
960 }
961 
cs35l33_irq_thread(int irq,void * data)962 static irqreturn_t cs35l33_irq_thread(int irq, void *data)
963 {
964 	struct cs35l33_private *cs35l33 = data;
965 	struct snd_soc_component *component = cs35l33->component;
966 	unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2;
967 
968 	regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2,
969 		&sticky_val2);
970 	regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
971 		&sticky_val1);
972 	regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2);
973 	regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1);
974 
975 	/* Check to see if the unmasked bits are active,
976 	 *  if not then exit.
977 	 */
978 	if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2))
979 		return IRQ_NONE;
980 
981 	regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
982 		&current_val);
983 
984 	/* handle the interrupts */
985 
986 	if (sticky_val1 & CS35L33_AMP_SHORT) {
987 		dev_crit(component->dev, "Amp short error\n");
988 		if (!(current_val & CS35L33_AMP_SHORT)) {
989 			dev_dbg(component->dev,
990 				"Amp short error release\n");
991 			regmap_update_bits(cs35l33->regmap,
992 				CS35L33_AMP_CTL,
993 				CS35L33_AMP_SHORT_RLS, 0);
994 			regmap_update_bits(cs35l33->regmap,
995 				CS35L33_AMP_CTL,
996 				CS35L33_AMP_SHORT_RLS,
997 				CS35L33_AMP_SHORT_RLS);
998 			regmap_update_bits(cs35l33->regmap,
999 				CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS,
1000 				0);
1001 		}
1002 	}
1003 
1004 	if (sticky_val1 & CS35L33_CAL_ERR) {
1005 		dev_err(component->dev, "Cal error\n");
1006 
1007 		/* redo the calibration in next power up */
1008 		cs35l33->amp_cal = false;
1009 
1010 		if (!(current_val & CS35L33_CAL_ERR)) {
1011 			dev_dbg(component->dev, "Cal error release\n");
1012 			regmap_update_bits(cs35l33->regmap,
1013 				CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1014 				0);
1015 			regmap_update_bits(cs35l33->regmap,
1016 				CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1017 				CS35L33_CAL_ERR_RLS);
1018 			regmap_update_bits(cs35l33->regmap,
1019 				CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1020 				0);
1021 		}
1022 	}
1023 
1024 	if (sticky_val1 & CS35L33_OTE) {
1025 		dev_crit(component->dev, "Over temperature error\n");
1026 		if (!(current_val & CS35L33_OTE)) {
1027 			dev_dbg(component->dev,
1028 				"Over temperature error release\n");
1029 			regmap_update_bits(cs35l33->regmap,
1030 				CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1031 			regmap_update_bits(cs35l33->regmap,
1032 				CS35L33_AMP_CTL, CS35L33_OTE_RLS,
1033 				CS35L33_OTE_RLS);
1034 			regmap_update_bits(cs35l33->regmap,
1035 				CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1036 		}
1037 	}
1038 
1039 	if (sticky_val1 & CS35L33_OTW) {
1040 		dev_err(component->dev, "Over temperature warning\n");
1041 		if (!(current_val & CS35L33_OTW)) {
1042 			dev_dbg(component->dev,
1043 				"Over temperature warning release\n");
1044 			regmap_update_bits(cs35l33->regmap,
1045 				CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1046 			regmap_update_bits(cs35l33->regmap,
1047 				CS35L33_AMP_CTL, CS35L33_OTW_RLS,
1048 				CS35L33_OTW_RLS);
1049 			regmap_update_bits(cs35l33->regmap,
1050 				CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1051 		}
1052 	}
1053 	if (CS35L33_ALIVE_ERR & sticky_val1)
1054 		dev_err(component->dev, "ERROR: ADSPCLK Interrupt\n");
1055 
1056 	if (CS35L33_MCLK_ERR & sticky_val1)
1057 		dev_err(component->dev, "ERROR: MCLK Interrupt\n");
1058 
1059 	if (CS35L33_VMON_OVFL & sticky_val2)
1060 		dev_err(component->dev,
1061 			"ERROR: VMON Overflow Interrupt\n");
1062 
1063 	if (CS35L33_IMON_OVFL & sticky_val2)
1064 		dev_err(component->dev,
1065 			"ERROR: IMON Overflow Interrupt\n");
1066 
1067 	if (CS35L33_VPMON_OVFL & sticky_val2)
1068 		dev_err(component->dev,
1069 			"ERROR: VPMON Overflow Interrupt\n");
1070 
1071 	return IRQ_HANDLED;
1072 }
1073 
1074 static const char * const cs35l33_core_supplies[] = {
1075 	"VA",
1076 	"VP",
1077 };
1078 
cs35l33_of_get_pdata(struct device * dev,struct cs35l33_private * cs35l33)1079 static int cs35l33_of_get_pdata(struct device *dev,
1080 				struct cs35l33_private *cs35l33)
1081 {
1082 	struct device_node *np = dev->of_node;
1083 	struct cs35l33_pdata *pdata = &cs35l33->pdata;
1084 	u32 val32;
1085 
1086 	if (!np)
1087 		return 0;
1088 
1089 	if (of_property_read_u32(np, "cirrus,boost-ctl", &val32) >= 0) {
1090 		pdata->boost_ctl = val32;
1091 		pdata->amp_drv_sel = 1;
1092 	}
1093 
1094 	if (of_property_read_u32(np, "cirrus,ramp-rate", &val32) >= 0) {
1095 		pdata->ramp_rate = val32;
1096 		cs35l33->enable_soft_ramp = true;
1097 	}
1098 
1099 	if (of_property_read_u32(np, "cirrus,boost-ipk", &val32) >= 0)
1100 		pdata->boost_ipk = val32;
1101 
1102 	if (of_property_read_u32(np, "cirrus,imon-adc-scale", &val32) >= 0) {
1103 		if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6))
1104 			pdata->imon_adc_scale = val32;
1105 		else
1106 			/* use default value */
1107 			pdata->imon_adc_scale = 0x8;
1108 	} else {
1109 		/* use default value */
1110 		pdata->imon_adc_scale = 0x8;
1111 	}
1112 
1113 	cs35l33_get_hg_data(np, pdata);
1114 
1115 	return 0;
1116 }
1117 
cs35l33_i2c_probe(struct i2c_client * i2c_client)1118 static int cs35l33_i2c_probe(struct i2c_client *i2c_client)
1119 {
1120 	struct cs35l33_private *cs35l33;
1121 	struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev);
1122 	int ret, devid, i;
1123 	unsigned int reg;
1124 
1125 	cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private),
1126 			       GFP_KERNEL);
1127 	if (!cs35l33)
1128 		return -ENOMEM;
1129 
1130 	i2c_set_clientdata(i2c_client, cs35l33);
1131 	cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap);
1132 	if (IS_ERR(cs35l33->regmap)) {
1133 		ret = PTR_ERR(cs35l33->regmap);
1134 		dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1135 		return ret;
1136 	}
1137 
1138 	regcache_cache_only(cs35l33->regmap, true);
1139 
1140 	for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++)
1141 		cs35l33->core_supplies[i].supply
1142 			= cs35l33_core_supplies[i];
1143 	cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies);
1144 
1145 	ret = devm_regulator_bulk_get(&i2c_client->dev,
1146 			cs35l33->num_core_supplies,
1147 			cs35l33->core_supplies);
1148 	if (ret != 0) {
1149 		dev_err(&i2c_client->dev,
1150 			"Failed to request core supplies: %d\n",
1151 			ret);
1152 		return ret;
1153 	}
1154 
1155 	if (pdata) {
1156 		cs35l33->pdata = *pdata;
1157 	} else {
1158 		cs35l33_of_get_pdata(&i2c_client->dev, cs35l33);
1159 		pdata = &cs35l33->pdata;
1160 	}
1161 
1162 	ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
1163 			cs35l33_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1164 			"cs35l33", cs35l33);
1165 	if (ret != 0)
1166 		dev_warn(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
1167 
1168 	/* We could issue !RST or skip it based on AMP topology */
1169 	cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1170 			"reset-gpios", GPIOD_OUT_HIGH);
1171 	if (IS_ERR(cs35l33->reset_gpio)) {
1172 		dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n",
1173 			__func__);
1174 		return PTR_ERR(cs35l33->reset_gpio);
1175 	}
1176 
1177 	ret = regulator_bulk_enable(cs35l33->num_core_supplies,
1178 					cs35l33->core_supplies);
1179 	if (ret != 0) {
1180 		dev_err(&i2c_client->dev,
1181 			"Failed to enable core supplies: %d\n",
1182 			ret);
1183 		return ret;
1184 	}
1185 
1186 	gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
1187 
1188 	msleep(CS35L33_BOOT_DELAY);
1189 	regcache_cache_only(cs35l33->regmap, false);
1190 
1191 	/* initialize codec */
1192 	devid = cirrus_read_device_id(cs35l33->regmap, CS35L33_DEVID_AB);
1193 	if (devid < 0) {
1194 		ret = devid;
1195 		dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
1196 		goto err_enable;
1197 	}
1198 
1199 	if (devid != CS35L33_CHIP_ID) {
1200 		dev_err(&i2c_client->dev,
1201 			"CS35L33 Device ID (%X). Expected ID %X\n",
1202 			devid, CS35L33_CHIP_ID);
1203 		ret = -EINVAL;
1204 		goto err_enable;
1205 	}
1206 
1207 	ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, &reg);
1208 	if (ret < 0) {
1209 		dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1210 		goto err_enable;
1211 	}
1212 
1213 	dev_info(&i2c_client->dev,
1214 		 "Cirrus Logic CS35L33, Revision: %02X\n", reg & 0xFF);
1215 
1216 	ret = regmap_register_patch(cs35l33->regmap,
1217 			cs35l33_patch, ARRAY_SIZE(cs35l33_patch));
1218 	if (ret < 0) {
1219 		dev_err(&i2c_client->dev,
1220 			"Error in applying regmap patch: %d\n", ret);
1221 		goto err_enable;
1222 	}
1223 
1224 	/* disable mclk and tdm */
1225 	regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
1226 		CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM,
1227 		CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM);
1228 
1229 	pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
1230 	pm_runtime_use_autosuspend(&i2c_client->dev);
1231 	pm_runtime_set_active(&i2c_client->dev);
1232 	pm_runtime_enable(&i2c_client->dev);
1233 
1234 	ret = devm_snd_soc_register_component(&i2c_client->dev,
1235 			&soc_component_dev_cs35l33, &cs35l33_dai, 1);
1236 	if (ret < 0) {
1237 		dev_err(&i2c_client->dev, "%s: Register component failed\n",
1238 			__func__);
1239 		goto err_enable;
1240 	}
1241 
1242 	return 0;
1243 
1244 err_enable:
1245 	gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
1246 
1247 	regulator_bulk_disable(cs35l33->num_core_supplies,
1248 			       cs35l33->core_supplies);
1249 
1250 	return ret;
1251 }
1252 
cs35l33_i2c_remove(struct i2c_client * client)1253 static void cs35l33_i2c_remove(struct i2c_client *client)
1254 {
1255 	struct cs35l33_private *cs35l33 = i2c_get_clientdata(client);
1256 
1257 	gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
1258 
1259 	pm_runtime_disable(&client->dev);
1260 	regulator_bulk_disable(cs35l33->num_core_supplies,
1261 		cs35l33->core_supplies);
1262 }
1263 
1264 static const struct of_device_id cs35l33_of_match[] = {
1265 	{ .compatible = "cirrus,cs35l33", },
1266 	{},
1267 };
1268 MODULE_DEVICE_TABLE(of, cs35l33_of_match);
1269 
1270 static const struct i2c_device_id cs35l33_id[] = {
1271 	{"cs35l33", 0},
1272 	{}
1273 };
1274 
1275 MODULE_DEVICE_TABLE(i2c, cs35l33_id);
1276 
1277 static struct i2c_driver cs35l33_i2c_driver = {
1278 	.driver = {
1279 		.name = "cs35l33",
1280 		.pm = &cs35l33_pm_ops,
1281 		.of_match_table = cs35l33_of_match,
1282 
1283 		},
1284 	.id_table = cs35l33_id,
1285 	.probe_new = cs35l33_i2c_probe,
1286 	.remove = cs35l33_i2c_remove,
1287 
1288 };
1289 module_i2c_driver(cs35l33_i2c_driver);
1290 
1291 MODULE_DESCRIPTION("ASoC CS35L33 driver");
1292 MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
1293 MODULE_LICENSE("GPL");
1294