1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * HD-audio stream operations
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <linux/clocksource.h>
10 #include <sound/core.h>
11 #include <sound/pcm.h>
12 #include <sound/hdaudio.h>
13 #include <sound/hda_register.h>
14 #include "trace.h"
15 
16 /*
17  * the hdac_stream library is intended to be used with the following
18  * transitions. The states are not formally defined in the code but loosely
19  * inspired by boolean variables. Note that the 'prepared' field is not used
20  * in this library but by the callers during the hw_params/prepare transitions
21  *
22  *			   |
23  *	stream_init()	   |
24  *			   v
25  *			+--+-------+
26  *			|  unused  |
27  *			+--+----+--+
28  *			   |    ^
29  *	stream_assign()	   | 	|    stream_release()
30  *			   v	|
31  *			+--+----+--+
32  *			|  opened  |
33  *			+--+----+--+
34  *			   |    ^
35  *	stream_reset()	   |    |
36  *	stream_setup()	   |	|    stream_cleanup()
37  *			   v	|
38  *			+--+----+--+
39  *			| prepared |
40  *			+--+----+--+
41  *			   |    ^
42  *	stream_start()	   | 	|    stream_stop()
43  *			   v	|
44  *			+--+----+--+
45  *			|  running |
46  *			+----------+
47  */
48 
49 /**
50  * snd_hdac_get_stream_stripe_ctl - get stripe control value
51  * @bus: HD-audio core bus
52  * @substream: PCM substream
53  */
snd_hdac_get_stream_stripe_ctl(struct hdac_bus * bus,struct snd_pcm_substream * substream)54 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
55 				   struct snd_pcm_substream *substream)
56 {
57 	struct snd_pcm_runtime *runtime = substream->runtime;
58 	unsigned int channels = runtime->channels,
59 		     rate = runtime->rate,
60 		     bits_per_sample = runtime->sample_bits,
61 		     max_sdo_lines, value, sdo_line;
62 
63 	/* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
64 	max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
65 
66 	/* following is from HD audio spec */
67 	for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
68 		if (rate > 48000)
69 			value = (channels * bits_per_sample *
70 					(rate / 48000)) / sdo_line;
71 		else
72 			value = (channels * bits_per_sample) / sdo_line;
73 
74 		if (value >= bus->sdo_limit)
75 			break;
76 	}
77 
78 	/* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
79 	return sdo_line >> 1;
80 }
81 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
82 
83 /**
84  * snd_hdac_stream_init - initialize each stream (aka device)
85  * @bus: HD-audio core bus
86  * @azx_dev: HD-audio core stream object to initialize
87  * @idx: stream index number
88  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
89  * @tag: the tag id to assign
90  *
91  * Assign the starting bdl address to each stream (device) and initialize.
92  */
snd_hdac_stream_init(struct hdac_bus * bus,struct hdac_stream * azx_dev,int idx,int direction,int tag)93 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
94 			  int idx, int direction, int tag)
95 {
96 	azx_dev->bus = bus;
97 	/* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
98 	azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
99 	/* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
100 	azx_dev->sd_int_sta_mask = 1 << idx;
101 	azx_dev->index = idx;
102 	azx_dev->direction = direction;
103 	azx_dev->stream_tag = tag;
104 	snd_hdac_dsp_lock_init(azx_dev);
105 	list_add_tail(&azx_dev->list, &bus->stream_list);
106 }
107 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
108 
109 /**
110  * snd_hdac_stream_start - start a stream
111  * @azx_dev: HD-audio core stream to start
112  * @fresh_start: false = wallclock timestamp relative to period wallclock
113  *
114  * Start a stream, set start_wallclk and set the running flag.
115  */
snd_hdac_stream_start(struct hdac_stream * azx_dev,bool fresh_start)116 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
117 {
118 	struct hdac_bus *bus = azx_dev->bus;
119 	int stripe_ctl;
120 
121 	trace_snd_hdac_stream_start(bus, azx_dev);
122 
123 	azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
124 	if (!fresh_start)
125 		azx_dev->start_wallclk -= azx_dev->period_wallclk;
126 
127 	/* enable SIE */
128 	snd_hdac_chip_updatel(bus, INTCTL,
129 			      1 << azx_dev->index,
130 			      1 << azx_dev->index);
131 	/* set stripe control */
132 	if (azx_dev->stripe) {
133 		if (azx_dev->substream)
134 			stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
135 		else
136 			stripe_ctl = 0;
137 		snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
138 					stripe_ctl);
139 	}
140 	/* set DMA start and interrupt mask */
141 	snd_hdac_stream_updateb(azx_dev, SD_CTL,
142 				0, SD_CTL_DMA_START | SD_INT_MASK);
143 	azx_dev->running = true;
144 }
145 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
146 
147 /**
148  * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers
149  * @azx_dev: HD-audio core stream to stop
150  */
snd_hdac_stream_clear(struct hdac_stream * azx_dev)151 static void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
152 {
153 	snd_hdac_stream_updateb(azx_dev, SD_CTL,
154 				SD_CTL_DMA_START | SD_INT_MASK, 0);
155 	snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
156 	if (azx_dev->stripe)
157 		snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
158 	azx_dev->running = false;
159 }
160 
161 /**
162  * snd_hdac_stream_stop - stop a stream
163  * @azx_dev: HD-audio core stream to stop
164  *
165  * Stop a stream DMA and disable stream interrupt
166  */
snd_hdac_stream_stop(struct hdac_stream * azx_dev)167 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
168 {
169 	trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
170 
171 	snd_hdac_stream_clear(azx_dev);
172 	/* disable SIE */
173 	snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
174 }
175 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
176 
177 /**
178  * snd_hdac_stop_streams - stop all streams
179  * @bus: HD-audio core bus
180  */
snd_hdac_stop_streams(struct hdac_bus * bus)181 void snd_hdac_stop_streams(struct hdac_bus *bus)
182 {
183 	struct hdac_stream *stream;
184 
185 	list_for_each_entry(stream, &bus->stream_list, list)
186 		snd_hdac_stream_stop(stream);
187 }
188 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
189 
190 /**
191  * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
192  * @bus: HD-audio core bus
193  */
snd_hdac_stop_streams_and_chip(struct hdac_bus * bus)194 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
195 {
196 
197 	if (bus->chip_init) {
198 		snd_hdac_stop_streams(bus);
199 		snd_hdac_bus_stop_chip(bus);
200 	}
201 }
202 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
203 
204 /**
205  * snd_hdac_stream_reset - reset a stream
206  * @azx_dev: HD-audio core stream to reset
207  */
snd_hdac_stream_reset(struct hdac_stream * azx_dev)208 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
209 {
210 	unsigned char val;
211 	int dma_run_state;
212 
213 	snd_hdac_stream_clear(azx_dev);
214 
215 	dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
216 
217 	snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
218 
219 	/* wait for hardware to report that the stream entered reset */
220 	snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300);
221 
222 	if (azx_dev->bus->dma_stop_delay && dma_run_state)
223 		udelay(azx_dev->bus->dma_stop_delay);
224 
225 	snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0);
226 
227 	/* wait for hardware to report that the stream is out of reset */
228 	snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300);
229 
230 	/* reset first position - may not be synced with hw at this time */
231 	if (azx_dev->posbuf)
232 		*azx_dev->posbuf = 0;
233 }
234 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
235 
236 /**
237  * snd_hdac_stream_setup -  set up the SD for streaming
238  * @azx_dev: HD-audio core stream to set up
239  */
snd_hdac_stream_setup(struct hdac_stream * azx_dev)240 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
241 {
242 	struct hdac_bus *bus = azx_dev->bus;
243 	struct snd_pcm_runtime *runtime;
244 	unsigned int val;
245 
246 	if (azx_dev->substream)
247 		runtime = azx_dev->substream->runtime;
248 	else
249 		runtime = NULL;
250 	/* make sure the run bit is zero for SD */
251 	snd_hdac_stream_clear(azx_dev);
252 	/* program the stream_tag */
253 	val = snd_hdac_stream_readl(azx_dev, SD_CTL);
254 	val = (val & ~SD_CTL_STREAM_TAG_MASK) |
255 		(azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
256 	if (!bus->snoop)
257 		val |= SD_CTL_TRAFFIC_PRIO;
258 	snd_hdac_stream_writel(azx_dev, SD_CTL, val);
259 
260 	/* program the length of samples in cyclic buffer */
261 	snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
262 
263 	/* program the stream format */
264 	/* this value needs to be the same as the one programmed */
265 	snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
266 
267 	/* program the stream LVI (last valid index) of the BDL */
268 	snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
269 
270 	/* program the BDL address */
271 	/* lower BDL address */
272 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
273 	/* upper BDL address */
274 	snd_hdac_stream_writel(azx_dev, SD_BDLPU,
275 			       upper_32_bits(azx_dev->bdl.addr));
276 
277 	/* enable the position buffer */
278 	if (bus->use_posbuf && bus->posbuf.addr) {
279 		if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
280 			snd_hdac_chip_writel(bus, DPLBASE,
281 				(u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
282 	}
283 
284 	/* set the interrupt enable bits in the descriptor control register */
285 	snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
286 
287 	azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
288 
289 	/* when LPIB delay correction gives a small negative value,
290 	 * we ignore it; currently set the threshold statically to
291 	 * 64 frames
292 	 */
293 	if (runtime && runtime->period_size > 64)
294 		azx_dev->delay_negative_threshold =
295 			-frames_to_bytes(runtime, 64);
296 	else
297 		azx_dev->delay_negative_threshold = 0;
298 
299 	/* wallclk has 24Mhz clock source */
300 	if (runtime)
301 		azx_dev->period_wallclk = (((runtime->period_size * 24000) /
302 				    runtime->rate) * 1000);
303 
304 	return 0;
305 }
306 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
307 
308 /**
309  * snd_hdac_stream_cleanup - cleanup a stream
310  * @azx_dev: HD-audio core stream to clean up
311  */
snd_hdac_stream_cleanup(struct hdac_stream * azx_dev)312 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
313 {
314 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
315 	snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
316 	snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
317 	azx_dev->bufsize = 0;
318 	azx_dev->period_bytes = 0;
319 	azx_dev->format_val = 0;
320 }
321 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
322 
323 /**
324  * snd_hdac_stream_assign - assign a stream for the PCM
325  * @bus: HD-audio core bus
326  * @substream: PCM substream to assign
327  *
328  * Look for an unused stream for the given PCM substream, assign it
329  * and return the stream object.  If no stream is free, returns NULL.
330  * The function tries to keep using the same stream object when it's used
331  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
332  * or matching entry is returned.  This is needed for some strange codecs.
333  */
snd_hdac_stream_assign(struct hdac_bus * bus,struct snd_pcm_substream * substream)334 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
335 					   struct snd_pcm_substream *substream)
336 {
337 	struct hdac_stream *azx_dev;
338 	struct hdac_stream *res = NULL;
339 
340 	/* make a non-zero unique key for the substream */
341 	int key = (substream->pcm->device << 16) | (substream->number << 2) |
342 		(substream->stream + 1);
343 
344 	spin_lock_irq(&bus->reg_lock);
345 	list_for_each_entry(azx_dev, &bus->stream_list, list) {
346 		if (azx_dev->direction != substream->stream)
347 			continue;
348 		if (azx_dev->opened)
349 			continue;
350 		if (azx_dev->assigned_key == key) {
351 			res = azx_dev;
352 			break;
353 		}
354 		if (!res || bus->reverse_assign)
355 			res = azx_dev;
356 	}
357 	if (res) {
358 		res->opened = 1;
359 		res->running = 0;
360 		res->assigned_key = key;
361 		res->substream = substream;
362 	}
363 	spin_unlock_irq(&bus->reg_lock);
364 	return res;
365 }
366 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
367 
368 /**
369  * snd_hdac_stream_release_locked - release the assigned stream
370  * @azx_dev: HD-audio core stream to release
371  *
372  * Release the stream that has been assigned by snd_hdac_stream_assign().
373  * The bus->reg_lock needs to be taken at a higher level
374  */
snd_hdac_stream_release_locked(struct hdac_stream * azx_dev)375 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev)
376 {
377 	azx_dev->opened = 0;
378 	azx_dev->running = 0;
379 	azx_dev->substream = NULL;
380 }
381 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked);
382 
383 /**
384  * snd_hdac_stream_release - release the assigned stream
385  * @azx_dev: HD-audio core stream to release
386  *
387  * Release the stream that has been assigned by snd_hdac_stream_assign().
388  */
snd_hdac_stream_release(struct hdac_stream * azx_dev)389 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
390 {
391 	struct hdac_bus *bus = azx_dev->bus;
392 
393 	spin_lock_irq(&bus->reg_lock);
394 	snd_hdac_stream_release_locked(azx_dev);
395 	spin_unlock_irq(&bus->reg_lock);
396 }
397 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
398 
399 /**
400  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
401  * direction
402  *
403  * @bus: HD-audio core bus
404  * @dir: direction for the stream to be found
405  * @stream_tag: stream tag for stream to be found
406  */
snd_hdac_get_stream(struct hdac_bus * bus,int dir,int stream_tag)407 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
408 					int dir, int stream_tag)
409 {
410 	struct hdac_stream *s;
411 
412 	list_for_each_entry(s, &bus->stream_list, list) {
413 		if (s->direction == dir && s->stream_tag == stream_tag)
414 			return s;
415 	}
416 
417 	return NULL;
418 }
419 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
420 
421 /*
422  * set up a BDL entry
423  */
setup_bdle(struct hdac_bus * bus,struct snd_dma_buffer * dmab,struct hdac_stream * azx_dev,__le32 ** bdlp,int ofs,int size,int with_ioc)424 static int setup_bdle(struct hdac_bus *bus,
425 		      struct snd_dma_buffer *dmab,
426 		      struct hdac_stream *azx_dev, __le32 **bdlp,
427 		      int ofs, int size, int with_ioc)
428 {
429 	__le32 *bdl = *bdlp;
430 
431 	while (size > 0) {
432 		dma_addr_t addr;
433 		int chunk;
434 
435 		if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
436 			return -EINVAL;
437 
438 		addr = snd_sgbuf_get_addr(dmab, ofs);
439 		/* program the address field of the BDL entry */
440 		bdl[0] = cpu_to_le32((u32)addr);
441 		bdl[1] = cpu_to_le32(upper_32_bits(addr));
442 		/* program the size field of the BDL entry */
443 		chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
444 		/* one BDLE cannot cross 4K boundary on CTHDA chips */
445 		if (bus->align_bdle_4k) {
446 			u32 remain = 0x1000 - (ofs & 0xfff);
447 
448 			if (chunk > remain)
449 				chunk = remain;
450 		}
451 		bdl[2] = cpu_to_le32(chunk);
452 		/* program the IOC to enable interrupt
453 		 * only when the whole fragment is processed
454 		 */
455 		size -= chunk;
456 		bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
457 		bdl += 4;
458 		azx_dev->frags++;
459 		ofs += chunk;
460 	}
461 	*bdlp = bdl;
462 	return ofs;
463 }
464 
465 /**
466  * snd_hdac_stream_setup_periods - set up BDL entries
467  * @azx_dev: HD-audio core stream to set up
468  *
469  * Set up the buffer descriptor table of the given stream based on the
470  * period and buffer sizes of the assigned PCM substream.
471  */
snd_hdac_stream_setup_periods(struct hdac_stream * azx_dev)472 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
473 {
474 	struct hdac_bus *bus = azx_dev->bus;
475 	struct snd_pcm_substream *substream = azx_dev->substream;
476 	struct snd_pcm_runtime *runtime = substream->runtime;
477 	__le32 *bdl;
478 	int i, ofs, periods, period_bytes;
479 	int pos_adj, pos_align;
480 
481 	/* reset BDL address */
482 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
483 	snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
484 
485 	period_bytes = azx_dev->period_bytes;
486 	periods = azx_dev->bufsize / period_bytes;
487 
488 	/* program the initial BDL entries */
489 	bdl = (__le32 *)azx_dev->bdl.area;
490 	ofs = 0;
491 	azx_dev->frags = 0;
492 
493 	pos_adj = bus->bdl_pos_adj;
494 	if (!azx_dev->no_period_wakeup && pos_adj > 0) {
495 		pos_align = pos_adj;
496 		pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
497 		if (!pos_adj)
498 			pos_adj = pos_align;
499 		else
500 			pos_adj = roundup(pos_adj, pos_align);
501 		pos_adj = frames_to_bytes(runtime, pos_adj);
502 		if (pos_adj >= period_bytes) {
503 			dev_warn(bus->dev, "Too big adjustment %d\n",
504 				 pos_adj);
505 			pos_adj = 0;
506 		} else {
507 			ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
508 					 azx_dev,
509 					 &bdl, ofs, pos_adj, true);
510 			if (ofs < 0)
511 				goto error;
512 		}
513 	} else
514 		pos_adj = 0;
515 
516 	for (i = 0; i < periods; i++) {
517 		if (i == periods - 1 && pos_adj)
518 			ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
519 					 azx_dev, &bdl, ofs,
520 					 period_bytes - pos_adj, 0);
521 		else
522 			ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
523 					 azx_dev, &bdl, ofs,
524 					 period_bytes,
525 					 !azx_dev->no_period_wakeup);
526 		if (ofs < 0)
527 			goto error;
528 	}
529 	return 0;
530 
531  error:
532 	dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
533 		azx_dev->bufsize, period_bytes);
534 	return -EINVAL;
535 }
536 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
537 
538 /**
539  * snd_hdac_stream_set_params - set stream parameters
540  * @azx_dev: HD-audio core stream for which parameters are to be set
541  * @format_val: format value parameter
542  *
543  * Setup the HD-audio core stream parameters from substream of the stream
544  * and passed format value
545  */
snd_hdac_stream_set_params(struct hdac_stream * azx_dev,unsigned int format_val)546 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
547 				 unsigned int format_val)
548 {
549 
550 	unsigned int bufsize, period_bytes;
551 	struct snd_pcm_substream *substream = azx_dev->substream;
552 	struct snd_pcm_runtime *runtime;
553 	int err;
554 
555 	if (!substream)
556 		return -EINVAL;
557 	runtime = substream->runtime;
558 	bufsize = snd_pcm_lib_buffer_bytes(substream);
559 	period_bytes = snd_pcm_lib_period_bytes(substream);
560 
561 	if (bufsize != azx_dev->bufsize ||
562 	    period_bytes != azx_dev->period_bytes ||
563 	    format_val != azx_dev->format_val ||
564 	    runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
565 		azx_dev->bufsize = bufsize;
566 		azx_dev->period_bytes = period_bytes;
567 		azx_dev->format_val = format_val;
568 		azx_dev->no_period_wakeup = runtime->no_period_wakeup;
569 		err = snd_hdac_stream_setup_periods(azx_dev);
570 		if (err < 0)
571 			return err;
572 	}
573 	return 0;
574 }
575 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
576 
azx_cc_read(const struct cyclecounter * cc)577 static u64 azx_cc_read(const struct cyclecounter *cc)
578 {
579 	struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
580 
581 	return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
582 }
583 
azx_timecounter_init(struct hdac_stream * azx_dev,bool force,u64 last)584 static void azx_timecounter_init(struct hdac_stream *azx_dev,
585 				 bool force, u64 last)
586 {
587 	struct timecounter *tc = &azx_dev->tc;
588 	struct cyclecounter *cc = &azx_dev->cc;
589 	u64 nsec;
590 
591 	cc->read = azx_cc_read;
592 	cc->mask = CLOCKSOURCE_MASK(32);
593 
594 	/*
595 	 * Calculate the optimal mult/shift values. The counter wraps
596 	 * around after ~178.9 seconds.
597 	 */
598 	clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000,
599 			       NSEC_PER_SEC, 178);
600 
601 	nsec = 0; /* audio time is elapsed time since trigger */
602 	timecounter_init(tc, cc, nsec);
603 	if (force) {
604 		/*
605 		 * force timecounter to use predefined value,
606 		 * used for synchronized starts
607 		 */
608 		tc->cycle_last = last;
609 	}
610 }
611 
612 /**
613  * snd_hdac_stream_timecounter_init - initialize time counter
614  * @azx_dev: HD-audio core stream (master stream)
615  * @streams: bit flags of streams to set up
616  *
617  * Initializes the time counter of streams marked by the bit flags (each
618  * bit corresponds to the stream index).
619  * The trigger timestamp of PCM substream assigned to the given stream is
620  * updated accordingly, too.
621  */
snd_hdac_stream_timecounter_init(struct hdac_stream * azx_dev,unsigned int streams)622 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
623 				      unsigned int streams)
624 {
625 	struct hdac_bus *bus = azx_dev->bus;
626 	struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
627 	struct hdac_stream *s;
628 	bool inited = false;
629 	u64 cycle_last = 0;
630 	int i = 0;
631 
632 	list_for_each_entry(s, &bus->stream_list, list) {
633 		if (streams & (1 << i)) {
634 			azx_timecounter_init(s, inited, cycle_last);
635 			if (!inited) {
636 				inited = true;
637 				cycle_last = s->tc.cycle_last;
638 			}
639 		}
640 		i++;
641 	}
642 
643 	snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
644 	runtime->trigger_tstamp_latched = true;
645 }
646 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
647 
648 /**
649  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
650  * @azx_dev: HD-audio core stream (master stream)
651  * @set: true = set, false = clear
652  * @streams: bit flags of streams to sync
653  * @reg: the stream sync register address
654  */
snd_hdac_stream_sync_trigger(struct hdac_stream * azx_dev,bool set,unsigned int streams,unsigned int reg)655 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
656 				  unsigned int streams, unsigned int reg)
657 {
658 	struct hdac_bus *bus = azx_dev->bus;
659 	unsigned int val;
660 
661 	if (!reg)
662 		reg = AZX_REG_SSYNC;
663 	val = _snd_hdac_chip_readl(bus, reg);
664 	if (set)
665 		val |= streams;
666 	else
667 		val &= ~streams;
668 	_snd_hdac_chip_writel(bus, reg, val);
669 }
670 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
671 
672 /**
673  * snd_hdac_stream_sync - sync with start/stop trigger operation
674  * @azx_dev: HD-audio core stream (master stream)
675  * @start: true = start, false = stop
676  * @streams: bit flags of streams to sync
677  *
678  * For @start = true, wait until all FIFOs get ready.
679  * For @start = false, wait until all RUN bits are cleared.
680  */
snd_hdac_stream_sync(struct hdac_stream * azx_dev,bool start,unsigned int streams)681 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
682 			  unsigned int streams)
683 {
684 	struct hdac_bus *bus = azx_dev->bus;
685 	int i, nwait, timeout;
686 	struct hdac_stream *s;
687 
688 	for (timeout = 5000; timeout; timeout--) {
689 		nwait = 0;
690 		i = 0;
691 		list_for_each_entry(s, &bus->stream_list, list) {
692 			if (!(streams & (1 << i++)))
693 				continue;
694 
695 			if (start) {
696 				/* check FIFO gets ready */
697 				if (!(snd_hdac_stream_readb(s, SD_STS) &
698 				      SD_STS_FIFO_READY))
699 					nwait++;
700 			} else {
701 				/* check RUN bit is cleared */
702 				if (snd_hdac_stream_readb(s, SD_CTL) &
703 				    SD_CTL_DMA_START) {
704 					nwait++;
705 					/*
706 					 * Perform stream reset if DMA RUN
707 					 * bit not cleared within given timeout
708 					 */
709 					if (timeout == 1)
710 						snd_hdac_stream_reset(s);
711 				}
712 			}
713 		}
714 		if (!nwait)
715 			break;
716 		cpu_relax();
717 	}
718 }
719 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
720 
721 #ifdef CONFIG_SND_HDA_DSP_LOADER
722 /**
723  * snd_hdac_dsp_prepare - prepare for DSP loading
724  * @azx_dev: HD-audio core stream used for DSP loading
725  * @format: HD-audio stream format
726  * @byte_size: data chunk byte size
727  * @bufp: allocated buffer
728  *
729  * Allocate the buffer for the given size and set up the given stream for
730  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
731  */
snd_hdac_dsp_prepare(struct hdac_stream * azx_dev,unsigned int format,unsigned int byte_size,struct snd_dma_buffer * bufp)732 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
733 			 unsigned int byte_size, struct snd_dma_buffer *bufp)
734 {
735 	struct hdac_bus *bus = azx_dev->bus;
736 	__le32 *bdl;
737 	int err;
738 
739 	snd_hdac_dsp_lock(azx_dev);
740 	spin_lock_irq(&bus->reg_lock);
741 	if (azx_dev->running || azx_dev->locked) {
742 		spin_unlock_irq(&bus->reg_lock);
743 		err = -EBUSY;
744 		goto unlock;
745 	}
746 	azx_dev->locked = true;
747 	spin_unlock_irq(&bus->reg_lock);
748 
749 	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
750 				  byte_size, bufp);
751 	if (err < 0)
752 		goto err_alloc;
753 
754 	azx_dev->substream = NULL;
755 	azx_dev->bufsize = byte_size;
756 	azx_dev->period_bytes = byte_size;
757 	azx_dev->format_val = format;
758 
759 	snd_hdac_stream_reset(azx_dev);
760 
761 	/* reset BDL address */
762 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
763 	snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
764 
765 	azx_dev->frags = 0;
766 	bdl = (__le32 *)azx_dev->bdl.area;
767 	err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
768 	if (err < 0)
769 		goto error;
770 
771 	snd_hdac_stream_setup(azx_dev);
772 	snd_hdac_dsp_unlock(azx_dev);
773 	return azx_dev->stream_tag;
774 
775  error:
776 	snd_dma_free_pages(bufp);
777  err_alloc:
778 	spin_lock_irq(&bus->reg_lock);
779 	azx_dev->locked = false;
780 	spin_unlock_irq(&bus->reg_lock);
781  unlock:
782 	snd_hdac_dsp_unlock(azx_dev);
783 	return err;
784 }
785 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
786 
787 /**
788  * snd_hdac_dsp_trigger - start / stop DSP loading
789  * @azx_dev: HD-audio core stream used for DSP loading
790  * @start: trigger start or stop
791  */
snd_hdac_dsp_trigger(struct hdac_stream * azx_dev,bool start)792 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
793 {
794 	if (start)
795 		snd_hdac_stream_start(azx_dev, true);
796 	else
797 		snd_hdac_stream_stop(azx_dev);
798 }
799 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
800 
801 /**
802  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
803  * @azx_dev: HD-audio core stream used for DSP loading
804  * @dmab: buffer used by DSP loading
805  */
snd_hdac_dsp_cleanup(struct hdac_stream * azx_dev,struct snd_dma_buffer * dmab)806 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
807 			  struct snd_dma_buffer *dmab)
808 {
809 	struct hdac_bus *bus = azx_dev->bus;
810 
811 	if (!dmab->area || !azx_dev->locked)
812 		return;
813 
814 	snd_hdac_dsp_lock(azx_dev);
815 	/* reset BDL address */
816 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
817 	snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
818 	snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
819 	azx_dev->bufsize = 0;
820 	azx_dev->period_bytes = 0;
821 	azx_dev->format_val = 0;
822 
823 	snd_dma_free_pages(dmab);
824 	dmab->area = NULL;
825 
826 	spin_lock_irq(&bus->reg_lock);
827 	azx_dev->locked = false;
828 	spin_unlock_irq(&bus->reg_lock);
829 	snd_hdac_dsp_unlock(azx_dev);
830 }
831 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
832 #endif /* CONFIG_SND_HDA_DSP_LOADER */
833