1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *	pci.h
4  *
5  *	PCI defines and function prototypes
6  *	Copyright 1994, Drew Eckhardt
7  *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8  *
9  *	PCI Express ASPM defines and function prototypes
10  *	Copyright (c) 2007 Intel Corp.
11  *		Zhang Yanmin (yanmin.zhang@intel.com)
12  *		Shaohua Li (shaohua.li@intel.com)
13  *
14  *	For more information, please consult the following manuals (look at
15  *	http://www.pcisig.com/ for how to get them):
16  *
17  *	PCI BIOS Specification
18  *	PCI Local Bus Specification
19  *	PCI to PCI Bridge Specification
20  *	PCI Express Specification
21  *	PCI System Design Guide
22  */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25 
26 
27 #include <linux/mod_devicetable.h>
28 
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
42 
43 #include <linux/pci_ids.h>
44 
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY  | \
46 			       PCI_STATUS_SIG_SYSTEM_ERROR | \
47 			       PCI_STATUS_REC_MASTER_ABORT | \
48 			       PCI_STATUS_REC_TARGET_ABORT | \
49 			       PCI_STATUS_SIG_TARGET_ABORT | \
50 			       PCI_STATUS_PARITY)
51 
52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
53 #define PCI_NUM_RESET_METHODS 7
54 
55 #define PCI_RESET_PROBE		true
56 #define PCI_RESET_DO_RESET	false
57 
58 /*
59  * The PCI interface treats multi-function devices as independent
60  * devices.  The slot/function address of each device is encoded
61  * in a single byte as follows:
62  *
63  *	7:3 = slot
64  *	2:0 = function
65  *
66  * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
67  * In the interest of not exposing interfaces to user-space unnecessarily,
68  * the following kernel-only defines are being added here.
69  */
70 #define PCI_DEVID(bus, devfn)	((((u16)(bus)) << 8) | (devfn))
71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
73 
74 /* pci_slot represents a physical slot */
75 struct pci_slot {
76 	struct pci_bus		*bus;		/* Bus this slot is on */
77 	struct list_head	list;		/* Node in list of slots */
78 	struct hotplug_slot	*hotplug;	/* Hotplug info (move here) */
79 	unsigned char		number;		/* PCI_SLOT(pci_dev->devfn) */
80 	struct kobject		kobj;
81 };
82 
pci_slot_name(const struct pci_slot * slot)83 static inline const char *pci_slot_name(const struct pci_slot *slot)
84 {
85 	return kobject_name(&slot->kobj);
86 }
87 
88 /* File state for mmap()s on /proc/bus/pci/X/Y */
89 enum pci_mmap_state {
90 	pci_mmap_io,
91 	pci_mmap_mem
92 };
93 
94 /* For PCI devices, the region numbers are assigned this way: */
95 enum {
96 	/* #0-5: standard PCI resources */
97 	PCI_STD_RESOURCES,
98 	PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
99 
100 	/* #6: expansion ROM resource */
101 	PCI_ROM_RESOURCE,
102 
103 	/* Device-specific resources */
104 #ifdef CONFIG_PCI_IOV
105 	PCI_IOV_RESOURCES,
106 	PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
107 #endif
108 
109 /* PCI-to-PCI (P2P) bridge windows */
110 #define PCI_BRIDGE_IO_WINDOW		(PCI_BRIDGE_RESOURCES + 0)
111 #define PCI_BRIDGE_MEM_WINDOW		(PCI_BRIDGE_RESOURCES + 1)
112 #define PCI_BRIDGE_PREF_MEM_WINDOW	(PCI_BRIDGE_RESOURCES + 2)
113 
114 /* CardBus bridge windows */
115 #define PCI_CB_BRIDGE_IO_0_WINDOW	(PCI_BRIDGE_RESOURCES + 0)
116 #define PCI_CB_BRIDGE_IO_1_WINDOW	(PCI_BRIDGE_RESOURCES + 1)
117 #define PCI_CB_BRIDGE_MEM_0_WINDOW	(PCI_BRIDGE_RESOURCES + 2)
118 #define PCI_CB_BRIDGE_MEM_1_WINDOW	(PCI_BRIDGE_RESOURCES + 3)
119 
120 /* Total number of bridge resources for P2P and CardBus */
121 #define PCI_BRIDGE_RESOURCE_NUM 4
122 
123 	/* Resources assigned to buses behind the bridge */
124 	PCI_BRIDGE_RESOURCES,
125 	PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
126 				  PCI_BRIDGE_RESOURCE_NUM - 1,
127 
128 	/* Total resources associated with a PCI device */
129 	PCI_NUM_RESOURCES,
130 
131 	/* Preserve this for compatibility */
132 	DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
133 };
134 
135 /**
136  * enum pci_interrupt_pin - PCI INTx interrupt values
137  * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
138  * @PCI_INTERRUPT_INTA: PCI INTA pin
139  * @PCI_INTERRUPT_INTB: PCI INTB pin
140  * @PCI_INTERRUPT_INTC: PCI INTC pin
141  * @PCI_INTERRUPT_INTD: PCI INTD pin
142  *
143  * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
144  * PCI_INTERRUPT_PIN register.
145  */
146 enum pci_interrupt_pin {
147 	PCI_INTERRUPT_UNKNOWN,
148 	PCI_INTERRUPT_INTA,
149 	PCI_INTERRUPT_INTB,
150 	PCI_INTERRUPT_INTC,
151 	PCI_INTERRUPT_INTD,
152 };
153 
154 /* The number of legacy PCI INTx interrupts */
155 #define PCI_NUM_INTX	4
156 
157 /*
158  * Reading from a device that doesn't respond typically returns ~0.  A
159  * successful read from a device may also return ~0, so you need additional
160  * information to reliably identify errors.
161  */
162 #define PCI_ERROR_RESPONSE		(~0ULL)
163 #define PCI_SET_ERROR_RESPONSE(val)	(*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
164 #define PCI_POSSIBLE_ERROR(val)		((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
165 
166 /*
167  * pci_power_t values must match the bits in the Capabilities PME_Support
168  * and Control/Status PowerState fields in the Power Management capability.
169  */
170 typedef int __bitwise pci_power_t;
171 
172 #define PCI_D0		((pci_power_t __force) 0)
173 #define PCI_D1		((pci_power_t __force) 1)
174 #define PCI_D2		((pci_power_t __force) 2)
175 #define PCI_D3hot	((pci_power_t __force) 3)
176 #define PCI_D3cold	((pci_power_t __force) 4)
177 #define PCI_UNKNOWN	((pci_power_t __force) 5)
178 #define PCI_POWER_ERROR	((pci_power_t __force) -1)
179 
180 /* Remember to update this when the list above changes! */
181 extern const char *pci_power_names[];
182 
pci_power_name(pci_power_t state)183 static inline const char *pci_power_name(pci_power_t state)
184 {
185 	return pci_power_names[1 + (__force int) state];
186 }
187 
188 /**
189  * typedef pci_channel_state_t
190  *
191  * The pci_channel state describes connectivity between the CPU and
192  * the PCI device.  If some PCI bus between here and the PCI device
193  * has crashed or locked up, this info is reflected here.
194  */
195 typedef unsigned int __bitwise pci_channel_state_t;
196 
197 enum {
198 	/* I/O channel is in normal state */
199 	pci_channel_io_normal = (__force pci_channel_state_t) 1,
200 
201 	/* I/O to channel is blocked */
202 	pci_channel_io_frozen = (__force pci_channel_state_t) 2,
203 
204 	/* PCI card is dead */
205 	pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
206 };
207 
208 typedef unsigned int __bitwise pcie_reset_state_t;
209 
210 enum pcie_reset_state {
211 	/* Reset is NOT asserted (Use to deassert reset) */
212 	pcie_deassert_reset = (__force pcie_reset_state_t) 1,
213 
214 	/* Use #PERST to reset PCIe device */
215 	pcie_warm_reset = (__force pcie_reset_state_t) 2,
216 
217 	/* Use PCIe Hot Reset to reset device */
218 	pcie_hot_reset = (__force pcie_reset_state_t) 3
219 };
220 
221 typedef unsigned short __bitwise pci_dev_flags_t;
222 enum pci_dev_flags {
223 	/* INTX_DISABLE in PCI_COMMAND register disables MSI too */
224 	PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
225 	/* Device configuration is irrevocably lost if disabled into D3 */
226 	PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
227 	/* Provide indication device is assigned by a Virtual Machine Manager */
228 	PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
229 	/* Flag for quirk use to store if quirk-specific ACS is enabled */
230 	PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
231 	/* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
232 	PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
233 	/* Do not use bus resets for device */
234 	PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
235 	/* Do not use PM reset even if device advertises NoSoftRst- */
236 	PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
237 	/* Get VPD from function 0 VPD */
238 	PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
239 	/* A non-root bridge where translation occurs, stop alias search here */
240 	PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
241 	/* Do not use FLR even if device advertises PCI_AF_CAP */
242 	PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
243 	/* Don't use Relaxed Ordering for TLPs directed at this device */
244 	PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
245 	/* Device does honor MSI masking despite saying otherwise */
246 	PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
247 };
248 
249 enum pci_irq_reroute_variant {
250 	INTEL_IRQ_REROUTE_VARIANT = 1,
251 	MAX_IRQ_REROUTE_VARIANTS = 3
252 };
253 
254 typedef unsigned short __bitwise pci_bus_flags_t;
255 enum pci_bus_flags {
256 	PCI_BUS_FLAGS_NO_MSI	= (__force pci_bus_flags_t) 1,
257 	PCI_BUS_FLAGS_NO_MMRBC	= (__force pci_bus_flags_t) 2,
258 	PCI_BUS_FLAGS_NO_AERSID	= (__force pci_bus_flags_t) 4,
259 	PCI_BUS_FLAGS_NO_EXTCFG	= (__force pci_bus_flags_t) 8,
260 };
261 
262 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
263 enum pcie_link_width {
264 	PCIE_LNK_WIDTH_RESRV	= 0x00,
265 	PCIE_LNK_X1		= 0x01,
266 	PCIE_LNK_X2		= 0x02,
267 	PCIE_LNK_X4		= 0x04,
268 	PCIE_LNK_X8		= 0x08,
269 	PCIE_LNK_X12		= 0x0c,
270 	PCIE_LNK_X16		= 0x10,
271 	PCIE_LNK_X32		= 0x20,
272 	PCIE_LNK_WIDTH_UNKNOWN	= 0xff,
273 };
274 
275 /* See matching string table in pci_speed_string() */
276 enum pci_bus_speed {
277 	PCI_SPEED_33MHz			= 0x00,
278 	PCI_SPEED_66MHz			= 0x01,
279 	PCI_SPEED_66MHz_PCIX		= 0x02,
280 	PCI_SPEED_100MHz_PCIX		= 0x03,
281 	PCI_SPEED_133MHz_PCIX		= 0x04,
282 	PCI_SPEED_66MHz_PCIX_ECC	= 0x05,
283 	PCI_SPEED_100MHz_PCIX_ECC	= 0x06,
284 	PCI_SPEED_133MHz_PCIX_ECC	= 0x07,
285 	PCI_SPEED_66MHz_PCIX_266	= 0x09,
286 	PCI_SPEED_100MHz_PCIX_266	= 0x0a,
287 	PCI_SPEED_133MHz_PCIX_266	= 0x0b,
288 	AGP_UNKNOWN			= 0x0c,
289 	AGP_1X				= 0x0d,
290 	AGP_2X				= 0x0e,
291 	AGP_4X				= 0x0f,
292 	AGP_8X				= 0x10,
293 	PCI_SPEED_66MHz_PCIX_533	= 0x11,
294 	PCI_SPEED_100MHz_PCIX_533	= 0x12,
295 	PCI_SPEED_133MHz_PCIX_533	= 0x13,
296 	PCIE_SPEED_2_5GT		= 0x14,
297 	PCIE_SPEED_5_0GT		= 0x15,
298 	PCIE_SPEED_8_0GT		= 0x16,
299 	PCIE_SPEED_16_0GT		= 0x17,
300 	PCIE_SPEED_32_0GT		= 0x18,
301 	PCIE_SPEED_64_0GT		= 0x19,
302 	PCI_SPEED_UNKNOWN		= 0xff,
303 };
304 
305 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
306 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
307 
308 struct pci_vpd {
309 	struct mutex	lock;
310 	unsigned int	len;
311 	u8		cap;
312 };
313 
314 struct irq_affinity;
315 struct pcie_link_state;
316 struct pci_sriov;
317 struct pci_p2pdma;
318 struct rcec_ea;
319 
320 /* The pci_dev structure describes PCI devices */
321 struct pci_dev {
322 	struct list_head bus_list;	/* Node in per-bus list */
323 	struct pci_bus	*bus;		/* Bus this device is on */
324 	struct pci_bus	*subordinate;	/* Bus this device bridges to */
325 
326 	void		*sysdata;	/* Hook for sys-specific extension */
327 	struct proc_dir_entry *procent;	/* Device entry in /proc/bus/pci */
328 	struct pci_slot	*slot;		/* Physical slot this device is in */
329 
330 	unsigned int	devfn;		/* Encoded device & function index */
331 	unsigned short	vendor;
332 	unsigned short	device;
333 	unsigned short	subsystem_vendor;
334 	unsigned short	subsystem_device;
335 	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */
336 	u8		revision;	/* PCI revision, low byte of class word */
337 	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
338 #ifdef CONFIG_PCIEAER
339 	u16		aer_cap;	/* AER capability offset */
340 	struct aer_stats *aer_stats;	/* AER stats for this device */
341 #endif
342 #ifdef CONFIG_PCIEPORTBUS
343 	struct rcec_ea	*rcec_ea;	/* RCEC cached endpoint association */
344 	struct pci_dev  *rcec;          /* Associated RCEC device */
345 #endif
346 	u32		devcap;		/* PCIe Device Capabilities */
347 	u8		pcie_cap;	/* PCIe capability offset */
348 	u8		msi_cap;	/* MSI capability offset */
349 	u8		msix_cap;	/* MSI-X capability offset */
350 	u8		pcie_mpss:3;	/* PCIe Max Payload Size Supported */
351 	u8		rom_base_reg;	/* Config register controlling ROM */
352 	u8		pin;		/* Interrupt pin this device uses */
353 	u16		pcie_flags_reg;	/* Cached PCIe Capabilities Register */
354 	unsigned long	*dma_alias_mask;/* Mask of enabled devfn aliases */
355 
356 	struct pci_driver *driver;	/* Driver bound to this device */
357 	u64		dma_mask;	/* Mask of the bits of bus address this
358 					   device implements.  Normally this is
359 					   0xffffffff.  You only need to change
360 					   this if your device has broken DMA
361 					   or supports 64-bit transfers.  */
362 
363 	struct device_dma_parameters dma_parms;
364 
365 	pci_power_t	current_state;	/* Current operating state. In ACPI,
366 					   this is D0-D3, D0 being fully
367 					   functional, and D3 being off. */
368 	unsigned int	imm_ready:1;	/* Supports Immediate Readiness */
369 	u8		pm_cap;		/* PM capability offset */
370 	unsigned int	pme_support:5;	/* Bitmask of states from which PME#
371 					   can be generated */
372 	unsigned int	pme_poll:1;	/* Poll device's PME status bit */
373 	unsigned int	d1_support:1;	/* Low power state D1 is supported */
374 	unsigned int	d2_support:1;	/* Low power state D2 is supported */
375 	unsigned int	no_d1d2:1;	/* D1 and D2 are forbidden */
376 	unsigned int	no_d3cold:1;	/* D3cold is forbidden */
377 	unsigned int	bridge_d3:1;	/* Allow D3 for bridge */
378 	unsigned int	d3cold_allowed:1;	/* D3cold is allowed by user */
379 	unsigned int	mmio_always_on:1;	/* Disallow turning off io/mem
380 						   decoding during BAR sizing */
381 	unsigned int	wakeup_prepared:1;
382 	unsigned int	skip_bus_pm:1;	/* Internal: Skip bus-level PM */
383 	unsigned int	ignore_hotplug:1;	/* Ignore hotplug events */
384 	unsigned int	hotplug_user_indicators:1; /* SlotCtl indicators
385 						      controlled exclusively by
386 						      user sysfs */
387 	unsigned int	clear_retrain_link:1;	/* Need to clear Retrain Link
388 						   bit manually */
389 	unsigned int	d3hot_delay;	/* D3hot->D0 transition time in ms */
390 	unsigned int	d3cold_delay;	/* D3cold->D0 transition time in ms */
391 
392 #ifdef CONFIG_PCIEASPM
393 	struct pcie_link_state	*link_state;	/* ASPM link state */
394 	unsigned int	ltr_path:1;	/* Latency Tolerance Reporting
395 					   supported from root to here */
396 	u16		l1ss;		/* L1SS Capability pointer */
397 #endif
398 	unsigned int	pasid_no_tlp:1;		/* PASID works without TLP Prefix */
399 	unsigned int	eetlp_prefix_path:1;	/* End-to-End TLP Prefix */
400 
401 	pci_channel_state_t error_state;	/* Current connectivity state */
402 	struct device	dev;			/* Generic device interface */
403 
404 	int		cfg_size;		/* Size of config space */
405 
406 	/*
407 	 * Instead of touching interrupt line and base address registers
408 	 * directly, use the values stored here. They might be different!
409 	 */
410 	unsigned int	irq;
411 	struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
412 
413 	bool		match_driver;		/* Skip attaching driver */
414 
415 	unsigned int	transparent:1;		/* Subtractive decode bridge */
416 	unsigned int	io_window:1;		/* Bridge has I/O window */
417 	unsigned int	pref_window:1;		/* Bridge has pref mem window */
418 	unsigned int	pref_64_window:1;	/* Pref mem window is 64-bit */
419 	unsigned int	multifunction:1;	/* Multi-function device */
420 
421 	unsigned int	is_busmaster:1;		/* Is busmaster */
422 	unsigned int	no_msi:1;		/* May not use MSI */
423 	unsigned int	no_64bit_msi:1;		/* May only use 32-bit MSIs */
424 	unsigned int	block_cfg_access:1;	/* Config space access blocked */
425 	unsigned int	broken_parity_status:1;	/* Generates false positive parity */
426 	unsigned int	irq_reroute_variant:2;	/* Needs IRQ rerouting variant */
427 	unsigned int	msi_enabled:1;
428 	unsigned int	msix_enabled:1;
429 	unsigned int	ari_enabled:1;		/* ARI forwarding */
430 	unsigned int	ats_enabled:1;		/* Address Translation Svc */
431 	unsigned int	pasid_enabled:1;	/* Process Address Space ID */
432 	unsigned int	pri_enabled:1;		/* Page Request Interface */
433 	unsigned int	is_managed:1;		/* Managed via devres */
434 	unsigned int	is_msi_managed:1;	/* MSI release via devres installed */
435 	unsigned int	needs_freset:1;		/* Requires fundamental reset */
436 	unsigned int	state_saved:1;
437 	unsigned int	is_physfn:1;
438 	unsigned int	is_virtfn:1;
439 	unsigned int	is_hotplug_bridge:1;
440 	unsigned int	shpc_managed:1;		/* SHPC owned by shpchp */
441 	unsigned int	is_thunderbolt:1;	/* Thunderbolt controller */
442 	/*
443 	 * Devices marked being untrusted are the ones that can potentially
444 	 * execute DMA attacks and similar. They are typically connected
445 	 * through external ports such as Thunderbolt but not limited to
446 	 * that. When an IOMMU is enabled they should be getting full
447 	 * mappings to make sure they cannot access arbitrary memory.
448 	 */
449 	unsigned int	untrusted:1;
450 	/*
451 	 * Info from the platform, e.g., ACPI or device tree, may mark a
452 	 * device as "external-facing".  An external-facing device is
453 	 * itself internal but devices downstream from it are external.
454 	 */
455 	unsigned int	external_facing:1;
456 	unsigned int	broken_intx_masking:1;	/* INTx masking can't be used */
457 	unsigned int	io_window_1k:1;		/* Intel bridge 1K I/O windows */
458 	unsigned int	irq_managed:1;
459 	unsigned int	non_compliant_bars:1;	/* Broken BARs; ignore them */
460 	unsigned int	is_probed:1;		/* Device probing in progress */
461 	unsigned int	link_active_reporting:1;/* Device capable of reporting link active */
462 	unsigned int	no_vf_scan:1;		/* Don't scan for VFs after IOV enablement */
463 	unsigned int	no_command_memory:1;	/* No PCI_COMMAND_MEMORY */
464 	unsigned int	rom_bar_overlap:1;	/* ROM BAR disable broken */
465 	pci_dev_flags_t dev_flags;
466 	atomic_t	enable_cnt;	/* pci_enable_device has been called */
467 
468 	u32		saved_config_space[16]; /* Config space saved at suspend time */
469 	struct hlist_head saved_cap_space;
470 	int		rom_attr_enabled;	/* Display of ROM attribute enabled? */
471 	struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
472 	struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
473 
474 #ifdef CONFIG_HOTPLUG_PCI_PCIE
475 	unsigned int	broken_cmd_compl:1;	/* No compl for some cmds */
476 #endif
477 #ifdef CONFIG_PCIE_PTM
478 	u16		ptm_cap;		/* PTM Capability */
479 	unsigned int	ptm_root:1;
480 	unsigned int	ptm_enabled:1;
481 	u8		ptm_granularity;
482 #endif
483 #ifdef CONFIG_PCI_MSI
484 	void __iomem	*msix_base;
485 	raw_spinlock_t	msi_lock;
486 #endif
487 	struct pci_vpd	vpd;
488 #ifdef CONFIG_PCIE_DPC
489 	u16		dpc_cap;
490 	unsigned int	dpc_rp_extensions:1;
491 	u8		dpc_rp_log_size;
492 #endif
493 #ifdef CONFIG_PCI_ATS
494 	union {
495 		struct pci_sriov	*sriov;		/* PF: SR-IOV info */
496 		struct pci_dev		*physfn;	/* VF: related PF */
497 	};
498 	u16		ats_cap;	/* ATS Capability offset */
499 	u8		ats_stu;	/* ATS Smallest Translation Unit */
500 #endif
501 #ifdef CONFIG_PCI_PRI
502 	u16		pri_cap;	/* PRI Capability offset */
503 	u32		pri_reqs_alloc; /* Number of PRI requests allocated */
504 	unsigned int	pasid_required:1; /* PRG Response PASID Required */
505 #endif
506 #ifdef CONFIG_PCI_PASID
507 	u16		pasid_cap;	/* PASID Capability offset */
508 	u16		pasid_features;
509 #endif
510 #ifdef CONFIG_PCI_P2PDMA
511 	struct pci_p2pdma __rcu *p2pdma;
512 #endif
513 	u16		acs_cap;	/* ACS Capability offset */
514 	phys_addr_t	rom;		/* Physical address if not from BAR */
515 	size_t		romlen;		/* Length if not from BAR */
516 	/*
517 	 * Driver name to force a match.  Do not set directly, because core
518 	 * frees it.  Use driver_set_override() to set or clear it.
519 	 */
520 	const char	*driver_override;
521 
522 	unsigned long	priv_flags;	/* Private flags for the PCI driver */
523 
524 	/* These methods index pci_reset_fn_methods[] */
525 	u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
526 };
527 
pci_physfn(struct pci_dev * dev)528 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
529 {
530 #ifdef CONFIG_PCI_IOV
531 	if (dev->is_virtfn)
532 		dev = dev->physfn;
533 #endif
534 	return dev;
535 }
536 
537 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
538 
539 #define	to_pci_dev(n) container_of(n, struct pci_dev, dev)
540 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
541 
pci_channel_offline(struct pci_dev * pdev)542 static inline int pci_channel_offline(struct pci_dev *pdev)
543 {
544 	return (pdev->error_state != pci_channel_io_normal);
545 }
546 
547 /*
548  * Currently in ACPI spec, for each PCI host bridge, PCI Segment
549  * Group number is limited to a 16-bit value, therefore (int)-1 is
550  * not a valid PCI domain number, and can be used as a sentinel
551  * value indicating ->domain_nr is not set by the driver (and
552  * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
553  * pci_bus_find_domain_nr()).
554  */
555 #define PCI_DOMAIN_NR_NOT_SET (-1)
556 
557 struct pci_host_bridge {
558 	struct device	dev;
559 	struct pci_bus	*bus;		/* Root bus */
560 	struct pci_ops	*ops;
561 	struct pci_ops	*child_ops;
562 	void		*sysdata;
563 	int		busnr;
564 	int		domain_nr;
565 	struct list_head windows;	/* resource_entry */
566 	struct list_head dma_ranges;	/* dma ranges resource list */
567 	u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
568 	int (*map_irq)(const struct pci_dev *, u8, u8);
569 	void (*release_fn)(struct pci_host_bridge *);
570 	void		*release_data;
571 	unsigned int	ignore_reset_delay:1;	/* For entire hierarchy */
572 	unsigned int	no_ext_tags:1;		/* No Extended Tags */
573 	unsigned int	native_aer:1;		/* OS may use PCIe AER */
574 	unsigned int	native_pcie_hotplug:1;	/* OS may use PCIe hotplug */
575 	unsigned int	native_shpc_hotplug:1;	/* OS may use SHPC hotplug */
576 	unsigned int	native_pme:1;		/* OS may use PCIe PME */
577 	unsigned int	native_ltr:1;		/* OS may use PCIe LTR */
578 	unsigned int	native_dpc:1;		/* OS may use PCIe DPC */
579 	unsigned int	preserve_config:1;	/* Preserve FW resource setup */
580 	unsigned int	size_windows:1;		/* Enable root bus sizing */
581 	unsigned int	msi_domain:1;		/* Bridge wants MSI domain */
582 
583 	/* Resource alignment requirements */
584 	resource_size_t (*align_resource)(struct pci_dev *dev,
585 			const struct resource *res,
586 			resource_size_t start,
587 			resource_size_t size,
588 			resource_size_t align);
589 	unsigned long	private[] ____cacheline_aligned;
590 };
591 
592 #define	to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
593 
pci_host_bridge_priv(struct pci_host_bridge * bridge)594 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
595 {
596 	return (void *)bridge->private;
597 }
598 
pci_host_bridge_from_priv(void * priv)599 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
600 {
601 	return container_of(priv, struct pci_host_bridge, private);
602 }
603 
604 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
605 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
606 						   size_t priv);
607 void pci_free_host_bridge(struct pci_host_bridge *bridge);
608 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
609 
610 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
611 				 void (*release_fn)(struct pci_host_bridge *),
612 				 void *release_data);
613 
614 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
615 
616 /*
617  * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
618  * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
619  * buses below host bridges or subtractive decode bridges) go in the list.
620  * Use pci_bus_for_each_resource() to iterate through all the resources.
621  */
622 
623 /*
624  * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
625  * and there's no way to program the bridge with the details of the window.
626  * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
627  * decode bit set, because they are explicit and can be programmed with _SRS.
628  */
629 #define PCI_SUBTRACTIVE_DECODE	0x1
630 
631 struct pci_bus_resource {
632 	struct list_head	list;
633 	struct resource		*res;
634 	unsigned int		flags;
635 };
636 
637 #define PCI_REGION_FLAG_MASK	0x0fU	/* These bits of resource flags tell us the PCI region flags */
638 
639 struct pci_bus {
640 	struct list_head node;		/* Node in list of buses */
641 	struct pci_bus	*parent;	/* Parent bus this bridge is on */
642 	struct list_head children;	/* List of child buses */
643 	struct list_head devices;	/* List of devices on this bus */
644 	struct pci_dev	*self;		/* Bridge device as seen by parent */
645 	struct list_head slots;		/* List of slots on this bus;
646 					   protected by pci_slot_mutex */
647 	struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
648 	struct list_head resources;	/* Address space routed to this bus */
649 	struct resource busn_res;	/* Bus numbers routed to this bus */
650 
651 	struct pci_ops	*ops;		/* Configuration access functions */
652 	void		*sysdata;	/* Hook for sys-specific extension */
653 	struct proc_dir_entry *procdir;	/* Directory entry in /proc/bus/pci */
654 
655 	unsigned char	number;		/* Bus number */
656 	unsigned char	primary;	/* Number of primary bridge */
657 	unsigned char	max_bus_speed;	/* enum pci_bus_speed */
658 	unsigned char	cur_bus_speed;	/* enum pci_bus_speed */
659 #ifdef CONFIG_PCI_DOMAINS_GENERIC
660 	int		domain_nr;
661 #endif
662 
663 	char		name[48];
664 
665 	unsigned short	bridge_ctl;	/* Manage NO_ISA/FBB/et al behaviors */
666 	pci_bus_flags_t bus_flags;	/* Inherited by child buses */
667 	struct device		*bridge;
668 	struct device		dev;
669 	struct bin_attribute	*legacy_io;	/* Legacy I/O for this bus */
670 	struct bin_attribute	*legacy_mem;	/* Legacy mem */
671 	unsigned int		is_added:1;
672 	unsigned int		unsafe_warn:1;	/* warned about RW1C config write */
673 };
674 
675 #define to_pci_bus(n)	container_of(n, struct pci_bus, dev)
676 
pci_dev_id(struct pci_dev * dev)677 static inline u16 pci_dev_id(struct pci_dev *dev)
678 {
679 	return PCI_DEVID(dev->bus->number, dev->devfn);
680 }
681 
682 /*
683  * Returns true if the PCI bus is root (behind host-PCI bridge),
684  * false otherwise
685  *
686  * Some code assumes that "bus->self == NULL" means that bus is a root bus.
687  * This is incorrect because "virtual" buses added for SR-IOV (via
688  * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
689  */
pci_is_root_bus(struct pci_bus * pbus)690 static inline bool pci_is_root_bus(struct pci_bus *pbus)
691 {
692 	return !(pbus->parent);
693 }
694 
695 /**
696  * pci_is_bridge - check if the PCI device is a bridge
697  * @dev: PCI device
698  *
699  * Return true if the PCI device is bridge whether it has subordinate
700  * or not.
701  */
pci_is_bridge(struct pci_dev * dev)702 static inline bool pci_is_bridge(struct pci_dev *dev)
703 {
704 	return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
705 		dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
706 }
707 
708 #define for_each_pci_bridge(dev, bus)				\
709 	list_for_each_entry(dev, &bus->devices, bus_list)	\
710 		if (!pci_is_bridge(dev)) {} else
711 
pci_upstream_bridge(struct pci_dev * dev)712 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
713 {
714 	dev = pci_physfn(dev);
715 	if (pci_is_root_bus(dev->bus))
716 		return NULL;
717 
718 	return dev->bus->self;
719 }
720 
721 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)722 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
723 {
724 	return pci_dev->msi_enabled || pci_dev->msix_enabled;
725 }
726 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)727 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
728 #endif
729 
730 /* Error values that may be returned by PCI functions */
731 #define PCIBIOS_SUCCESSFUL		0x00
732 #define PCIBIOS_FUNC_NOT_SUPPORTED	0x81
733 #define PCIBIOS_BAD_VENDOR_ID		0x83
734 #define PCIBIOS_DEVICE_NOT_FOUND	0x86
735 #define PCIBIOS_BAD_REGISTER_NUMBER	0x87
736 #define PCIBIOS_SET_FAILED		0x88
737 #define PCIBIOS_BUFFER_TOO_SMALL	0x89
738 
739 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)740 static inline int pcibios_err_to_errno(int err)
741 {
742 	if (err <= PCIBIOS_SUCCESSFUL)
743 		return err; /* Assume already errno */
744 
745 	switch (err) {
746 	case PCIBIOS_FUNC_NOT_SUPPORTED:
747 		return -ENOENT;
748 	case PCIBIOS_BAD_VENDOR_ID:
749 		return -ENOTTY;
750 	case PCIBIOS_DEVICE_NOT_FOUND:
751 		return -ENODEV;
752 	case PCIBIOS_BAD_REGISTER_NUMBER:
753 		return -EFAULT;
754 	case PCIBIOS_SET_FAILED:
755 		return -EIO;
756 	case PCIBIOS_BUFFER_TOO_SMALL:
757 		return -ENOSPC;
758 	}
759 
760 	return -ERANGE;
761 }
762 
763 /* Low-level architecture-dependent routines */
764 
765 struct pci_ops {
766 	int (*add_bus)(struct pci_bus *bus);
767 	void (*remove_bus)(struct pci_bus *bus);
768 	void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
769 	int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
770 	int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
771 };
772 
773 /*
774  * ACPI needs to be able to access PCI config space before we've done a
775  * PCI bus scan and created pci_bus structures.
776  */
777 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
778 		 int reg, int len, u32 *val);
779 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
780 		  int reg, int len, u32 val);
781 
782 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
783 typedef u64 pci_bus_addr_t;
784 #else
785 typedef u32 pci_bus_addr_t;
786 #endif
787 
788 struct pci_bus_region {
789 	pci_bus_addr_t	start;
790 	pci_bus_addr_t	end;
791 };
792 
793 struct pci_dynids {
794 	spinlock_t		lock;	/* Protects list, index */
795 	struct list_head	list;	/* For IDs added at runtime */
796 };
797 
798 
799 /*
800  * PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
801  * a set of callbacks in struct pci_error_handlers, that device driver
802  * will be notified of PCI bus errors, and will be driven to recovery
803  * when an error occurs.
804  */
805 
806 typedef unsigned int __bitwise pci_ers_result_t;
807 
808 enum pci_ers_result {
809 	/* No result/none/not supported in device driver */
810 	PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
811 
812 	/* Device driver can recover without slot reset */
813 	PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
814 
815 	/* Device driver wants slot to be reset */
816 	PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
817 
818 	/* Device has completely failed, is unrecoverable */
819 	PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
820 
821 	/* Device driver is fully recovered and operational */
822 	PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
823 
824 	/* No AER capabilities registered for the driver */
825 	PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
826 };
827 
828 /* PCI bus error event callbacks */
829 struct pci_error_handlers {
830 	/* PCI bus error detected on this device */
831 	pci_ers_result_t (*error_detected)(struct pci_dev *dev,
832 					   pci_channel_state_t error);
833 
834 	/* MMIO has been re-enabled, but not DMA */
835 	pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
836 
837 	/* PCI slot has been reset */
838 	pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
839 
840 	/* PCI function reset prepare or completed */
841 	void (*reset_prepare)(struct pci_dev *dev);
842 	void (*reset_done)(struct pci_dev *dev);
843 
844 	/* Device driver may resume normal operations */
845 	void (*resume)(struct pci_dev *dev);
846 };
847 
848 
849 struct module;
850 
851 /**
852  * struct pci_driver - PCI driver structure
853  * @node:	List of driver structures.
854  * @name:	Driver name.
855  * @id_table:	Pointer to table of device IDs the driver is
856  *		interested in.  Most drivers should export this
857  *		table using MODULE_DEVICE_TABLE(pci,...).
858  * @probe:	This probing function gets called (during execution
859  *		of pci_register_driver() for already existing
860  *		devices or later if a new device gets inserted) for
861  *		all PCI devices which match the ID table and are not
862  *		"owned" by the other drivers yet. This function gets
863  *		passed a "struct pci_dev \*" for each device whose
864  *		entry in the ID table matches the device. The probe
865  *		function returns zero when the driver chooses to
866  *		take "ownership" of the device or an error code
867  *		(negative number) otherwise.
868  *		The probe function always gets called from process
869  *		context, so it can sleep.
870  * @remove:	The remove() function gets called whenever a device
871  *		being handled by this driver is removed (either during
872  *		deregistration of the driver or when it's manually
873  *		pulled out of a hot-pluggable slot).
874  *		The remove function always gets called from process
875  *		context, so it can sleep.
876  * @suspend:	Put device into low power state.
877  * @resume:	Wake device from low power state.
878  *		(Please see Documentation/power/pci.rst for descriptions
879  *		of PCI Power Management and the related functions.)
880  * @shutdown:	Hook into reboot_notifier_list (kernel/sys.c).
881  *		Intended to stop any idling DMA operations.
882  *		Useful for enabling wake-on-lan (NIC) or changing
883  *		the power state of a device before reboot.
884  *		e.g. drivers/net/e100.c.
885  * @sriov_configure: Optional driver callback to allow configuration of
886  *		number of VFs to enable via sysfs "sriov_numvfs" file.
887  * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
888  *              vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
889  *              This will change MSI-X Table Size in the VF Message Control
890  *              registers.
891  * @sriov_get_vf_total_msix: PF driver callback to get the total number of
892  *              MSI-X vectors available for distribution to the VFs.
893  * @err_handler: See Documentation/PCI/pci-error-recovery.rst
894  * @groups:	Sysfs attribute groups.
895  * @dev_groups: Attributes attached to the device that will be
896  *              created once it is bound to the driver.
897  * @driver:	Driver model structure.
898  * @dynids:	List of dynamically added device IDs.
899  * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
900  *		For most device drivers, no need to care about this flag
901  *		as long as all DMAs are handled through the kernel DMA API.
902  *		For some special ones, for example VFIO drivers, they know
903  *		how to manage the DMA themselves and set this flag so that
904  *		the IOMMU layer will allow them to setup and manage their
905  *		own I/O address space.
906  */
907 struct pci_driver {
908 	struct list_head	node;
909 	const char		*name;
910 	const struct pci_device_id *id_table;	/* Must be non-NULL for probe to be called */
911 	int  (*probe)(struct pci_dev *dev, const struct pci_device_id *id);	/* New device inserted */
912 	void (*remove)(struct pci_dev *dev);	/* Device removed (NULL if not a hot-plug capable driver) */
913 	int  (*suspend)(struct pci_dev *dev, pm_message_t state);	/* Device suspended */
914 	int  (*resume)(struct pci_dev *dev);	/* Device woken up */
915 	void (*shutdown)(struct pci_dev *dev);
916 	int  (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
917 	int  (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
918 	u32  (*sriov_get_vf_total_msix)(struct pci_dev *pf);
919 	const struct pci_error_handlers *err_handler;
920 	const struct attribute_group **groups;
921 	const struct attribute_group **dev_groups;
922 	struct device_driver	driver;
923 	struct pci_dynids	dynids;
924 	bool driver_managed_dma;
925 };
926 
to_pci_driver(struct device_driver * drv)927 static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
928 {
929     return drv ? container_of(drv, struct pci_driver, driver) : NULL;
930 }
931 
932 /**
933  * PCI_DEVICE - macro used to describe a specific PCI device
934  * @vend: the 16 bit PCI Vendor ID
935  * @dev: the 16 bit PCI Device ID
936  *
937  * This macro is used to create a struct pci_device_id that matches a
938  * specific device.  The subvendor and subdevice fields will be set to
939  * PCI_ANY_ID.
940  */
941 #define PCI_DEVICE(vend,dev) \
942 	.vendor = (vend), .device = (dev), \
943 	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
944 
945 /**
946  * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
947  *                              override_only flags.
948  * @vend: the 16 bit PCI Vendor ID
949  * @dev: the 16 bit PCI Device ID
950  * @driver_override: the 32 bit PCI Device override_only
951  *
952  * This macro is used to create a struct pci_device_id that matches only a
953  * driver_override device. The subvendor and subdevice fields will be set to
954  * PCI_ANY_ID.
955  */
956 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
957 	.vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
958 	.subdevice = PCI_ANY_ID, .override_only = (driver_override)
959 
960 /**
961  * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
962  *                                   "driver_override" PCI device.
963  * @vend: the 16 bit PCI Vendor ID
964  * @dev: the 16 bit PCI Device ID
965  *
966  * This macro is used to create a struct pci_device_id that matches a
967  * specific device. The subvendor and subdevice fields will be set to
968  * PCI_ANY_ID and the driver_override will be set to
969  * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
970  */
971 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
972 	PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
973 
974 /**
975  * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
976  * @vend: the 16 bit PCI Vendor ID
977  * @dev: the 16 bit PCI Device ID
978  * @subvend: the 16 bit PCI Subvendor ID
979  * @subdev: the 16 bit PCI Subdevice ID
980  *
981  * This macro is used to create a struct pci_device_id that matches a
982  * specific device with subsystem information.
983  */
984 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
985 	.vendor = (vend), .device = (dev), \
986 	.subvendor = (subvend), .subdevice = (subdev)
987 
988 /**
989  * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
990  * @dev_class: the class, subclass, prog-if triple for this device
991  * @dev_class_mask: the class mask for this device
992  *
993  * This macro is used to create a struct pci_device_id that matches a
994  * specific PCI class.  The vendor, device, subvendor, and subdevice
995  * fields will be set to PCI_ANY_ID.
996  */
997 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
998 	.class = (dev_class), .class_mask = (dev_class_mask), \
999 	.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1000 	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1001 
1002 /**
1003  * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1004  * @vend: the vendor name
1005  * @dev: the 16 bit PCI Device ID
1006  *
1007  * This macro is used to create a struct pci_device_id that matches a
1008  * specific PCI device.  The subvendor, and subdevice fields will be set
1009  * to PCI_ANY_ID. The macro allows the next field to follow as the device
1010  * private data.
1011  */
1012 #define PCI_VDEVICE(vend, dev) \
1013 	.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1014 	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1015 
1016 /**
1017  * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1018  * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1019  * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1020  * @data: the driver data to be filled
1021  *
1022  * This macro is used to create a struct pci_device_id that matches a
1023  * specific PCI device.  The subvendor, and subdevice fields will be set
1024  * to PCI_ANY_ID.
1025  */
1026 #define PCI_DEVICE_DATA(vend, dev, data) \
1027 	.vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1028 	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1029 	.driver_data = (kernel_ulong_t)(data)
1030 
1031 enum {
1032 	PCI_REASSIGN_ALL_RSRC	= 0x00000001,	/* Ignore firmware setup */
1033 	PCI_REASSIGN_ALL_BUS	= 0x00000002,	/* Reassign all bus numbers */
1034 	PCI_PROBE_ONLY		= 0x00000004,	/* Use existing setup */
1035 	PCI_CAN_SKIP_ISA_ALIGN	= 0x00000008,	/* Don't do ISA alignment */
1036 	PCI_ENABLE_PROC_DOMAINS	= 0x00000010,	/* Enable domains in /proc */
1037 	PCI_COMPAT_DOMAIN_0	= 0x00000020,	/* ... except domain 0 */
1038 	PCI_SCAN_ALL_PCIE_DEVS	= 0x00000040,	/* Scan all, not just dev 0 */
1039 };
1040 
1041 #define PCI_IRQ_LEGACY		(1 << 0) /* Allow legacy interrupts */
1042 #define PCI_IRQ_MSI		(1 << 1) /* Allow MSI interrupts */
1043 #define PCI_IRQ_MSIX		(1 << 2) /* Allow MSI-X interrupts */
1044 #define PCI_IRQ_AFFINITY	(1 << 3) /* Auto-assign affinity */
1045 
1046 /* These external functions are only available when PCI support is enabled */
1047 #ifdef CONFIG_PCI
1048 
1049 extern unsigned int pci_flags;
1050 
pci_set_flags(int flags)1051 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)1052 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)1053 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)1054 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1055 
1056 void pcie_bus_configure_settings(struct pci_bus *bus);
1057 
1058 enum pcie_bus_config_types {
1059 	PCIE_BUS_TUNE_OFF,	/* Don't touch MPS at all */
1060 	PCIE_BUS_DEFAULT,	/* Ensure MPS matches upstream bridge */
1061 	PCIE_BUS_SAFE,		/* Use largest MPS boot-time devices support */
1062 	PCIE_BUS_PERFORMANCE,	/* Use MPS and MRRS for best performance */
1063 	PCIE_BUS_PEER2PEER,	/* Set MPS = 128 for all devices */
1064 };
1065 
1066 extern enum pcie_bus_config_types pcie_bus_config;
1067 
1068 extern struct bus_type pci_bus_type;
1069 
1070 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1071  * code, or PCI core code. */
1072 extern struct list_head pci_root_buses;	/* List of all known PCI buses */
1073 /* Some device drivers need know if PCI is initiated */
1074 int no_pci_devices(void);
1075 
1076 void pcibios_resource_survey_bus(struct pci_bus *bus);
1077 void pcibios_bus_add_device(struct pci_dev *pdev);
1078 void pcibios_add_bus(struct pci_bus *bus);
1079 void pcibios_remove_bus(struct pci_bus *bus);
1080 void pcibios_fixup_bus(struct pci_bus *);
1081 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1082 /* Architecture-specific versions may override this (weak) */
1083 char *pcibios_setup(char *str);
1084 
1085 /* Used only when drivers/pci/setup.c is used */
1086 resource_size_t pcibios_align_resource(void *, const struct resource *,
1087 				resource_size_t,
1088 				resource_size_t);
1089 
1090 /* Weak but can be overridden by arch */
1091 void pci_fixup_cardbus(struct pci_bus *);
1092 
1093 /* Generic PCI functions used internally */
1094 
1095 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1096 			     struct resource *res);
1097 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1098 			     struct pci_bus_region *region);
1099 void pcibios_scan_specific_bus(int busn);
1100 struct pci_bus *pci_find_bus(int domain, int busnr);
1101 void pci_bus_add_devices(const struct pci_bus *bus);
1102 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1103 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1104 				    struct pci_ops *ops, void *sysdata,
1105 				    struct list_head *resources);
1106 int pci_host_probe(struct pci_host_bridge *bridge);
1107 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1108 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1109 void pci_bus_release_busn_res(struct pci_bus *b);
1110 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1111 				  struct pci_ops *ops, void *sysdata,
1112 				  struct list_head *resources);
1113 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1114 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1115 				int busnr);
1116 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1117 				 const char *name,
1118 				 struct hotplug_slot *hotplug);
1119 void pci_destroy_slot(struct pci_slot *slot);
1120 #ifdef CONFIG_SYSFS
1121 void pci_dev_assign_slot(struct pci_dev *dev);
1122 #else
pci_dev_assign_slot(struct pci_dev * dev)1123 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1124 #endif
1125 int pci_scan_slot(struct pci_bus *bus, int devfn);
1126 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1127 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1128 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1129 void pci_bus_add_device(struct pci_dev *dev);
1130 void pci_read_bridge_bases(struct pci_bus *child);
1131 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1132 					  struct resource *res);
1133 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1134 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1135 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1136 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1137 void pci_dev_put(struct pci_dev *dev);
1138 void pci_remove_bus(struct pci_bus *b);
1139 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1140 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1141 void pci_stop_root_bus(struct pci_bus *bus);
1142 void pci_remove_root_bus(struct pci_bus *bus);
1143 void pci_setup_cardbus(struct pci_bus *bus);
1144 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1145 void pci_sort_breadthfirst(void);
1146 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1147 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1148 
1149 /* Generic PCI functions exported to card drivers */
1150 
1151 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1152 u8 pci_find_capability(struct pci_dev *dev, int cap);
1153 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1154 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1155 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1156 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1157 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1158 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1159 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1160 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1161 
1162 u64 pci_get_dsn(struct pci_dev *dev);
1163 
1164 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1165 			       struct pci_dev *from);
1166 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1167 			       unsigned int ss_vendor, unsigned int ss_device,
1168 			       struct pci_dev *from);
1169 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1170 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1171 					    unsigned int devfn);
1172 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1173 int pci_dev_present(const struct pci_device_id *ids);
1174 
1175 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1176 			     int where, u8 *val);
1177 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1178 			     int where, u16 *val);
1179 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1180 			      int where, u32 *val);
1181 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1182 			      int where, u8 val);
1183 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1184 			      int where, u16 val);
1185 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1186 			       int where, u32 val);
1187 
1188 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1189 			    int where, int size, u32 *val);
1190 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1191 			    int where, int size, u32 val);
1192 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1193 			      int where, int size, u32 *val);
1194 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1195 			       int where, int size, u32 val);
1196 
1197 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1198 
1199 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1200 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1201 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1202 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1203 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1204 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1205 
1206 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1207 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1208 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1209 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1210 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1211 				       u16 clear, u16 set);
1212 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1213 					u32 clear, u32 set);
1214 
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1215 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1216 					   u16 set)
1217 {
1218 	return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1219 }
1220 
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1221 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1222 					    u32 set)
1223 {
1224 	return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1225 }
1226 
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1227 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1228 					     u16 clear)
1229 {
1230 	return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1231 }
1232 
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1233 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1234 					      u32 clear)
1235 {
1236 	return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1237 }
1238 
1239 /* User-space driven config access */
1240 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1241 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1242 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1243 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1244 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1245 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1246 
1247 int __must_check pci_enable_device(struct pci_dev *dev);
1248 int __must_check pci_enable_device_io(struct pci_dev *dev);
1249 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1250 int __must_check pci_reenable_device(struct pci_dev *);
1251 int __must_check pcim_enable_device(struct pci_dev *pdev);
1252 void pcim_pin_device(struct pci_dev *pdev);
1253 
pci_intx_mask_supported(struct pci_dev * pdev)1254 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1255 {
1256 	/*
1257 	 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1258 	 * writable and no quirk has marked the feature broken.
1259 	 */
1260 	return !pdev->broken_intx_masking;
1261 }
1262 
pci_is_enabled(struct pci_dev * pdev)1263 static inline int pci_is_enabled(struct pci_dev *pdev)
1264 {
1265 	return (atomic_read(&pdev->enable_cnt) > 0);
1266 }
1267 
pci_is_managed(struct pci_dev * pdev)1268 static inline int pci_is_managed(struct pci_dev *pdev)
1269 {
1270 	return pdev->is_managed;
1271 }
1272 
1273 void pci_disable_device(struct pci_dev *dev);
1274 
1275 extern unsigned int pcibios_max_latency;
1276 void pci_set_master(struct pci_dev *dev);
1277 void pci_clear_master(struct pci_dev *dev);
1278 
1279 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1280 int pci_set_cacheline_size(struct pci_dev *dev);
1281 int __must_check pci_set_mwi(struct pci_dev *dev);
1282 int __must_check pcim_set_mwi(struct pci_dev *dev);
1283 int pci_try_set_mwi(struct pci_dev *dev);
1284 void pci_clear_mwi(struct pci_dev *dev);
1285 void pci_disable_parity(struct pci_dev *dev);
1286 void pci_intx(struct pci_dev *dev, int enable);
1287 bool pci_check_and_mask_intx(struct pci_dev *dev);
1288 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1289 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1290 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1291 int pcix_get_max_mmrbc(struct pci_dev *dev);
1292 int pcix_get_mmrbc(struct pci_dev *dev);
1293 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1294 int pcie_get_readrq(struct pci_dev *dev);
1295 int pcie_set_readrq(struct pci_dev *dev, int rq);
1296 int pcie_get_mps(struct pci_dev *dev);
1297 int pcie_set_mps(struct pci_dev *dev, int mps);
1298 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1299 			     enum pci_bus_speed *speed,
1300 			     enum pcie_link_width *width);
1301 void pcie_print_link_status(struct pci_dev *dev);
1302 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1303 int pcie_flr(struct pci_dev *dev);
1304 int __pci_reset_function_locked(struct pci_dev *dev);
1305 int pci_reset_function(struct pci_dev *dev);
1306 int pci_reset_function_locked(struct pci_dev *dev);
1307 int pci_try_reset_function(struct pci_dev *dev);
1308 int pci_probe_reset_slot(struct pci_slot *slot);
1309 int pci_probe_reset_bus(struct pci_bus *bus);
1310 int pci_reset_bus(struct pci_dev *dev);
1311 void pci_reset_secondary_bus(struct pci_dev *dev);
1312 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1313 void pci_update_resource(struct pci_dev *dev, int resno);
1314 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1315 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1316 void pci_release_resource(struct pci_dev *dev, int resno);
pci_rebar_bytes_to_size(u64 bytes)1317 static inline int pci_rebar_bytes_to_size(u64 bytes)
1318 {
1319 	bytes = roundup_pow_of_two(bytes);
1320 
1321 	/* Return BAR size as defined in the resizable BAR specification */
1322 	return max(ilog2(bytes), 20) - 20;
1323 }
1324 
1325 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1326 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1327 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1328 bool pci_device_is_present(struct pci_dev *pdev);
1329 void pci_ignore_hotplug(struct pci_dev *dev);
1330 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1331 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1332 
1333 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1334 		irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1335 		const char *fmt, ...);
1336 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1337 
1338 /* ROM control related routines */
1339 int pci_enable_rom(struct pci_dev *pdev);
1340 void pci_disable_rom(struct pci_dev *pdev);
1341 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1342 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1343 
1344 /* Power management related routines */
1345 int pci_save_state(struct pci_dev *dev);
1346 void pci_restore_state(struct pci_dev *dev);
1347 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1348 int pci_load_saved_state(struct pci_dev *dev,
1349 			 struct pci_saved_state *state);
1350 int pci_load_and_free_saved_state(struct pci_dev *dev,
1351 				  struct pci_saved_state **state);
1352 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1353 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1354 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1355 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1356 void pci_pme_active(struct pci_dev *dev, bool enable);
1357 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1358 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1359 int pci_prepare_to_sleep(struct pci_dev *dev);
1360 int pci_back_from_sleep(struct pci_dev *dev);
1361 bool pci_dev_run_wake(struct pci_dev *dev);
1362 void pci_d3cold_enable(struct pci_dev *dev);
1363 void pci_d3cold_disable(struct pci_dev *dev);
1364 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1365 void pci_resume_bus(struct pci_bus *bus);
1366 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1367 
1368 /* For use by arch with custom probe code */
1369 void set_pcie_port_type(struct pci_dev *pdev);
1370 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1371 
1372 /* Functions for PCI Hotplug drivers to use */
1373 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1374 unsigned int pci_rescan_bus(struct pci_bus *bus);
1375 void pci_lock_rescan_remove(void);
1376 void pci_unlock_rescan_remove(void);
1377 
1378 /* Vital Product Data routines */
1379 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1380 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1381 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1382 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1383 
1384 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1385 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1386 void pci_bus_assign_resources(const struct pci_bus *bus);
1387 void pci_bus_claim_resources(struct pci_bus *bus);
1388 void pci_bus_size_bridges(struct pci_bus *bus);
1389 int pci_claim_resource(struct pci_dev *, int);
1390 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1391 void pci_assign_unassigned_resources(void);
1392 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1393 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1394 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1395 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1396 void pdev_enable_device(struct pci_dev *);
1397 int pci_enable_resources(struct pci_dev *, int mask);
1398 void pci_assign_irq(struct pci_dev *dev);
1399 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1400 #define HAVE_PCI_REQ_REGIONS	2
1401 int __must_check pci_request_regions(struct pci_dev *, const char *);
1402 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1403 void pci_release_regions(struct pci_dev *);
1404 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1405 void pci_release_region(struct pci_dev *, int);
1406 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1407 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1408 void pci_release_selected_regions(struct pci_dev *, int);
1409 
1410 /* drivers/pci/bus.c */
1411 void pci_add_resource(struct list_head *resources, struct resource *res);
1412 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1413 			     resource_size_t offset);
1414 void pci_free_resource_list(struct list_head *resources);
1415 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1416 			  unsigned int flags);
1417 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1418 void pci_bus_remove_resources(struct pci_bus *bus);
1419 int devm_request_pci_bus_resources(struct device *dev,
1420 				   struct list_head *resources);
1421 
1422 /* Temporary until new and working PCI SBR API in place */
1423 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1424 
1425 #define pci_bus_for_each_resource(bus, res, i)				\
1426 	for (i = 0;							\
1427 	    (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1428 	     i++)
1429 
1430 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1431 			struct resource *res, resource_size_t size,
1432 			resource_size_t align, resource_size_t min,
1433 			unsigned long type_mask,
1434 			resource_size_t (*alignf)(void *,
1435 						  const struct resource *,
1436 						  resource_size_t,
1437 						  resource_size_t),
1438 			void *alignf_data);
1439 
1440 
1441 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1442 			resource_size_t size);
1443 unsigned long pci_address_to_pio(phys_addr_t addr);
1444 phys_addr_t pci_pio_to_address(unsigned long pio);
1445 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1446 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1447 			   phys_addr_t phys_addr);
1448 void pci_unmap_iospace(struct resource *res);
1449 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1450 				      resource_size_t offset,
1451 				      resource_size_t size);
1452 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1453 					  struct resource *res);
1454 
pci_bus_address(struct pci_dev * pdev,int bar)1455 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1456 {
1457 	struct pci_bus_region region;
1458 
1459 	pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1460 	return region.start;
1461 }
1462 
1463 /* Proper probing supporting hot-pluggable devices */
1464 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1465 				       const char *mod_name);
1466 
1467 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1468 #define pci_register_driver(driver)		\
1469 	__pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1470 
1471 void pci_unregister_driver(struct pci_driver *dev);
1472 
1473 /**
1474  * module_pci_driver() - Helper macro for registering a PCI driver
1475  * @__pci_driver: pci_driver struct
1476  *
1477  * Helper macro for PCI drivers which do not do anything special in module
1478  * init/exit. This eliminates a lot of boilerplate. Each module may only
1479  * use this macro once, and calling it replaces module_init() and module_exit()
1480  */
1481 #define module_pci_driver(__pci_driver) \
1482 	module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1483 
1484 /**
1485  * builtin_pci_driver() - Helper macro for registering a PCI driver
1486  * @__pci_driver: pci_driver struct
1487  *
1488  * Helper macro for PCI drivers which do not do anything special in their
1489  * init code. This eliminates a lot of boilerplate. Each driver may only
1490  * use this macro once, and calling it replaces device_initcall(...)
1491  */
1492 #define builtin_pci_driver(__pci_driver) \
1493 	builtin_driver(__pci_driver, pci_register_driver)
1494 
1495 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1496 int pci_add_dynid(struct pci_driver *drv,
1497 		  unsigned int vendor, unsigned int device,
1498 		  unsigned int subvendor, unsigned int subdevice,
1499 		  unsigned int class, unsigned int class_mask,
1500 		  unsigned long driver_data);
1501 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1502 					 struct pci_dev *dev);
1503 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1504 		    int pass);
1505 
1506 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1507 		  void *userdata);
1508 int pci_cfg_space_size(struct pci_dev *dev);
1509 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1510 void pci_setup_bridge(struct pci_bus *bus);
1511 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1512 					 unsigned long type);
1513 
1514 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1515 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1516 
1517 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1518 		      unsigned int command_bits, u32 flags);
1519 
1520 /*
1521  * Virtual interrupts allow for more interrupts to be allocated
1522  * than the device has interrupts for. These are not programmed
1523  * into the device's MSI-X table and must be handled by some
1524  * other driver means.
1525  */
1526 #define PCI_IRQ_VIRTUAL		(1 << 4)
1527 
1528 #define PCI_IRQ_ALL_TYPES \
1529 	(PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1530 
1531 #include <linux/dmapool.h>
1532 
1533 struct msix_entry {
1534 	u32	vector;	/* Kernel uses to write allocated vector */
1535 	u16	entry;	/* Driver uses to specify entry, OS writes */
1536 };
1537 
1538 #ifdef CONFIG_PCI_MSI
1539 int pci_msi_vec_count(struct pci_dev *dev);
1540 void pci_disable_msi(struct pci_dev *dev);
1541 int pci_msix_vec_count(struct pci_dev *dev);
1542 void pci_disable_msix(struct pci_dev *dev);
1543 void pci_restore_msi_state(struct pci_dev *dev);
1544 int pci_msi_enabled(void);
1545 int pci_enable_msi(struct pci_dev *dev);
1546 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1547 			  int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1548 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1549 					struct msix_entry *entries, int nvec)
1550 {
1551 	int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1552 	if (rc < 0)
1553 		return rc;
1554 	return 0;
1555 }
1556 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1557 				   unsigned int max_vecs, unsigned int flags,
1558 				   struct irq_affinity *affd);
1559 
1560 void pci_free_irq_vectors(struct pci_dev *dev);
1561 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1562 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1563 
1564 #else
pci_msi_vec_count(struct pci_dev * dev)1565 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1566 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1567 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1568 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1569 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1570 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1571 static inline int pci_enable_msi(struct pci_dev *dev)
1572 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1573 static inline int pci_enable_msix_range(struct pci_dev *dev,
1574 			struct msix_entry *entries, int minvec, int maxvec)
1575 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1576 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1577 			struct msix_entry *entries, int nvec)
1578 { return -ENOSYS; }
1579 
1580 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1581 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1582 			       unsigned int max_vecs, unsigned int flags,
1583 			       struct irq_affinity *aff_desc)
1584 {
1585 	if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1586 		return 1;
1587 	return -ENOSPC;
1588 }
1589 
pci_free_irq_vectors(struct pci_dev * dev)1590 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1591 {
1592 }
1593 
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1594 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1595 {
1596 	if (WARN_ON_ONCE(nr > 0))
1597 		return -EINVAL;
1598 	return dev->irq;
1599 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1600 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1601 		int vec)
1602 {
1603 	return cpu_possible_mask;
1604 }
1605 #endif
1606 
1607 /**
1608  * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1609  * @d: the INTx IRQ domain
1610  * @node: the DT node for the device whose interrupt we're translating
1611  * @intspec: the interrupt specifier data from the DT
1612  * @intsize: the number of entries in @intspec
1613  * @out_hwirq: pointer at which to write the hwirq number
1614  * @out_type: pointer at which to write the interrupt type
1615  *
1616  * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1617  * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1618  * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1619  * INTx value to obtain the hwirq number.
1620  *
1621  * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1622  */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1623 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1624 				      struct device_node *node,
1625 				      const u32 *intspec,
1626 				      unsigned int intsize,
1627 				      unsigned long *out_hwirq,
1628 				      unsigned int *out_type)
1629 {
1630 	const u32 intx = intspec[0];
1631 
1632 	if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1633 		return -EINVAL;
1634 
1635 	*out_hwirq = intx - PCI_INTERRUPT_INTA;
1636 	return 0;
1637 }
1638 
1639 #ifdef CONFIG_PCIEPORTBUS
1640 extern bool pcie_ports_disabled;
1641 extern bool pcie_ports_native;
1642 #else
1643 #define pcie_ports_disabled	true
1644 #define pcie_ports_native	false
1645 #endif
1646 
1647 #define PCIE_LINK_STATE_L0S		BIT(0)
1648 #define PCIE_LINK_STATE_L1		BIT(1)
1649 #define PCIE_LINK_STATE_CLKPM		BIT(2)
1650 #define PCIE_LINK_STATE_L1_1		BIT(3)
1651 #define PCIE_LINK_STATE_L1_2		BIT(4)
1652 #define PCIE_LINK_STATE_L1_1_PCIPM	BIT(5)
1653 #define PCIE_LINK_STATE_L1_2_PCIPM	BIT(6)
1654 
1655 #ifdef CONFIG_PCIEASPM
1656 int pci_disable_link_state(struct pci_dev *pdev, int state);
1657 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1658 void pcie_no_aspm(void);
1659 bool pcie_aspm_support_enabled(void);
1660 bool pcie_aspm_enabled(struct pci_dev *pdev);
1661 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1662 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1663 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1664 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1665 { return 0; }
pcie_no_aspm(void)1666 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1667 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1668 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1669 #endif
1670 
1671 #ifdef CONFIG_PCIEAER
1672 bool pci_aer_available(void);
1673 #else
pci_aer_available(void)1674 static inline bool pci_aer_available(void) { return false; }
1675 #endif
1676 
1677 bool pci_ats_disabled(void);
1678 
1679 #ifdef CONFIG_PCIE_PTM
1680 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1681 void pci_disable_ptm(struct pci_dev *dev);
1682 bool pcie_ptm_enabled(struct pci_dev *dev);
1683 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1684 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1685 { return -EINVAL; }
pci_disable_ptm(struct pci_dev * dev)1686 static inline void pci_disable_ptm(struct pci_dev *dev) { }
pcie_ptm_enabled(struct pci_dev * dev)1687 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1688 { return false; }
1689 #endif
1690 
1691 void pci_cfg_access_lock(struct pci_dev *dev);
1692 bool pci_cfg_access_trylock(struct pci_dev *dev);
1693 void pci_cfg_access_unlock(struct pci_dev *dev);
1694 
1695 void pci_dev_lock(struct pci_dev *dev);
1696 int pci_dev_trylock(struct pci_dev *dev);
1697 void pci_dev_unlock(struct pci_dev *dev);
1698 
1699 /*
1700  * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
1701  * a PCI domain is defined to be a set of PCI buses which share
1702  * configuration space.
1703  */
1704 #ifdef CONFIG_PCI_DOMAINS
1705 extern int pci_domains_supported;
1706 #else
1707 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1708 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1709 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1710 #endif /* CONFIG_PCI_DOMAINS */
1711 
1712 /*
1713  * Generic implementation for PCI domain support. If your
1714  * architecture does not need custom management of PCI
1715  * domains then this implementation will be used
1716  */
1717 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1718 static inline int pci_domain_nr(struct pci_bus *bus)
1719 {
1720 	return bus->domain_nr;
1721 }
1722 #ifdef CONFIG_ACPI
1723 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1724 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1725 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1726 { return 0; }
1727 #endif
1728 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1729 #endif
1730 
1731 /* Some architectures require additional setup to direct VGA traffic */
1732 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1733 				    unsigned int command_bits, u32 flags);
1734 void pci_register_set_vga_state(arch_set_vga_state_t func);
1735 
1736 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1737 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1738 {
1739 	return pci_request_selected_regions(pdev,
1740 			    pci_select_bars(pdev, IORESOURCE_IO), name);
1741 }
1742 
1743 static inline void
pci_release_io_regions(struct pci_dev * pdev)1744 pci_release_io_regions(struct pci_dev *pdev)
1745 {
1746 	return pci_release_selected_regions(pdev,
1747 			    pci_select_bars(pdev, IORESOURCE_IO));
1748 }
1749 
1750 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1751 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1752 {
1753 	return pci_request_selected_regions(pdev,
1754 			    pci_select_bars(pdev, IORESOURCE_MEM), name);
1755 }
1756 
1757 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1758 pci_release_mem_regions(struct pci_dev *pdev)
1759 {
1760 	return pci_release_selected_regions(pdev,
1761 			    pci_select_bars(pdev, IORESOURCE_MEM));
1762 }
1763 
1764 #else /* CONFIG_PCI is not enabled */
1765 
pci_set_flags(int flags)1766 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1767 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1768 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1769 static inline int pci_has_flag(int flag) { return 0; }
1770 
1771 /*
1772  * If the system does not have PCI, clearly these return errors.  Define
1773  * these as simple inline functions to avoid hair in drivers.
1774  */
1775 #define _PCI_NOP(o, s, t) \
1776 	static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1777 						int where, t val) \
1778 		{ return PCIBIOS_FUNC_NOT_SUPPORTED; }
1779 
1780 #define _PCI_NOP_ALL(o, x)	_PCI_NOP(o, byte, u8 x) \
1781 				_PCI_NOP(o, word, u16 x) \
1782 				_PCI_NOP(o, dword, u32 x)
1783 _PCI_NOP_ALL(read, *)
1784 _PCI_NOP_ALL(write,)
1785 
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1786 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1787 					     unsigned int device,
1788 					     struct pci_dev *from)
1789 { return NULL; }
1790 
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1791 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1792 					     unsigned int device,
1793 					     unsigned int ss_vendor,
1794 					     unsigned int ss_device,
1795 					     struct pci_dev *from)
1796 { return NULL; }
1797 
pci_get_class(unsigned int class,struct pci_dev * from)1798 static inline struct pci_dev *pci_get_class(unsigned int class,
1799 					    struct pci_dev *from)
1800 { return NULL; }
1801 
1802 
pci_dev_present(const struct pci_device_id * ids)1803 static inline int pci_dev_present(const struct pci_device_id *ids)
1804 { return 0; }
1805 
1806 #define no_pci_devices()	(1)
1807 #define pci_dev_put(dev)	do { } while (0)
1808 
pci_set_master(struct pci_dev * dev)1809 static inline void pci_set_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1810 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1811 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1812 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1813 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1814 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1815 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1816 						     struct module *owner,
1817 						     const char *mod_name)
1818 { return 0; }
pci_register_driver(struct pci_driver * drv)1819 static inline int pci_register_driver(struct pci_driver *drv)
1820 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1821 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1822 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1823 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1824 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1825 					   int cap)
1826 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1827 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1828 { return 0; }
1829 
pci_get_dsn(struct pci_dev * dev)1830 static inline u64 pci_get_dsn(struct pci_dev *dev)
1831 { return 0; }
1832 
1833 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1834 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1835 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1836 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1837 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1838 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1839 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1840 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1841 					   pm_message_t state)
1842 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1843 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1844 				  int enable)
1845 { return 0; }
1846 
pci_find_resource(struct pci_dev * dev,struct resource * res)1847 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1848 						 struct resource *res)
1849 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1850 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1851 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1852 static inline void pci_release_regions(struct pci_dev *dev) { }
1853 
pci_register_io_range(struct fwnode_handle * fwnode,phys_addr_t addr,resource_size_t size)1854 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1855 					phys_addr_t addr, resource_size_t size)
1856 { return -EINVAL; }
1857 
pci_address_to_pio(phys_addr_t addr)1858 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1859 
pci_find_next_bus(const struct pci_bus * from)1860 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1861 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1862 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1863 						unsigned int devfn)
1864 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1865 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1866 					unsigned int bus, unsigned int devfn)
1867 { return NULL; }
1868 
pci_domain_nr(struct pci_bus * bus)1869 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1870 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1871 
1872 #define dev_is_pci(d) (false)
1873 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1874 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1875 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1876 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1877 				      struct device_node *node,
1878 				      const u32 *intspec,
1879 				      unsigned int intsize,
1880 				      unsigned long *out_hwirq,
1881 				      unsigned int *out_type)
1882 { return -EINVAL; }
1883 
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1884 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1885 							 struct pci_dev *dev)
1886 { return NULL; }
pci_ats_disabled(void)1887 static inline bool pci_ats_disabled(void) { return true; }
1888 
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1889 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1890 {
1891 	return -EINVAL;
1892 }
1893 
1894 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1895 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1896 			       unsigned int max_vecs, unsigned int flags,
1897 			       struct irq_affinity *aff_desc)
1898 {
1899 	return -ENOSPC;
1900 }
1901 #endif /* CONFIG_PCI */
1902 
1903 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1904 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1905 		      unsigned int max_vecs, unsigned int flags)
1906 {
1907 	return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1908 					      NULL);
1909 }
1910 
1911 /* Include architecture-dependent settings and functions */
1912 
1913 #include <asm/pci.h>
1914 
1915 /*
1916  * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1917  * is expected to be an offset within that region.
1918  *
1919  */
1920 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1921 			    struct vm_area_struct *vma,
1922 			    enum pci_mmap_state mmap_state, int write_combine);
1923 
1924 #ifndef arch_can_pci_mmap_wc
1925 #define arch_can_pci_mmap_wc()		0
1926 #endif
1927 
1928 #ifndef arch_can_pci_mmap_io
1929 #define arch_can_pci_mmap_io()		0
1930 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1931 #else
1932 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1933 #endif
1934 
1935 #ifndef pci_root_bus_fwnode
1936 #define pci_root_bus_fwnode(bus)	NULL
1937 #endif
1938 
1939 /*
1940  * These helpers provide future and backwards compatibility
1941  * for accessing popular PCI BAR info
1942  */
1943 #define pci_resource_start(dev, bar)	((dev)->resource[(bar)].start)
1944 #define pci_resource_end(dev, bar)	((dev)->resource[(bar)].end)
1945 #define pci_resource_flags(dev, bar)	((dev)->resource[(bar)].flags)
1946 #define pci_resource_len(dev,bar) \
1947 	((pci_resource_end((dev), (bar)) == 0) ? 0 :	\
1948 							\
1949 	 (pci_resource_end((dev), (bar)) -		\
1950 	  pci_resource_start((dev), (bar)) + 1))
1951 
1952 /*
1953  * Similar to the helpers above, these manipulate per-pci_dev
1954  * driver-specific data.  They are really just a wrapper around
1955  * the generic device structure functions of these calls.
1956  */
pci_get_drvdata(struct pci_dev * pdev)1957 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1958 {
1959 	return dev_get_drvdata(&pdev->dev);
1960 }
1961 
pci_set_drvdata(struct pci_dev * pdev,void * data)1962 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1963 {
1964 	dev_set_drvdata(&pdev->dev, data);
1965 }
1966 
pci_name(const struct pci_dev * pdev)1967 static inline const char *pci_name(const struct pci_dev *pdev)
1968 {
1969 	return dev_name(&pdev->dev);
1970 }
1971 
1972 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1973 			  const struct resource *rsrc,
1974 			  resource_size_t *start, resource_size_t *end);
1975 
1976 /*
1977  * The world is not perfect and supplies us with broken PCI devices.
1978  * For at least a part of these bugs we need a work-around, so both
1979  * generic (drivers/pci/quirks.c) and per-architecture code can define
1980  * fixup hooks to be called for particular buggy devices.
1981  */
1982 
1983 struct pci_fixup {
1984 	u16 vendor;			/* Or PCI_ANY_ID */
1985 	u16 device;			/* Or PCI_ANY_ID */
1986 	u32 class;			/* Or PCI_ANY_ID */
1987 	unsigned int class_shift;	/* should be 0, 8, 16 */
1988 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1989 	int hook_offset;
1990 #else
1991 	void (*hook)(struct pci_dev *dev);
1992 #endif
1993 };
1994 
1995 enum pci_fixup_pass {
1996 	pci_fixup_early,	/* Before probing BARs */
1997 	pci_fixup_header,	/* After reading configuration header */
1998 	pci_fixup_final,	/* Final phase of device fixups */
1999 	pci_fixup_enable,	/* pci_enable_device() time */
2000 	pci_fixup_resume,	/* pci_device_resume() */
2001 	pci_fixup_suspend,	/* pci_device_suspend() */
2002 	pci_fixup_resume_early, /* pci_device_resume_early() */
2003 	pci_fixup_suspend_late,	/* pci_device_suspend_late() */
2004 };
2005 
2006 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2007 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class,	\
2008 				    class_shift, hook)			\
2009 	__ADDRESSABLE(hook)						\
2010 	asm(".section "	#sec ", \"a\"				\n"	\
2011 	    ".balign	16					\n"	\
2012 	    ".short "	#vendor ", " #device "			\n"	\
2013 	    ".long "	#class ", " #class_shift "		\n"	\
2014 	    ".long "	#hook " - .				\n"	\
2015 	    ".previous						\n");
2016 
2017 /*
2018  * Clang's LTO may rename static functions in C, but has no way to
2019  * handle such renamings when referenced from inline asm. To work
2020  * around this, create global C stubs for these cases.
2021  */
2022 #ifdef CONFIG_LTO_CLANG
2023 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class,	\
2024 				  class_shift, hook, stub)		\
2025 	void stub(struct pci_dev *dev);					\
2026 	void stub(struct pci_dev *dev)					\
2027 	{ 								\
2028 		hook(dev); 						\
2029 	}								\
2030 	___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class,	\
2031 				  class_shift, stub)
2032 #else
2033 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class,	\
2034 				  class_shift, hook, stub)		\
2035 	___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class,	\
2036 				  class_shift, hook)
2037 #endif
2038 
2039 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class,	\
2040 				  class_shift, hook)			\
2041 	__DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class,	\
2042 				  class_shift, hook, __UNIQUE_ID(hook))
2043 #else
2044 /* Anonymous variables would be nice... */
2045 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class,	\
2046 				  class_shift, hook)			\
2047 	static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used	\
2048 	__attribute__((__section__(#section), aligned((sizeof(void *)))))    \
2049 		= { vendor, device, class, class_shift, hook };
2050 #endif
2051 
2052 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class,		\
2053 					 class_shift, hook)		\
2054 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,			\
2055 		hook, vendor, device, class, class_shift, hook)
2056 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class,		\
2057 					 class_shift, hook)		\
2058 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,			\
2059 		hook, vendor, device, class, class_shift, hook)
2060 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class,		\
2061 					 class_shift, hook)		\
2062 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,			\
2063 		hook, vendor, device, class, class_shift, hook)
2064 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class,		\
2065 					 class_shift, hook)		\
2066 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,			\
2067 		hook, vendor, device, class, class_shift, hook)
2068 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,		\
2069 					 class_shift, hook)		\
2070 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,			\
2071 		resume##hook, vendor, device, class, class_shift, hook)
2072 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,	\
2073 					 class_shift, hook)		\
2074 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,		\
2075 		resume_early##hook, vendor, device, class, class_shift, hook)
2076 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,		\
2077 					 class_shift, hook)		\
2078 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,			\
2079 		suspend##hook, vendor, device, class, class_shift, hook)
2080 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class,	\
2081 					 class_shift, hook)		\
2082 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,		\
2083 		suspend_late##hook, vendor, device, class, class_shift, hook)
2084 
2085 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)			\
2086 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,			\
2087 		hook, vendor, device, PCI_ANY_ID, 0, hook)
2088 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)			\
2089 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,			\
2090 		hook, vendor, device, PCI_ANY_ID, 0, hook)
2091 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)			\
2092 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,			\
2093 		hook, vendor, device, PCI_ANY_ID, 0, hook)
2094 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)			\
2095 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,			\
2096 		hook, vendor, device, PCI_ANY_ID, 0, hook)
2097 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)			\
2098 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,			\
2099 		resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2100 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)		\
2101 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,		\
2102 		resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2103 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)			\
2104 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,			\
2105 		suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2106 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook)		\
2107 	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,		\
2108 		suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2109 
2110 #ifdef CONFIG_PCI_QUIRKS
2111 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2112 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2113 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2114 				    struct pci_dev *dev) { }
2115 #endif
2116 
2117 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2118 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2119 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2120 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2121 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2122 				   const char *name);
2123 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2124 
2125 extern int pci_pci_problems;
2126 #define PCIPCI_FAIL		1	/* No PCI PCI DMA */
2127 #define PCIPCI_TRITON		2
2128 #define PCIPCI_NATOMA		4
2129 #define PCIPCI_VIAETBF		8
2130 #define PCIPCI_VSFX		16
2131 #define PCIPCI_ALIMAGIK		32	/* Need low latency setting */
2132 #define PCIAGP_FAIL		64	/* No PCI to AGP DMA */
2133 
2134 extern unsigned long pci_cardbus_io_size;
2135 extern unsigned long pci_cardbus_mem_size;
2136 extern u8 pci_dfl_cache_line_size;
2137 extern u8 pci_cache_line_size;
2138 
2139 /* Architecture-specific versions may override these (weak) */
2140 void pcibios_disable_device(struct pci_dev *dev);
2141 void pcibios_set_master(struct pci_dev *dev);
2142 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2143 				 enum pcie_reset_state state);
2144 int pcibios_device_add(struct pci_dev *dev);
2145 void pcibios_release_device(struct pci_dev *dev);
2146 #ifdef CONFIG_PCI
2147 void pcibios_penalize_isa_irq(int irq, int active);
2148 #else
pcibios_penalize_isa_irq(int irq,int active)2149 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2150 #endif
2151 int pcibios_alloc_irq(struct pci_dev *dev);
2152 void pcibios_free_irq(struct pci_dev *dev);
2153 resource_size_t pcibios_default_alignment(void);
2154 
2155 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2156 void __init pci_mmcfg_early_init(void);
2157 void __init pci_mmcfg_late_init(void);
2158 #else
pci_mmcfg_early_init(void)2159 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2160 static inline void pci_mmcfg_late_init(void) { }
2161 #endif
2162 
2163 int pci_ext_cfg_avail(void);
2164 
2165 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2166 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2167 
2168 #ifdef CONFIG_PCI_IOV
2169 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2170 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2171 int pci_iov_vf_id(struct pci_dev *dev);
2172 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2173 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2174 void pci_disable_sriov(struct pci_dev *dev);
2175 
2176 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2177 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2178 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2179 int pci_num_vf(struct pci_dev *dev);
2180 int pci_vfs_assigned(struct pci_dev *dev);
2181 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2182 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2183 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2184 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2185 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2186 
2187 /* Arch may override these (weak) */
2188 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2189 int pcibios_sriov_disable(struct pci_dev *pdev);
2190 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2191 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2192 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2193 {
2194 	return -ENOSYS;
2195 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2196 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2197 {
2198 	return -ENOSYS;
2199 }
2200 
pci_iov_vf_id(struct pci_dev * dev)2201 static inline int pci_iov_vf_id(struct pci_dev *dev)
2202 {
2203 	return -ENOSYS;
2204 }
2205 
pci_iov_get_pf_drvdata(struct pci_dev * dev,struct pci_driver * pf_driver)2206 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2207 					   struct pci_driver *pf_driver)
2208 {
2209 	return ERR_PTR(-EINVAL);
2210 }
2211 
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2212 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2213 { return -ENODEV; }
2214 
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2215 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2216 				     struct pci_dev *virtfn, int id)
2217 {
2218 	return -ENODEV;
2219 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2220 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2221 {
2222 	return -ENOSYS;
2223 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2224 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2225 					 int id) { }
pci_disable_sriov(struct pci_dev * dev)2226 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2227 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2228 static inline int pci_vfs_assigned(struct pci_dev *dev)
2229 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2230 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2231 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2232 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2233 { return 0; }
2234 #define pci_sriov_configure_simple	NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2235 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2236 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2237 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2238 #endif
2239 
2240 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2241 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2242 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2243 #endif
2244 
2245 /**
2246  * pci_pcie_cap - get the saved PCIe capability offset
2247  * @dev: PCI device
2248  *
2249  * PCIe capability offset is calculated at PCI device initialization
2250  * time and saved in the data structure. This function returns saved
2251  * PCIe capability offset. Using this instead of pci_find_capability()
2252  * reduces unnecessary search in the PCI configuration space. If you
2253  * need to calculate PCIe capability offset from raw device for some
2254  * reasons, please use pci_find_capability() instead.
2255  */
pci_pcie_cap(struct pci_dev * dev)2256 static inline int pci_pcie_cap(struct pci_dev *dev)
2257 {
2258 	return dev->pcie_cap;
2259 }
2260 
2261 /**
2262  * pci_is_pcie - check if the PCI device is PCI Express capable
2263  * @dev: PCI device
2264  *
2265  * Returns: true if the PCI device is PCI Express capable, false otherwise.
2266  */
pci_is_pcie(struct pci_dev * dev)2267 static inline bool pci_is_pcie(struct pci_dev *dev)
2268 {
2269 	return pci_pcie_cap(dev);
2270 }
2271 
2272 /**
2273  * pcie_caps_reg - get the PCIe Capabilities Register
2274  * @dev: PCI device
2275  */
pcie_caps_reg(const struct pci_dev * dev)2276 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2277 {
2278 	return dev->pcie_flags_reg;
2279 }
2280 
2281 /**
2282  * pci_pcie_type - get the PCIe device/port type
2283  * @dev: PCI device
2284  */
pci_pcie_type(const struct pci_dev * dev)2285 static inline int pci_pcie_type(const struct pci_dev *dev)
2286 {
2287 	return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2288 }
2289 
2290 /**
2291  * pcie_find_root_port - Get the PCIe root port device
2292  * @dev: PCI device
2293  *
2294  * Traverse up the parent chain and return the PCIe Root Port PCI Device
2295  * for a given PCI/PCIe Device.
2296  */
pcie_find_root_port(struct pci_dev * dev)2297 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2298 {
2299 	while (dev) {
2300 		if (pci_is_pcie(dev) &&
2301 		    pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2302 			return dev;
2303 		dev = pci_upstream_bridge(dev);
2304 	}
2305 
2306 	return NULL;
2307 }
2308 
2309 void pci_request_acs(void);
2310 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2311 bool pci_acs_path_enabled(struct pci_dev *start,
2312 			  struct pci_dev *end, u16 acs_flags);
2313 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2314 
2315 #define PCI_VPD_LRDT			0x80	/* Large Resource Data Type */
2316 #define PCI_VPD_LRDT_ID(x)		((x) | PCI_VPD_LRDT)
2317 
2318 /* Large Resource Data Type Tag Item Names */
2319 #define PCI_VPD_LTIN_ID_STRING		0x02	/* Identifier String */
2320 #define PCI_VPD_LTIN_RO_DATA		0x10	/* Read-Only Data */
2321 #define PCI_VPD_LTIN_RW_DATA		0x11	/* Read-Write Data */
2322 
2323 #define PCI_VPD_LRDT_ID_STRING		PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2324 #define PCI_VPD_LRDT_RO_DATA		PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2325 #define PCI_VPD_LRDT_RW_DATA		PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2326 
2327 #define PCI_VPD_RO_KEYWORD_PARTNO	"PN"
2328 #define PCI_VPD_RO_KEYWORD_SERIALNO	"SN"
2329 #define PCI_VPD_RO_KEYWORD_MFR_ID	"MN"
2330 #define PCI_VPD_RO_KEYWORD_VENDOR0	"V0"
2331 #define PCI_VPD_RO_KEYWORD_CHKSUM	"RV"
2332 
2333 /**
2334  * pci_vpd_alloc - Allocate buffer and read VPD into it
2335  * @dev: PCI device
2336  * @size: pointer to field where VPD length is returned
2337  *
2338  * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2339  */
2340 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2341 
2342 /**
2343  * pci_vpd_find_id_string - Locate id string in VPD
2344  * @buf: Pointer to buffered VPD data
2345  * @len: The length of the buffer area in which to search
2346  * @size: Pointer to field where length of id string is returned
2347  *
2348  * Returns the index of the id string or -ENOENT if not found.
2349  */
2350 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2351 
2352 /**
2353  * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2354  * @buf: Pointer to buffered VPD data
2355  * @len: The length of the buffer area in which to search
2356  * @kw: The keyword to search for
2357  * @size: Pointer to field where length of found keyword data is returned
2358  *
2359  * Returns the index of the information field keyword data or -ENOENT if
2360  * not found.
2361  */
2362 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2363 				 const char *kw, unsigned int *size);
2364 
2365 /**
2366  * pci_vpd_check_csum - Check VPD checksum
2367  * @buf: Pointer to buffered VPD data
2368  * @len: VPD size
2369  *
2370  * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2371  */
2372 int pci_vpd_check_csum(const void *buf, unsigned int len);
2373 
2374 /* PCI <-> OF binding helpers */
2375 #ifdef CONFIG_OF
2376 struct device_node;
2377 struct irq_domain;
2378 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2379 bool pci_host_of_has_msi_map(struct device *dev);
2380 
2381 /* Arch may override this (weak) */
2382 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2383 
2384 #else	/* CONFIG_OF */
2385 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2386 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
pci_host_of_has_msi_map(struct device * dev)2387 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2388 #endif  /* CONFIG_OF */
2389 
2390 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2391 pci_device_to_OF_node(const struct pci_dev *pdev)
2392 {
2393 	return pdev ? pdev->dev.of_node : NULL;
2394 }
2395 
pci_bus_to_OF_node(struct pci_bus * bus)2396 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2397 {
2398 	return bus ? bus->dev.of_node : NULL;
2399 }
2400 
2401 #ifdef CONFIG_ACPI
2402 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2403 
2404 void
2405 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2406 bool pci_pr3_present(struct pci_dev *pdev);
2407 #else
2408 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2409 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2410 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2411 #endif
2412 
2413 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2414 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2415 {
2416 	return pdev->dev.archdata.edev;
2417 }
2418 #endif
2419 
2420 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2421 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2422 int pci_for_each_dma_alias(struct pci_dev *pdev,
2423 			   int (*fn)(struct pci_dev *pdev,
2424 				     u16 alias, void *data), void *data);
2425 
2426 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2427 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2428 {
2429 	pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2430 }
pci_clear_dev_assigned(struct pci_dev * pdev)2431 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2432 {
2433 	pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2434 }
pci_is_dev_assigned(struct pci_dev * pdev)2435 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2436 {
2437 	return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2438 }
2439 
2440 /**
2441  * pci_ari_enabled - query ARI forwarding status
2442  * @bus: the PCI bus
2443  *
2444  * Returns true if ARI forwarding is enabled.
2445  */
pci_ari_enabled(struct pci_bus * bus)2446 static inline bool pci_ari_enabled(struct pci_bus *bus)
2447 {
2448 	return bus->self && bus->self->ari_enabled;
2449 }
2450 
2451 /**
2452  * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2453  * @pdev: PCI device to check
2454  *
2455  * Walk upwards from @pdev and check for each encountered bridge if it's part
2456  * of a Thunderbolt controller.  Reaching the host bridge means @pdev is not
2457  * Thunderbolt-attached.  (But rather soldered to the mainboard usually.)
2458  */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2459 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2460 {
2461 	struct pci_dev *parent = pdev;
2462 
2463 	if (pdev->is_thunderbolt)
2464 		return true;
2465 
2466 	while ((parent = pci_upstream_bridge(parent)))
2467 		if (parent->is_thunderbolt)
2468 			return true;
2469 
2470 	return false;
2471 }
2472 
2473 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2474 void pci_uevent_ers(struct pci_dev *pdev, enum  pci_ers_result err_type);
2475 #endif
2476 
2477 #include <linux/dma-mapping.h>
2478 
2479 #define pci_printk(level, pdev, fmt, arg...) \
2480 	dev_printk(level, &(pdev)->dev, fmt, ##arg)
2481 
2482 #define pci_emerg(pdev, fmt, arg...)	dev_emerg(&(pdev)->dev, fmt, ##arg)
2483 #define pci_alert(pdev, fmt, arg...)	dev_alert(&(pdev)->dev, fmt, ##arg)
2484 #define pci_crit(pdev, fmt, arg...)	dev_crit(&(pdev)->dev, fmt, ##arg)
2485 #define pci_err(pdev, fmt, arg...)	dev_err(&(pdev)->dev, fmt, ##arg)
2486 #define pci_warn(pdev, fmt, arg...)	dev_warn(&(pdev)->dev, fmt, ##arg)
2487 #define pci_notice(pdev, fmt, arg...)	dev_notice(&(pdev)->dev, fmt, ##arg)
2488 #define pci_info(pdev, fmt, arg...)	dev_info(&(pdev)->dev, fmt, ##arg)
2489 #define pci_dbg(pdev, fmt, arg...)	dev_dbg(&(pdev)->dev, fmt, ##arg)
2490 
2491 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2492 	dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2493 
2494 #define pci_info_ratelimited(pdev, fmt, arg...) \
2495 	dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2496 
2497 #define pci_WARN(pdev, condition, fmt, arg...) \
2498 	WARN(condition, "%s %s: " fmt, \
2499 	     dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2500 
2501 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2502 	WARN_ONCE(condition, "%s %s: " fmt, \
2503 		  dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2504 
2505 #endif /* LINUX_PCI_H */
2506