1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * ci.h - common structures, functions, and macros of the ChipIdea driver
4 *
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 *
7 * Author: David Lopo
8 */
9
10 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
11 #define __DRIVERS_USB_CHIPIDEA_CI_H
12
13 #include <linux/list.h>
14 #include <linux/irqreturn.h>
15 #include <linux/usb.h>
16 #include <linux/usb/gadget.h>
17 #include <linux/usb/otg-fsm.h>
18 #include <linux/usb/otg.h>
19 #include <linux/usb/role.h>
20 #include <linux/ulpi/interface.h>
21
22 /******************************************************************************
23 * DEFINE
24 *****************************************************************************/
25 #define TD_PAGE_COUNT 5
26 #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
27 #define ENDPT_MAX 32
28 #define CI_MAX_BUF_SIZE (TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE)
29
30 /******************************************************************************
31 * REGISTERS
32 *****************************************************************************/
33 /* Identification Registers */
34 #define ID_ID 0x0
35 #define ID_HWGENERAL 0x4
36 #define ID_HWHOST 0x8
37 #define ID_HWDEVICE 0xc
38 #define ID_HWTXBUF 0x10
39 #define ID_HWRXBUF 0x14
40 #define ID_SBUSCFG 0x90
41
42 /* register indices */
43 enum ci_hw_regs {
44 CAP_CAPLENGTH,
45 CAP_HCCPARAMS,
46 CAP_DCCPARAMS,
47 CAP_TESTMODE,
48 CAP_LAST = CAP_TESTMODE,
49 OP_USBCMD,
50 OP_USBSTS,
51 OP_USBINTR,
52 OP_FRINDEX,
53 OP_DEVICEADDR,
54 OP_ENDPTLISTADDR,
55 OP_TTCTRL,
56 OP_BURSTSIZE,
57 OP_ULPI_VIEWPORT,
58 OP_PORTSC,
59 OP_DEVLC,
60 OP_OTGSC,
61 OP_USBMODE,
62 OP_ENDPTSETUPSTAT,
63 OP_ENDPTPRIME,
64 OP_ENDPTFLUSH,
65 OP_ENDPTSTAT,
66 OP_ENDPTCOMPLETE,
67 OP_ENDPTCTRL,
68 /* endptctrl1..15 follow */
69 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
70 };
71
72 /******************************************************************************
73 * STRUCTURES
74 *****************************************************************************/
75 /**
76 * struct ci_hw_ep - endpoint representation
77 * @ep: endpoint structure for gadget drivers
78 * @dir: endpoint direction (TX/RX)
79 * @num: endpoint number
80 * @type: endpoint type
81 * @name: string description of the endpoint
82 * @qh: queue head for this endpoint
83 * @wedge: is the endpoint wedged
84 * @ci: pointer to the controller
85 * @lock: pointer to controller's spinlock
86 * @td_pool: pointer to controller's TD pool
87 */
88 struct ci_hw_ep {
89 struct usb_ep ep;
90 u8 dir;
91 u8 num;
92 u8 type;
93 char name[16];
94 struct {
95 struct list_head queue;
96 struct ci_hw_qh *ptr;
97 dma_addr_t dma;
98 } qh;
99 int wedge;
100
101 /* global resources */
102 struct ci_hdrc *ci;
103 spinlock_t *lock;
104 struct dma_pool *td_pool;
105 struct td_node *pending_td;
106 };
107
108 enum ci_role {
109 CI_ROLE_HOST = 0,
110 CI_ROLE_GADGET,
111 CI_ROLE_END,
112 };
113
114 enum ci_revision {
115 CI_REVISION_1X = 10, /* Revision 1.x */
116 CI_REVISION_20 = 20, /* Revision 2.0 */
117 CI_REVISION_21, /* Revision 2.1 */
118 CI_REVISION_22, /* Revision 2.2 */
119 CI_REVISION_23, /* Revision 2.3 */
120 CI_REVISION_24, /* Revision 2.4 */
121 CI_REVISION_25, /* Revision 2.5 */
122 CI_REVISION_25_PLUS, /* Revision above than 2.5 */
123 CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
124 };
125
126 /**
127 * struct ci_role_driver - host/gadget role driver
128 * @start: start this role
129 * @stop: stop this role
130 * @irq: irq handler for this role
131 * @name: role name string (host/gadget)
132 */
133 struct ci_role_driver {
134 int (*start)(struct ci_hdrc *);
135 void (*stop)(struct ci_hdrc *);
136 irqreturn_t (*irq)(struct ci_hdrc *);
137 const char *name;
138 };
139
140 /**
141 * struct hw_bank - hardware register mapping representation
142 * @lpm: set if the device is LPM capable
143 * @phys: physical address of the controller's registers
144 * @abs: absolute address of the beginning of register window
145 * @cap: capability registers
146 * @op: operational registers
147 * @size: size of the register window
148 * @regmap: register lookup table
149 */
150 struct hw_bank {
151 unsigned lpm;
152 resource_size_t phys;
153 void __iomem *abs;
154 void __iomem *cap;
155 void __iomem *op;
156 size_t size;
157 void __iomem *regmap[OP_LAST + 1];
158 };
159
160 /**
161 * struct ci_hdrc - chipidea device representation
162 * @dev: pointer to parent device
163 * @lock: access synchronization
164 * @hw_bank: hardware register mapping
165 * @irq: IRQ number
166 * @roles: array of supported roles for this controller
167 * @role: current role
168 * @is_otg: if the device is otg-capable
169 * @fsm: otg finite state machine
170 * @otg_fsm_hrtimer: hrtimer for otg fsm timers
171 * @hr_timeouts: time out list for active otg fsm timers
172 * @enabled_otg_timer_bits: bits of enabled otg timers
173 * @next_otg_timer: next nearest enabled timer to be expired
174 * @work: work for role changing
175 * @wq: workqueue thread
176 * @qh_pool: allocation pool for queue heads
177 * @td_pool: allocation pool for transfer descriptors
178 * @gadget: device side representation for peripheral controller
179 * @driver: gadget driver
180 * @resume_state: save the state of gadget suspend from
181 * @hw_ep_max: total number of endpoints supported by hardware
182 * @ci_hw_ep: array of endpoints
183 * @ep0_dir: ep0 direction
184 * @ep0out: pointer to ep0 OUT endpoint
185 * @ep0in: pointer to ep0 IN endpoint
186 * @status: ep0 status request
187 * @setaddr: if we should set the address on status completion
188 * @address: usb address received from the host
189 * @remote_wakeup: host-enabled remote wakeup
190 * @suspended: suspended by host
191 * @test_mode: the selected test mode
192 * @platdata: platform specific information supplied by parent device
193 * @vbus_active: is VBUS active
194 * @ulpi: pointer to ULPI device, if any
195 * @ulpi_ops: ULPI read/write ops for this device
196 * @phy: pointer to PHY, if any
197 * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
198 * @hcd: pointer to usb_hcd for ehci host driver
199 * @id_event: indicates there is an id event, and handled at ci_otg_work
200 * @b_sess_valid_event: indicates there is a vbus event, and handled
201 * at ci_otg_work
202 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
203 * @supports_runtime_pm: if runtime pm is supported
204 * @in_lpm: if the core in low power mode
205 * @wakeup_int: if wakeup interrupt occur
206 * @rev: The revision number for controller
207 */
208 struct ci_hdrc {
209 struct device *dev;
210 spinlock_t lock;
211 struct hw_bank hw_bank;
212 int irq;
213 struct ci_role_driver *roles[CI_ROLE_END];
214 enum ci_role role;
215 bool is_otg;
216 struct usb_otg otg;
217 struct otg_fsm fsm;
218 struct hrtimer otg_fsm_hrtimer;
219 ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS];
220 unsigned enabled_otg_timer_bits;
221 enum otg_fsm_timer next_otg_timer;
222 struct usb_role_switch *role_switch;
223 struct work_struct work;
224 struct workqueue_struct *wq;
225
226 struct dma_pool *qh_pool;
227 struct dma_pool *td_pool;
228
229 struct usb_gadget gadget;
230 struct usb_gadget_driver *driver;
231 enum usb_device_state resume_state;
232 unsigned hw_ep_max;
233 struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
234 u32 ep0_dir;
235 struct ci_hw_ep *ep0out, *ep0in;
236
237 struct usb_request *status;
238 bool setaddr;
239 u8 address;
240 u8 remote_wakeup;
241 u8 suspended;
242 u8 test_mode;
243
244 struct ci_hdrc_platform_data *platdata;
245 int vbus_active;
246 struct ulpi *ulpi;
247 struct ulpi_ops ulpi_ops;
248 struct phy *phy;
249 /* old usb_phy interface */
250 struct usb_phy *usb_phy;
251 struct usb_hcd *hcd;
252 bool id_event;
253 bool b_sess_valid_event;
254 bool imx28_write_fix;
255 bool supports_runtime_pm;
256 bool in_lpm;
257 bool wakeup_int;
258 enum ci_revision rev;
259 };
260
ci_role(struct ci_hdrc * ci)261 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
262 {
263 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
264 return ci->roles[ci->role];
265 }
266
ci_role_start(struct ci_hdrc * ci,enum ci_role role)267 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
268 {
269 int ret;
270
271 if (role >= CI_ROLE_END)
272 return -EINVAL;
273
274 if (!ci->roles[role])
275 return -ENXIO;
276
277 ret = ci->roles[role]->start(ci);
278 if (!ret)
279 ci->role = role;
280 return ret;
281 }
282
ci_role_stop(struct ci_hdrc * ci)283 static inline void ci_role_stop(struct ci_hdrc *ci)
284 {
285 enum ci_role role = ci->role;
286
287 if (role == CI_ROLE_END)
288 return;
289
290 ci->role = CI_ROLE_END;
291
292 ci->roles[role]->stop(ci);
293 }
294
ci_role_to_usb_role(struct ci_hdrc * ci)295 static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
296 {
297 if (ci->role == CI_ROLE_HOST)
298 return USB_ROLE_HOST;
299 else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
300 return USB_ROLE_DEVICE;
301 else
302 return USB_ROLE_NONE;
303 }
304
usb_role_to_ci_role(enum usb_role role)305 static inline enum ci_role usb_role_to_ci_role(enum usb_role role)
306 {
307 if (role == USB_ROLE_HOST)
308 return CI_ROLE_HOST;
309 else if (role == USB_ROLE_DEVICE)
310 return CI_ROLE_GADGET;
311 else
312 return CI_ROLE_END;
313 }
314
315 /**
316 * hw_read_id_reg: reads from a identification register
317 * @ci: the controller
318 * @offset: offset from the beginning of identification registers region
319 * @mask: bitfield mask
320 *
321 * This function returns register contents
322 */
hw_read_id_reg(struct ci_hdrc * ci,u32 offset,u32 mask)323 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
324 {
325 return ioread32(ci->hw_bank.abs + offset) & mask;
326 }
327
328 /**
329 * hw_write_id_reg: writes to a identification register
330 * @ci: the controller
331 * @offset: offset from the beginning of identification registers region
332 * @mask: bitfield mask
333 * @data: new value
334 */
hw_write_id_reg(struct ci_hdrc * ci,u32 offset,u32 mask,u32 data)335 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
336 u32 mask, u32 data)
337 {
338 if (~mask)
339 data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
340 | (data & mask);
341
342 iowrite32(data, ci->hw_bank.abs + offset);
343 }
344
345 /**
346 * hw_read: reads from a hw register
347 * @ci: the controller
348 * @reg: register index
349 * @mask: bitfield mask
350 *
351 * This function returns register contents
352 */
hw_read(struct ci_hdrc * ci,enum ci_hw_regs reg,u32 mask)353 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
354 {
355 return ioread32(ci->hw_bank.regmap[reg]) & mask;
356 }
357
358 #ifdef CONFIG_SOC_IMX28
imx28_ci_writel(u32 val,volatile void __iomem * addr)359 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
360 {
361 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
362 }
363 #else
imx28_ci_writel(u32 val,volatile void __iomem * addr)364 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
365 {
366 }
367 #endif
368
__hw_write(struct ci_hdrc * ci,u32 val,void __iomem * addr)369 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
370 void __iomem *addr)
371 {
372 if (ci->imx28_write_fix)
373 imx28_ci_writel(val, addr);
374 else
375 iowrite32(val, addr);
376 }
377
378 /**
379 * hw_write: writes to a hw register
380 * @ci: the controller
381 * @reg: register index
382 * @mask: bitfield mask
383 * @data: new value
384 */
hw_write(struct ci_hdrc * ci,enum ci_hw_regs reg,u32 mask,u32 data)385 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
386 u32 mask, u32 data)
387 {
388 if (~mask)
389 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
390 | (data & mask);
391
392 __hw_write(ci, data, ci->hw_bank.regmap[reg]);
393 }
394
395 /**
396 * hw_test_and_clear: tests & clears a hw register
397 * @ci: the controller
398 * @reg: register index
399 * @mask: bitfield mask
400 *
401 * This function returns register contents
402 */
hw_test_and_clear(struct ci_hdrc * ci,enum ci_hw_regs reg,u32 mask)403 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
404 u32 mask)
405 {
406 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
407
408 __hw_write(ci, val, ci->hw_bank.regmap[reg]);
409 return val;
410 }
411
412 /**
413 * hw_test_and_write: tests & writes a hw register
414 * @ci: the controller
415 * @reg: register index
416 * @mask: bitfield mask
417 * @data: new value
418 *
419 * This function returns register contents
420 */
hw_test_and_write(struct ci_hdrc * ci,enum ci_hw_regs reg,u32 mask,u32 data)421 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
422 u32 mask, u32 data)
423 {
424 u32 val = hw_read(ci, reg, ~0);
425
426 hw_write(ci, reg, mask, data);
427 return (val & mask) >> __ffs(mask);
428 }
429
430 /**
431 * ci_otg_is_fsm_mode: runtime check if otg controller
432 * is in otg fsm mode.
433 *
434 * @ci: chipidea device
435 */
ci_otg_is_fsm_mode(struct ci_hdrc * ci)436 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
437 {
438 #ifdef CONFIG_USB_OTG_FSM
439 struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
440
441 return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
442 ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
443 otg_caps->hnp_support || otg_caps->adp_support);
444 #else
445 return false;
446 #endif
447 }
448
449 int ci_ulpi_init(struct ci_hdrc *ci);
450 void ci_ulpi_exit(struct ci_hdrc *ci);
451 int ci_ulpi_resume(struct ci_hdrc *ci);
452
453 u32 hw_read_intr_enable(struct ci_hdrc *ci);
454
455 u32 hw_read_intr_status(struct ci_hdrc *ci);
456
457 int hw_device_reset(struct ci_hdrc *ci);
458
459 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
460
461 u8 hw_port_test_get(struct ci_hdrc *ci);
462
463 void hw_phymode_configure(struct ci_hdrc *ci);
464
465 void ci_platform_configure(struct ci_hdrc *ci);
466
467 void dbg_create_files(struct ci_hdrc *ci);
468
469 void dbg_remove_files(struct ci_hdrc *ci);
470 #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
471