1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Comtrol RocketPort EXPRESS/INFINITY cards
4 *
5 * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
6 *
7 * Inspired by, and loosely based on:
8 *
9 * ar933x_uart.c
10 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
11 *
12 * rocketport_infinity_express-linux-1.20.tar.gz
13 * Copyright (C) 2004-2011 Comtrol, Inc.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/compiler.h>
18 #include <linux/completion.h>
19 #include <linux/console.h>
20 #include <linux/delay.h>
21 #include <linux/firmware.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/ioport.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/log2.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/serial.h>
31 #include <linux/serial_core.h>
32 #include <linux/slab.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/types.h>
37
38 #define DRV_NAME "rp2"
39
40 #define RP2_FW_NAME "rp2.fw"
41 #define RP2_UCODE_BYTES 0x3f
42
43 #define PORTS_PER_ASIC 16
44 #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
45
46 #define UART_CLOCK 44236800
47 #define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16))
48 #define FIFO_SIZE 512
49
50 /* BAR0 registers */
51 #define RP2_FPGA_CTL0 0x110
52 #define RP2_FPGA_CTL1 0x11c
53 #define RP2_IRQ_MASK 0x1ec
54 #define RP2_IRQ_MASK_EN_m BIT(0)
55 #define RP2_IRQ_STATUS 0x1f0
56
57 /* BAR1 registers */
58 #define RP2_ASIC_SPACING 0x1000
59 #define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING))
60
61 #define RP2_PORT_BASE 0x000
62 #define RP2_PORT_SPACING 0x040
63
64 #define RP2_UCODE_BASE 0x400
65 #define RP2_UCODE_SPACING 0x80
66
67 #define RP2_CLK_PRESCALER 0xc00
68 #define RP2_CH_IRQ_STAT 0xc04
69 #define RP2_CH_IRQ_MASK 0xc08
70 #define RP2_ASIC_IRQ 0xd00
71 #define RP2_ASIC_IRQ_EN_m BIT(20)
72 #define RP2_GLOBAL_CMD 0xd0c
73 #define RP2_ASIC_CFG 0xd04
74
75 /* port registers */
76 #define RP2_DATA_DWORD 0x000
77
78 #define RP2_DATA_BYTE 0x008
79 #define RP2_DATA_BYTE_ERR_PARITY_m BIT(8)
80 #define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
81 #define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
82 #define RP2_DATA_BYTE_BREAK_m BIT(11)
83
84 /* This lets uart_insert_char() drop bytes received on a !CREAD port */
85 #define RP2_DUMMY_READ BIT(16)
86
87 #define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \
88 RP2_DATA_BYTE_ERR_OVERRUN_m | \
89 RP2_DATA_BYTE_ERR_FRAMING_m | \
90 RP2_DATA_BYTE_BREAK_m)
91
92 #define RP2_RX_FIFO_COUNT 0x00c
93 #define RP2_TX_FIFO_COUNT 0x00e
94
95 #define RP2_CHAN_STAT 0x010
96 #define RP2_CHAN_STAT_RXDATA_m BIT(0)
97 #define RP2_CHAN_STAT_DCD_m BIT(3)
98 #define RP2_CHAN_STAT_DSR_m BIT(4)
99 #define RP2_CHAN_STAT_CTS_m BIT(5)
100 #define RP2_CHAN_STAT_RI_m BIT(6)
101 #define RP2_CHAN_STAT_OVERRUN_m BIT(13)
102 #define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
103 #define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
104 #define RP2_CHAN_STAT_CD_CHANGED_m BIT(18)
105 #define RP2_CHAN_STAT_RI_CHANGED_m BIT(22)
106 #define RP2_CHAN_STAT_TXEMPTY_m BIT(25)
107
108 #define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \
109 RP2_CHAN_STAT_CTS_CHANGED_m | \
110 RP2_CHAN_STAT_CD_CHANGED_m | \
111 RP2_CHAN_STAT_RI_CHANGED_m)
112
113 #define RP2_TXRX_CTL 0x014
114 #define RP2_TXRX_CTL_MSRIRQ_m BIT(0)
115 #define RP2_TXRX_CTL_RXIRQ_m BIT(2)
116 #define RP2_TXRX_CTL_RX_TRIG_s 3
117 #define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
118 #define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
119 #define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
120 #define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
121 #define RP2_TXRX_CTL_RX_EN_m BIT(5)
122 #define RP2_TXRX_CTL_RTSFLOW_m BIT(6)
123 #define RP2_TXRX_CTL_DTRFLOW_m BIT(7)
124 #define RP2_TXRX_CTL_TX_TRIG_s 16
125 #define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
126 #define RP2_TXRX_CTL_DSRFLOW_m BIT(18)
127 #define RP2_TXRX_CTL_TXIRQ_m BIT(19)
128 #define RP2_TXRX_CTL_CTSFLOW_m BIT(23)
129 #define RP2_TXRX_CTL_TX_EN_m BIT(24)
130 #define RP2_TXRX_CTL_RTS_m BIT(25)
131 #define RP2_TXRX_CTL_DTR_m BIT(26)
132 #define RP2_TXRX_CTL_LOOP_m BIT(27)
133 #define RP2_TXRX_CTL_BREAK_m BIT(28)
134 #define RP2_TXRX_CTL_CMSPAR_m BIT(29)
135 #define RP2_TXRX_CTL_nPARODD_m BIT(30)
136 #define RP2_TXRX_CTL_PARENB_m BIT(31)
137
138 #define RP2_UART_CTL 0x018
139 #define RP2_UART_CTL_MODE_s 0
140 #define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s)
141 #define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s)
142 #define RP2_UART_CTL_FLUSH_RX_m BIT(3)
143 #define RP2_UART_CTL_FLUSH_TX_m BIT(4)
144 #define RP2_UART_CTL_RESET_CH_m BIT(5)
145 #define RP2_UART_CTL_XMIT_EN_m BIT(6)
146 #define RP2_UART_CTL_DATABITS_s 8
147 #define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s)
148 #define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s)
149 #define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s)
150 #define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s)
151 #define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s)
152 #define RP2_UART_CTL_STOPBITS_m BIT(10)
153
154 #define RP2_BAUD 0x01c
155
156 /* ucode registers */
157 #define RP2_TX_SWFLOW 0x02
158 #define RP2_TX_SWFLOW_ena 0x81
159 #define RP2_TX_SWFLOW_dis 0x9d
160
161 #define RP2_RX_SWFLOW 0x0c
162 #define RP2_RX_SWFLOW_ena 0x81
163 #define RP2_RX_SWFLOW_dis 0x8d
164
165 #define RP2_RX_FIFO 0x37
166 #define RP2_RX_FIFO_ena 0x08
167 #define RP2_RX_FIFO_dis 0x81
168
169 static struct uart_driver rp2_uart_driver = {
170 .owner = THIS_MODULE,
171 .driver_name = DRV_NAME,
172 .dev_name = "ttyRP",
173 .nr = CONFIG_SERIAL_RP2_NR_UARTS,
174 };
175
176 struct rp2_card;
177
178 struct rp2_uart_port {
179 struct uart_port port;
180 int idx;
181 int ignore_rx;
182 struct rp2_card *card;
183 void __iomem *asic_base;
184 void __iomem *base;
185 void __iomem *ucode;
186 };
187
188 struct rp2_card {
189 struct pci_dev *pdev;
190 struct rp2_uart_port *ports;
191 int n_ports;
192 int initialized_ports;
193 int minor_start;
194 int smpte;
195 void __iomem *bar0;
196 void __iomem *bar1;
197 spinlock_t card_lock;
198 };
199
200 #define RP_ID(prod) PCI_VDEVICE(RP, (prod))
201 #define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
202
rp2_decode_cap(const struct pci_device_id * id,int * ports,int * smpte)203 static inline void rp2_decode_cap(const struct pci_device_id *id,
204 int *ports, int *smpte)
205 {
206 *ports = id->driver_data >> 8;
207 *smpte = id->driver_data & 0xff;
208 }
209
210 static DEFINE_SPINLOCK(rp2_minor_lock);
211 static int rp2_minor_next;
212
rp2_alloc_ports(int n_ports)213 static int rp2_alloc_ports(int n_ports)
214 {
215 int ret = -ENOSPC;
216
217 spin_lock(&rp2_minor_lock);
218 if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) {
219 /* sorry, no support for hot unplugging individual cards */
220 ret = rp2_minor_next;
221 rp2_minor_next += n_ports;
222 }
223 spin_unlock(&rp2_minor_lock);
224
225 return ret;
226 }
227
port_to_up(struct uart_port * port)228 static inline struct rp2_uart_port *port_to_up(struct uart_port *port)
229 {
230 return container_of(port, struct rp2_uart_port, port);
231 }
232
rp2_rmw(struct rp2_uart_port * up,int reg,u32 clr_bits,u32 set_bits)233 static void rp2_rmw(struct rp2_uart_port *up, int reg,
234 u32 clr_bits, u32 set_bits)
235 {
236 u32 tmp = readl(up->base + reg);
237 tmp &= ~clr_bits;
238 tmp |= set_bits;
239 writel(tmp, up->base + reg);
240 }
241
rp2_rmw_clr(struct rp2_uart_port * up,int reg,u32 val)242 static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)
243 {
244 rp2_rmw(up, reg, val, 0);
245 }
246
rp2_rmw_set(struct rp2_uart_port * up,int reg,u32 val)247 static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)
248 {
249 rp2_rmw(up, reg, 0, val);
250 }
251
rp2_mask_ch_irq(struct rp2_uart_port * up,int ch_num,int is_enabled)252 static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,
253 int is_enabled)
254 {
255 unsigned long flags, irq_mask;
256
257 spin_lock_irqsave(&up->card->card_lock, flags);
258
259 irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);
260 if (is_enabled)
261 irq_mask &= ~BIT(ch_num);
262 else
263 irq_mask |= BIT(ch_num);
264 writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
265
266 spin_unlock_irqrestore(&up->card->card_lock, flags);
267 }
268
rp2_uart_tx_empty(struct uart_port * port)269 static unsigned int rp2_uart_tx_empty(struct uart_port *port)
270 {
271 struct rp2_uart_port *up = port_to_up(port);
272 unsigned long tx_fifo_bytes, flags;
273
274 /*
275 * This should probably check the transmitter, not the FIFO.
276 * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is
277 * enabled.
278 */
279 spin_lock_irqsave(&up->port.lock, flags);
280 tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);
281 spin_unlock_irqrestore(&up->port.lock, flags);
282
283 return tx_fifo_bytes ? 0 : TIOCSER_TEMT;
284 }
285
rp2_uart_get_mctrl(struct uart_port * port)286 static unsigned int rp2_uart_get_mctrl(struct uart_port *port)
287 {
288 struct rp2_uart_port *up = port_to_up(port);
289 u32 status;
290
291 status = readl(up->base + RP2_CHAN_STAT);
292 return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) |
293 ((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) |
294 ((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) |
295 ((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0);
296 }
297
rp2_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)298 static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
299 {
300 rp2_rmw(port_to_up(port), RP2_TXRX_CTL,
301 RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m,
302 ((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) |
303 ((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) |
304 ((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0));
305 }
306
rp2_uart_start_tx(struct uart_port * port)307 static void rp2_uart_start_tx(struct uart_port *port)
308 {
309 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
310 }
311
rp2_uart_stop_tx(struct uart_port * port)312 static void rp2_uart_stop_tx(struct uart_port *port)
313 {
314 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
315 }
316
rp2_uart_stop_rx(struct uart_port * port)317 static void rp2_uart_stop_rx(struct uart_port *port)
318 {
319 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m);
320 }
321
rp2_uart_break_ctl(struct uart_port * port,int break_state)322 static void rp2_uart_break_ctl(struct uart_port *port, int break_state)
323 {
324 unsigned long flags;
325
326 spin_lock_irqsave(&port->lock, flags);
327 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m,
328 break_state ? RP2_TXRX_CTL_BREAK_m : 0);
329 spin_unlock_irqrestore(&port->lock, flags);
330 }
331
rp2_uart_enable_ms(struct uart_port * port)332 static void rp2_uart_enable_ms(struct uart_port *port)
333 {
334 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m);
335 }
336
__rp2_uart_set_termios(struct rp2_uart_port * up,unsigned long cfl,unsigned long ifl,unsigned int baud_div)337 static void __rp2_uart_set_termios(struct rp2_uart_port *up,
338 unsigned long cfl,
339 unsigned long ifl,
340 unsigned int baud_div)
341 {
342 /* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */
343 writew(baud_div - 1, up->base + RP2_BAUD);
344
345 /* data bits and stop bits */
346 rp2_rmw(up, RP2_UART_CTL,
347 RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m,
348 ((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) |
349 (((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) |
350 (((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) |
351 (((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) |
352 (((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0));
353
354 /* parity and hardware flow control */
355 rp2_rmw(up, RP2_TXRX_CTL,
356 RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m |
357 RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m |
358 RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m |
359 RP2_TXRX_CTL_CTSFLOW_m,
360 ((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) |
361 ((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) |
362 ((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) |
363 ((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m |
364 RP2_TXRX_CTL_CTSFLOW_m) : 0));
365
366 /* XON/XOFF software flow control */
367 writeb((ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis,
368 up->ucode + RP2_TX_SWFLOW);
369 writeb((ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis,
370 up->ucode + RP2_RX_SWFLOW);
371 }
372
rp2_uart_set_termios(struct uart_port * port,struct ktermios * new,const struct ktermios * old)373 static void rp2_uart_set_termios(struct uart_port *port, struct ktermios *new,
374 const struct ktermios *old)
375 {
376 struct rp2_uart_port *up = port_to_up(port);
377 unsigned long flags;
378 unsigned int baud, baud_div;
379
380 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
381 baud_div = uart_get_divisor(port, baud);
382
383 if (tty_termios_baud_rate(new))
384 tty_termios_encode_baud_rate(new, baud, baud);
385
386 spin_lock_irqsave(&port->lock, flags);
387
388 /* ignore all characters if CREAD is not set */
389 port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ;
390
391 __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);
392 uart_update_timeout(port, new->c_cflag, baud);
393
394 spin_unlock_irqrestore(&port->lock, flags);
395 }
396
rp2_rx_chars(struct rp2_uart_port * up)397 static void rp2_rx_chars(struct rp2_uart_port *up)
398 {
399 u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);
400 struct tty_port *port = &up->port.state->port;
401
402 for (; bytes != 0; bytes--) {
403 u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;
404 char ch = byte & 0xff;
405
406 if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) {
407 if (!uart_handle_sysrq_char(&up->port, ch))
408 uart_insert_char(&up->port, byte, 0, ch,
409 TTY_NORMAL);
410 } else {
411 char flag = TTY_NORMAL;
412
413 if (byte & RP2_DATA_BYTE_BREAK_m)
414 flag = TTY_BREAK;
415 else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m)
416 flag = TTY_FRAME;
417 else if (byte & RP2_DATA_BYTE_ERR_PARITY_m)
418 flag = TTY_PARITY;
419 uart_insert_char(&up->port, byte,
420 RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag);
421 }
422 up->port.icount.rx++;
423 }
424
425 tty_flip_buffer_push(port);
426 }
427
rp2_tx_chars(struct rp2_uart_port * up)428 static void rp2_tx_chars(struct rp2_uart_port *up)
429 {
430 u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT);
431 struct circ_buf *xmit = &up->port.state->xmit;
432
433 if (uart_tx_stopped(&up->port)) {
434 rp2_uart_stop_tx(&up->port);
435 return;
436 }
437
438 for (; max_tx != 0; max_tx--) {
439 if (up->port.x_char) {
440 writeb(up->port.x_char, up->base + RP2_DATA_BYTE);
441 up->port.x_char = 0;
442 up->port.icount.tx++;
443 continue;
444 }
445 if (uart_circ_empty(xmit)) {
446 rp2_uart_stop_tx(&up->port);
447 break;
448 }
449 writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE);
450 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
451 up->port.icount.tx++;
452 }
453
454 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
455 uart_write_wakeup(&up->port);
456 }
457
rp2_ch_interrupt(struct rp2_uart_port * up)458 static void rp2_ch_interrupt(struct rp2_uart_port *up)
459 {
460 u32 status;
461
462 spin_lock(&up->port.lock);
463
464 /*
465 * The IRQ status bits are clear-on-write. Other status bits in
466 * this register aren't, so it's harmless to write to them.
467 */
468 status = readl(up->base + RP2_CHAN_STAT);
469 writel(status, up->base + RP2_CHAN_STAT);
470
471 if (status & RP2_CHAN_STAT_RXDATA_m)
472 rp2_rx_chars(up);
473 if (status & RP2_CHAN_STAT_TXEMPTY_m)
474 rp2_tx_chars(up);
475 if (status & RP2_CHAN_STAT_MS_CHANGED_MASK)
476 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
477
478 spin_unlock(&up->port.lock);
479 }
480
rp2_asic_interrupt(struct rp2_card * card,unsigned int asic_id)481 static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id)
482 {
483 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
484 int ch, handled = 0;
485 unsigned long status = readl(base + RP2_CH_IRQ_STAT) &
486 ~readl(base + RP2_CH_IRQ_MASK);
487
488 for_each_set_bit(ch, &status, PORTS_PER_ASIC) {
489 rp2_ch_interrupt(&card->ports[ch]);
490 handled++;
491 }
492 return handled;
493 }
494
rp2_uart_interrupt(int irq,void * dev_id)495 static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id)
496 {
497 struct rp2_card *card = dev_id;
498 int handled;
499
500 handled = rp2_asic_interrupt(card, 0);
501 if (card->n_ports >= PORTS_PER_ASIC)
502 handled += rp2_asic_interrupt(card, 1);
503
504 return handled ? IRQ_HANDLED : IRQ_NONE;
505 }
506
rp2_flush_fifos(struct rp2_uart_port * up)507 static inline void rp2_flush_fifos(struct rp2_uart_port *up)
508 {
509 rp2_rmw_set(up, RP2_UART_CTL,
510 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
511 readl(up->base + RP2_UART_CTL);
512 udelay(10);
513 rp2_rmw_clr(up, RP2_UART_CTL,
514 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
515 }
516
rp2_uart_startup(struct uart_port * port)517 static int rp2_uart_startup(struct uart_port *port)
518 {
519 struct rp2_uart_port *up = port_to_up(port);
520
521 rp2_flush_fifos(up);
522 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m);
523 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m,
524 RP2_TXRX_CTL_RX_TRIG_1);
525 rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
526 rp2_mask_ch_irq(up, up->idx, 1);
527
528 return 0;
529 }
530
rp2_uart_shutdown(struct uart_port * port)531 static void rp2_uart_shutdown(struct uart_port *port)
532 {
533 struct rp2_uart_port *up = port_to_up(port);
534 unsigned long flags;
535
536 rp2_uart_break_ctl(port, 0);
537
538 spin_lock_irqsave(&port->lock, flags);
539 rp2_mask_ch_irq(up, up->idx, 0);
540 rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
541 spin_unlock_irqrestore(&port->lock, flags);
542 }
543
rp2_uart_type(struct uart_port * port)544 static const char *rp2_uart_type(struct uart_port *port)
545 {
546 return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL;
547 }
548
rp2_uart_release_port(struct uart_port * port)549 static void rp2_uart_release_port(struct uart_port *port)
550 {
551 /* Nothing to release ... */
552 }
553
rp2_uart_request_port(struct uart_port * port)554 static int rp2_uart_request_port(struct uart_port *port)
555 {
556 /* UARTs always present */
557 return 0;
558 }
559
rp2_uart_config_port(struct uart_port * port,int flags)560 static void rp2_uart_config_port(struct uart_port *port, int flags)
561 {
562 if (flags & UART_CONFIG_TYPE)
563 port->type = PORT_RP2;
564 }
565
rp2_uart_verify_port(struct uart_port * port,struct serial_struct * ser)566 static int rp2_uart_verify_port(struct uart_port *port,
567 struct serial_struct *ser)
568 {
569 if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2)
570 return -EINVAL;
571
572 return 0;
573 }
574
575 static const struct uart_ops rp2_uart_ops = {
576 .tx_empty = rp2_uart_tx_empty,
577 .set_mctrl = rp2_uart_set_mctrl,
578 .get_mctrl = rp2_uart_get_mctrl,
579 .stop_tx = rp2_uart_stop_tx,
580 .start_tx = rp2_uart_start_tx,
581 .stop_rx = rp2_uart_stop_rx,
582 .enable_ms = rp2_uart_enable_ms,
583 .break_ctl = rp2_uart_break_ctl,
584 .startup = rp2_uart_startup,
585 .shutdown = rp2_uart_shutdown,
586 .set_termios = rp2_uart_set_termios,
587 .type = rp2_uart_type,
588 .release_port = rp2_uart_release_port,
589 .request_port = rp2_uart_request_port,
590 .config_port = rp2_uart_config_port,
591 .verify_port = rp2_uart_verify_port,
592 };
593
rp2_reset_asic(struct rp2_card * card,unsigned int asic_id)594 static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id)
595 {
596 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
597 u32 clk_cfg;
598
599 writew(1, base + RP2_GLOBAL_CMD);
600 readw(base + RP2_GLOBAL_CMD);
601 msleep(100);
602 writel(0, base + RP2_CLK_PRESCALER);
603
604 /* TDM clock configuration */
605 clk_cfg = readw(base + RP2_ASIC_CFG);
606 clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9);
607 writew(clk_cfg, base + RP2_ASIC_CFG);
608
609 /* IRQ routing */
610 writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
611 writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
612 }
613
rp2_init_card(struct rp2_card * card)614 static void rp2_init_card(struct rp2_card *card)
615 {
616 writel(4, card->bar0 + RP2_FPGA_CTL0);
617 writel(0, card->bar0 + RP2_FPGA_CTL1);
618
619 rp2_reset_asic(card, 0);
620 if (card->n_ports >= PORTS_PER_ASIC)
621 rp2_reset_asic(card, 1);
622
623 writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);
624 }
625
rp2_init_port(struct rp2_uart_port * up,const struct firmware * fw)626 static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw)
627 {
628 int i;
629
630 writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
631 readl(up->base + RP2_UART_CTL);
632 udelay(1);
633
634 writel(0, up->base + RP2_TXRX_CTL);
635 writel(0, up->base + RP2_UART_CTL);
636 readl(up->base + RP2_UART_CTL);
637 udelay(1);
638
639 rp2_flush_fifos(up);
640
641 for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++)
642 writeb(fw->data[i], up->ucode + i);
643
644 __rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV);
645 rp2_uart_set_mctrl(&up->port, 0);
646
647 writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);
648 rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m,
649 RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232);
650 rp2_rmw_set(up, RP2_TXRX_CTL,
651 RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m);
652 }
653
rp2_remove_ports(struct rp2_card * card)654 static void rp2_remove_ports(struct rp2_card *card)
655 {
656 int i;
657
658 for (i = 0; i < card->initialized_ports; i++)
659 uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port);
660 card->initialized_ports = 0;
661 }
662
rp2_load_firmware(struct rp2_card * card,const struct firmware * fw)663 static int rp2_load_firmware(struct rp2_card *card, const struct firmware *fw)
664 {
665 resource_size_t phys_base;
666 int i, rc = 0;
667
668 phys_base = pci_resource_start(card->pdev, 1);
669
670 for (i = 0; i < card->n_ports; i++) {
671 struct rp2_uart_port *rp = &card->ports[i];
672 struct uart_port *p;
673 int j = (unsigned)i % PORTS_PER_ASIC;
674
675 rp->asic_base = card->bar1;
676 rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;
677 rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING;
678 rp->card = card;
679 rp->idx = j;
680
681 p = &rp->port;
682 p->line = card->minor_start + i;
683 p->dev = &card->pdev->dev;
684 p->type = PORT_RP2;
685 p->iotype = UPIO_MEM32;
686 p->uartclk = UART_CLOCK;
687 p->regshift = 2;
688 p->fifosize = FIFO_SIZE;
689 p->ops = &rp2_uart_ops;
690 p->irq = card->pdev->irq;
691 p->membase = rp->base;
692 p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING;
693
694 if (i >= PORTS_PER_ASIC) {
695 rp->asic_base += RP2_ASIC_SPACING;
696 rp->base += RP2_ASIC_SPACING;
697 rp->ucode += RP2_ASIC_SPACING;
698 p->mapbase += RP2_ASIC_SPACING;
699 }
700
701 rp2_init_port(rp, fw);
702 rc = uart_add_one_port(&rp2_uart_driver, p);
703 if (rc) {
704 dev_err(&card->pdev->dev,
705 "error registering port %d: %d\n", i, rc);
706 rp2_remove_ports(card);
707 break;
708 }
709 card->initialized_ports++;
710 }
711
712 return rc;
713 }
714
rp2_probe(struct pci_dev * pdev,const struct pci_device_id * id)715 static int rp2_probe(struct pci_dev *pdev,
716 const struct pci_device_id *id)
717 {
718 const struct firmware *fw;
719 struct rp2_card *card;
720 struct rp2_uart_port *ports;
721 void __iomem * const *bars;
722 int rc;
723
724 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
725 if (!card)
726 return -ENOMEM;
727 pci_set_drvdata(pdev, card);
728 spin_lock_init(&card->card_lock);
729
730 rc = pcim_enable_device(pdev);
731 if (rc)
732 return rc;
733
734 rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME);
735 if (rc)
736 return rc;
737
738 bars = pcim_iomap_table(pdev);
739 card->bar0 = bars[0];
740 card->bar1 = bars[1];
741 card->pdev = pdev;
742
743 rp2_decode_cap(id, &card->n_ports, &card->smpte);
744 dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports);
745
746 card->minor_start = rp2_alloc_ports(card->n_ports);
747 if (card->minor_start < 0) {
748 dev_err(&pdev->dev,
749 "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n");
750 return -EINVAL;
751 }
752
753 rp2_init_card(card);
754
755 ports = devm_kcalloc(&pdev->dev, card->n_ports, sizeof(*ports),
756 GFP_KERNEL);
757 if (!ports)
758 return -ENOMEM;
759 card->ports = ports;
760
761 rc = request_firmware(&fw, RP2_FW_NAME, &pdev->dev);
762 if (rc < 0) {
763 dev_err(&pdev->dev, "cannot find '%s' firmware image\n",
764 RP2_FW_NAME);
765 return rc;
766 }
767
768 rc = rp2_load_firmware(card, fw);
769
770 release_firmware(fw);
771 if (rc < 0)
772 return rc;
773
774 rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt,
775 IRQF_SHARED, DRV_NAME, card);
776 if (rc)
777 return rc;
778
779 return 0;
780 }
781
rp2_remove(struct pci_dev * pdev)782 static void rp2_remove(struct pci_dev *pdev)
783 {
784 struct rp2_card *card = pci_get_drvdata(pdev);
785
786 rp2_remove_ports(card);
787 }
788
789 static const struct pci_device_id rp2_pci_tbl[] = {
790
791 /* RocketPort INFINITY cards */
792
793 { RP_ID(0x0040), RP_CAP(8, 0) }, /* INF Octa, RJ45, selectable */
794 { RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */
795 { RP_ID(0x0042), RP_CAP(8, 0) }, /* INF Octa, ext interface */
796 { RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */
797 { RP_ID(0x0044), RP_CAP(4, 0) }, /* INF Quad, DB, selectable */
798 { RP_ID(0x0045), RP_CAP(8, 0) }, /* INF Octa, DB, selectable */
799 { RP_ID(0x0046), RP_CAP(4, 0) }, /* INF Quad, ext interface */
800 { RP_ID(0x0047), RP_CAP(4, 0) }, /* INF Quad, RJ45 */
801 { RP_ID(0x004a), RP_CAP(4, 0) }, /* INF Plus, Quad */
802 { RP_ID(0x004b), RP_CAP(8, 0) }, /* INF Plus, Octa */
803 { RP_ID(0x004c), RP_CAP(8, 0) }, /* INF III, Octa */
804 { RP_ID(0x004d), RP_CAP(4, 0) }, /* INF III, Quad */
805 { RP_ID(0x004e), RP_CAP(2, 0) }, /* INF Plus, 2, RS232 */
806 { RP_ID(0x004f), RP_CAP(2, 1) }, /* INF Plus, 2, SMPTE */
807 { RP_ID(0x0050), RP_CAP(4, 0) }, /* INF Plus, Quad, RJ45 */
808 { RP_ID(0x0051), RP_CAP(8, 0) }, /* INF Plus, Octa, RJ45 */
809 { RP_ID(0x0052), RP_CAP(8, 1) }, /* INF Octa, SMPTE */
810
811 /* RocketPort EXPRESS cards */
812
813 { RP_ID(0x0060), RP_CAP(8, 0) }, /* EXP Octa, RJ45, selectable */
814 { RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */
815 { RP_ID(0x0062), RP_CAP(8, 0) }, /* EXP Octa, ext interface */
816 { RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */
817 { RP_ID(0x0064), RP_CAP(4, 0) }, /* EXP Quad, DB, selectable */
818 { RP_ID(0x0065), RP_CAP(8, 0) }, /* EXP Octa, DB, selectable */
819 { RP_ID(0x0066), RP_CAP(4, 0) }, /* EXP Quad, ext interface */
820 { RP_ID(0x0067), RP_CAP(4, 0) }, /* EXP Quad, RJ45 */
821 { RP_ID(0x0068), RP_CAP(8, 0) }, /* EXP Octa, RJ11 */
822 { RP_ID(0x0072), RP_CAP(8, 1) }, /* EXP Octa, SMPTE */
823 { }
824 };
825 MODULE_DEVICE_TABLE(pci, rp2_pci_tbl);
826
827 static struct pci_driver rp2_pci_driver = {
828 .name = DRV_NAME,
829 .id_table = rp2_pci_tbl,
830 .probe = rp2_probe,
831 .remove = rp2_remove,
832 };
833
rp2_uart_init(void)834 static int __init rp2_uart_init(void)
835 {
836 int rc;
837
838 rc = uart_register_driver(&rp2_uart_driver);
839 if (rc)
840 return rc;
841
842 rc = pci_register_driver(&rp2_pci_driver);
843 if (rc) {
844 uart_unregister_driver(&rp2_uart_driver);
845 return rc;
846 }
847
848 return 0;
849 }
850
rp2_uart_exit(void)851 static void __exit rp2_uart_exit(void)
852 {
853 pci_unregister_driver(&rp2_pci_driver);
854 uart_unregister_driver(&rp2_uart_driver);
855 }
856
857 module_init(rp2_uart_init);
858 module_exit(rp2_uart_exit);
859
860 MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver");
861 MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>");
862 MODULE_LICENSE("GPL v2");
863 MODULE_FIRMWARE(RP2_FW_NAME);
864