1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
5 *
6 * Modifications for inclusion into the Linux staging tree are
7 * Copyright(c) 2010 Larry Finger. All rights reserved.
8 *
9 * Contact information:
10 * WLAN FAE <wlanfae@realtek.com>
11 * Larry Finger <Larry.Finger@lwfinger.net>
12 *
13 ******************************************************************************/
14 #define _RTL871X_MP_C_
15
16 #include "osdep_service.h"
17 #include "drv_types.h"
18 #include "rtl871x_mp_phy_regdef.h"
19 #include "rtl8712_cmd.h"
20
_init_mp_priv_(struct mp_priv * pmp_priv)21 static void _init_mp_priv_(struct mp_priv *pmp_priv)
22 {
23 pmp_priv->mode = _LOOPBOOK_MODE_;
24 pmp_priv->curr_ch = 1;
25 pmp_priv->curr_modem = MIXED_PHY;
26 pmp_priv->curr_rateidx = 0;
27 pmp_priv->curr_txpoweridx = 0x14;
28 pmp_priv->antenna_tx = ANTENNA_A;
29 pmp_priv->antenna_rx = ANTENNA_AB;
30 pmp_priv->check_mp_pkt = 0;
31 pmp_priv->tx_pktcount = 0;
32 pmp_priv->rx_pktcount = 0;
33 pmp_priv->rx_crcerrpktcount = 0;
34 }
35
init_mp_priv(struct mp_priv * pmp_priv)36 static int init_mp_priv(struct mp_priv *pmp_priv)
37 {
38 int i;
39 struct mp_xmit_frame *pmp_xmitframe;
40
41 _init_mp_priv_(pmp_priv);
42 _init_queue(&pmp_priv->free_mp_xmitqueue);
43 pmp_priv->pallocated_mp_xmitframe_buf = NULL;
44 pmp_priv->pallocated_mp_xmitframe_buf = kmalloc(NR_MP_XMITFRAME *
45 sizeof(struct mp_xmit_frame) + 4,
46 GFP_ATOMIC);
47 if (!pmp_priv->pallocated_mp_xmitframe_buf)
48 return -ENOMEM;
49
50 pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf +
51 4 -
52 ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
53 pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
54 for (i = 0; i < NR_MP_XMITFRAME; i++) {
55 INIT_LIST_HEAD(&(pmp_xmitframe->list));
56 list_add_tail(&(pmp_xmitframe->list),
57 &(pmp_priv->free_mp_xmitqueue.queue));
58 pmp_xmitframe->pkt = NULL;
59 pmp_xmitframe->frame_tag = MP_FRAMETAG;
60 pmp_xmitframe->padapter = pmp_priv->papdater;
61 pmp_xmitframe++;
62 }
63 pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
64 return 0;
65 }
66
free_mp_priv(struct mp_priv * pmp_priv)67 static int free_mp_priv(struct mp_priv *pmp_priv)
68 {
69 kfree(pmp_priv->pallocated_mp_xmitframe_buf);
70 return 0;
71 }
72
mp871xinit(struct _adapter * padapter)73 void mp871xinit(struct _adapter *padapter)
74 {
75 struct mp_priv *pmppriv = &padapter->mppriv;
76
77 pmppriv->papdater = padapter;
78 init_mp_priv(pmppriv);
79 }
80
mp871xdeinit(struct _adapter * padapter)81 void mp871xdeinit(struct _adapter *padapter)
82 {
83 struct mp_priv *pmppriv = &padapter->mppriv;
84
85 free_mp_priv(pmppriv);
86 }
87
88 /*
89 * Special for bb and rf reg read/write
90 */
fw_iocmd_read(struct _adapter * pAdapter,struct IOCMD_STRUCT iocmd)91 static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd)
92 {
93 u32 cmd32 = 0, val32 = 0;
94 u8 iocmd_class = iocmd.cmdclass;
95 u16 iocmd_value = iocmd.value;
96 u8 iocmd_idx = iocmd.index;
97
98 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
99 if (r8712_fw_cmd(pAdapter, cmd32))
100 r8712_fw_cmd_data(pAdapter, &val32, 1);
101 else
102 val32 = 0;
103 return val32;
104 }
105
fw_iocmd_write(struct _adapter * pAdapter,struct IOCMD_STRUCT iocmd,u32 value)106 static u8 fw_iocmd_write(struct _adapter *pAdapter,
107 struct IOCMD_STRUCT iocmd, u32 value)
108 {
109 u32 cmd32 = 0;
110 u8 iocmd_class = iocmd.cmdclass;
111 u32 iocmd_value = iocmd.value;
112 u8 iocmd_idx = iocmd.index;
113
114 r8712_fw_cmd_data(pAdapter, &value, 0);
115 msleep(100);
116 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
117 return r8712_fw_cmd(pAdapter, cmd32);
118 }
119
120 /* offset : 0X800~0XFFF */
r8712_bb_reg_read(struct _adapter * pAdapter,u16 offset)121 u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset)
122 {
123 u8 shift = offset & 0x0003; /* 4 byte access */
124 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */
125 u32 bb_val = 0;
126 struct IOCMD_STRUCT iocmd;
127
128 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
129 iocmd.value = bb_addr;
130 iocmd.index = IOCMD_BB_READ_IDX;
131 bb_val = fw_iocmd_read(pAdapter, iocmd);
132 if (shift != 0) {
133 u32 bb_val2 = 0;
134
135 bb_val >>= (shift * 8);
136 iocmd.value += 4;
137 bb_val2 = fw_iocmd_read(pAdapter, iocmd);
138 bb_val2 <<= ((4 - shift) * 8);
139 bb_val |= bb_val2;
140 }
141 return bb_val;
142 }
143
144 /* offset : 0X800~0XFFF */
r8712_bb_reg_write(struct _adapter * pAdapter,u16 offset,u32 value)145 u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value)
146 {
147 u8 shift = offset & 0x0003; /* 4 byte access */
148 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */
149 struct IOCMD_STRUCT iocmd;
150
151 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
152 iocmd.value = bb_addr;
153 iocmd.index = IOCMD_BB_WRITE_IDX;
154 if (shift != 0) {
155 u32 oldValue = 0;
156 u32 newValue = value;
157
158 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
159 oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8));
160 value = oldValue | (newValue << (shift * 8));
161 if (!fw_iocmd_write(pAdapter, iocmd, value))
162 return false;
163 iocmd.value += 4;
164 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
165 oldValue &= (0xFFFFFFFF << (shift * 8));
166 value = oldValue | (newValue >> ((4 - shift) * 8));
167 }
168 return fw_iocmd_write(pAdapter, iocmd, value);
169 }
170
171 /* offset : 0x00 ~ 0xFF */
r8712_rf_reg_read(struct _adapter * pAdapter,u8 path,u8 offset)172 u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset)
173 {
174 u16 rf_addr = (path << 8) | offset;
175 struct IOCMD_STRUCT iocmd;
176
177 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
178 iocmd.value = rf_addr;
179 iocmd.index = IOCMD_RF_READ_IDX;
180 return fw_iocmd_read(pAdapter, iocmd);
181 }
182
r8712_rf_reg_write(struct _adapter * pAdapter,u8 path,u8 offset,u32 value)183 u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value)
184 {
185 u16 rf_addr = (path << 8) | offset;
186 struct IOCMD_STRUCT iocmd;
187
188 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
189 iocmd.value = rf_addr;
190 iocmd.index = IOCMD_RF_WRIT_IDX;
191 return fw_iocmd_write(pAdapter, iocmd, value);
192 }
193
bitshift(u32 bitmask)194 static u32 bitshift(u32 bitmask)
195 {
196 u32 i;
197
198 for (i = 0; i <= 31; i++)
199 if (((bitmask >> i) & 0x1) == 1)
200 break;
201 return i;
202 }
203
get_bb_reg(struct _adapter * pAdapter,u16 offset,u32 bitmask)204 static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask)
205 {
206 u32 org_value, bit_shift;
207
208 org_value = r8712_bb_reg_read(pAdapter, offset);
209 bit_shift = bitshift(bitmask);
210 return (org_value & bitmask) >> bit_shift;
211 }
212
set_bb_reg(struct _adapter * pAdapter,u16 offset,u32 bitmask,u32 value)213 static u8 set_bb_reg(struct _adapter *pAdapter,
214 u16 offset,
215 u32 bitmask,
216 u32 value)
217 {
218 u32 org_value, bit_shift, new_value;
219
220 if (bitmask != bMaskDWord) {
221 org_value = r8712_bb_reg_read(pAdapter, offset);
222 bit_shift = bitshift(bitmask);
223 new_value = (org_value & (~bitmask)) | (value << bit_shift);
224 } else {
225 new_value = value;
226 }
227 return r8712_bb_reg_write(pAdapter, offset, new_value);
228 }
229
get_rf_reg(struct _adapter * pAdapter,u8 path,u8 offset,u32 bitmask)230 static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
231 u32 bitmask)
232 {
233 u32 org_value, bit_shift;
234
235 org_value = r8712_rf_reg_read(pAdapter, path, offset);
236 bit_shift = bitshift(bitmask);
237 return (org_value & bitmask) >> bit_shift;
238 }
239
set_rf_reg(struct _adapter * pAdapter,u8 path,u8 offset,u32 bitmask,u32 value)240 static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
241 u32 value)
242 {
243 u32 org_value, bit_shift, new_value;
244
245 if (bitmask != bMaskDWord) {
246 org_value = r8712_rf_reg_read(pAdapter, path, offset);
247 bit_shift = bitshift(bitmask);
248 new_value = (org_value & (~bitmask)) | (value << bit_shift);
249 } else {
250 new_value = value;
251 }
252 return r8712_rf_reg_write(pAdapter, path, offset, new_value);
253 }
254
255 /*
256 * SetChannel
257 * Description
258 * Use H2C command to change channel,
259 * not only modify rf register, but also other setting need to be done.
260 */
r8712_SetChannel(struct _adapter * pAdapter)261 void r8712_SetChannel(struct _adapter *pAdapter)
262 {
263 struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv;
264 struct cmd_obj *pcmd = NULL;
265 struct SetChannel_parm *pparm = NULL;
266 u16 code = GEN_CMD_CODE(_SetChannel);
267
268 pcmd = kmalloc(sizeof(*pcmd), GFP_ATOMIC);
269 if (!pcmd)
270 return;
271 pparm = kmalloc(sizeof(*pparm), GFP_ATOMIC);
272 if (!pparm) {
273 kfree(pcmd);
274 return;
275 }
276 pparm->curr_ch = pAdapter->mppriv.curr_ch;
277 init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code);
278 r8712_enqueue_cmd(pcmdpriv, pcmd);
279 }
280
SetCCKTxPower(struct _adapter * pAdapter,u8 TxPower)281 static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower)
282 {
283 u16 TxAGC = 0;
284
285 TxAGC = TxPower;
286 set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
287 }
288
SetOFDMTxPower(struct _adapter * pAdapter,u8 TxPower)289 static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower)
290 {
291 u32 TxAGC = 0;
292
293 TxAGC |= ((TxPower << 24) | (TxPower << 16) | (TxPower << 8) |
294 TxPower);
295 set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
296 set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
297 set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
298 set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC);
299 set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC);
300 set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC);
301 }
302
r8712_SetTxPower(struct _adapter * pAdapter)303 void r8712_SetTxPower(struct _adapter *pAdapter)
304 {
305 u8 TxPower = pAdapter->mppriv.curr_txpoweridx;
306
307 SetCCKTxPower(pAdapter, TxPower);
308 SetOFDMTxPower(pAdapter, TxPower);
309 }
310
r8712_SetTxAGCOffset(struct _adapter * pAdapter,u32 ulTxAGCOffset)311 void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset)
312 {
313 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
314
315 TxAGCOffset_B = ulTxAGCOffset & 0x000000ff;
316 TxAGCOffset_C = (ulTxAGCOffset & 0x0000ff00) >> 8;
317 TxAGCOffset_D = (ulTxAGCOffset & 0x00ff0000) >> 16;
318 tmpAGC = TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B;
319 set_bb_reg(pAdapter, rFPGA0_TxGainStage,
320 (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
321 }
322
r8712_SetDataRate(struct _adapter * pAdapter)323 void r8712_SetDataRate(struct _adapter *pAdapter)
324 {
325 u8 path = RF_PATH_A;
326 u8 offset = RF_SYN_G2;
327 u32 value;
328
329 value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200;
330 r8712_rf_reg_write(pAdapter, path, offset, value);
331 }
332
r8712_SwitchBandwidth(struct _adapter * pAdapter)333 void r8712_SwitchBandwidth(struct _adapter *pAdapter)
334 {
335 /* 3 1.Set MAC register : BWOPMODE bit2:1 20MhzBW */
336 u8 regBwOpMode = 0;
337 u8 Bandwidth = pAdapter->mppriv.curr_bandwidth;
338
339 regBwOpMode = r8712_read8(pAdapter, 0x10250203);
340 if (Bandwidth == HT_CHANNEL_WIDTH_20)
341 regBwOpMode |= BIT(2);
342 else
343 regBwOpMode &= ~(BIT(2));
344 r8712_write8(pAdapter, 0x10250203, regBwOpMode);
345 /* 3 2.Set PHY related register */
346 switch (Bandwidth) {
347 /* 20 MHz channel*/
348 case HT_CHANNEL_WIDTH_20:
349 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0);
350 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0);
351 /* Use PHY_REG.txt default value. Do not need to change.
352 * Correct the tx power for CCK rate in 40M.
353 * It is set in Tx descriptor for 8192x series
354 */
355 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58);
356 break;
357 /* 40 MHz channel*/
358 case HT_CHANNEL_WIDTH_40:
359 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1);
360 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1);
361 /* Use PHY_REG.txt default value. Do not need to change.
362 * Correct the tx power for CCK rate in 40M.
363 * Set Control channel to upper or lower. These settings are
364 * required only for 40MHz
365 */
366 set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
367 (HAL_PRIME_CHNL_OFFSET_DONT_CARE >> 1));
368 set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
369 HAL_PRIME_CHNL_OFFSET_DONT_CARE);
370 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
371 break;
372 default:
373 break;
374 }
375
376 /* 3 3.Set RF related register */
377 switch (Bandwidth) {
378 case HT_CHANNEL_WIDTH_20:
379 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
380 BIT(10) | BIT(11), 0x01);
381 break;
382 case HT_CHANNEL_WIDTH_40:
383 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
384 BIT(10) | BIT(11), 0x00);
385 break;
386 default:
387 break;
388 }
389 }
390
391 /*------------------------------Define structure----------------------------*/
392 struct R_ANTENNA_SELECT_OFDM {
393 u32 r_tx_antenna:4;
394 u32 r_ant_l:4;
395 u32 r_ant_non_ht:4;
396 u32 r_ant_ht1:4;
397 u32 r_ant_ht2:4;
398 u32 r_ant_ht_s1:4;
399 u32 r_ant_non_ht_s1:4;
400 u32 OFDM_TXSC:2;
401 u32 Reserved:2;
402 };
403
404 struct R_ANTENNA_SELECT_CCK {
405 u8 r_cckrx_enable_2:2;
406 u8 r_cckrx_enable:2;
407 u8 r_ccktx_enable:4;
408 };
409
r8712_SwitchAntenna(struct _adapter * pAdapter)410 void r8712_SwitchAntenna(struct _adapter *pAdapter)
411 {
412 u32 ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0;
413 u8 ofdm_rx_ant_sel_val = 0;
414 u8 cck_ant_select_val = 0;
415 u32 cck_ant_sel_val = 0;
416 struct R_ANTENNA_SELECT_CCK *p_cck_txrx;
417
418 p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val;
419
420 switch (pAdapter->mppriv.antenna_tx) {
421 case ANTENNA_A:
422 /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
423 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
424 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
425 ofdm_tx_en_val = 0x3;
426 ofdm_tx_ant_sel_val = 0x11111111;/* Power save */
427 p_cck_txrx->r_ccktx_enable = 0x8;
428 break;
429 case ANTENNA_B:
430 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
431 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
432 ofdm_tx_en_val = 0x3;
433 ofdm_tx_ant_sel_val = 0x22222222;/* Power save */
434 p_cck_txrx->r_ccktx_enable = 0x4;
435 break;
436 case ANTENNA_AB: /* For 8192S */
437 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
438 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
439 ofdm_tx_en_val = 0x3;
440 ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */
441 p_cck_txrx->r_ccktx_enable = 0xC;
442 break;
443 default:
444 break;
445 }
446 /*OFDM Tx*/
447 set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val);
448 /*OFDM Tx*/
449 set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val);
450 switch (pAdapter->mppriv.antenna_rx) {
451 case ANTENNA_A:
452 ofdm_rx_ant_sel_val = 0x1; /* A */
453 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
454 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
455 break;
456 case ANTENNA_B:
457 ofdm_rx_ant_sel_val = 0x2; /* B */
458 p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
459 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
460 break;
461 case ANTENNA_AB:
462 ofdm_rx_ant_sel_val = 0x3; /* AB */
463 p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
464 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
465 break;
466 default:
467 break;
468 }
469 /*OFDM Rx*/
470 set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f,
471 ofdm_rx_ant_sel_val);
472 /*OFDM Rx*/
473 set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f,
474 ofdm_rx_ant_sel_val);
475
476 cck_ant_sel_val = cck_ant_select_val;
477 /*CCK TxRx*/
478 set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
479 }
480
TriggerRFThermalMeter(struct _adapter * pAdapter)481 static void TriggerRFThermalMeter(struct _adapter *pAdapter)
482 {
483 /* 0x24: RF Reg[6:5] */
484 set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
485 }
486
ReadRFThermalMeter(struct _adapter * pAdapter)487 static u32 ReadRFThermalMeter(struct _adapter *pAdapter)
488 {
489 /* 0x24: RF Reg[4:0] */
490 return get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);
491 }
492
r8712_GetThermalMeter(struct _adapter * pAdapter,u32 * value)493 void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value)
494 {
495 TriggerRFThermalMeter(pAdapter);
496 msleep(1000);
497 *value = ReadRFThermalMeter(pAdapter);
498 }
499
r8712_SetSingleCarrierTx(struct _adapter * pAdapter,u8 bStart)500 void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart)
501 {
502 if (bStart) { /* Start Single Carrier. */
503 /* 1. if OFDM block on? */
504 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
505 /*set OFDM block on*/
506 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
507 /* 2. set CCK test mode off, set to CCK normal mode */
508 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
509 /* 3. turn on scramble setting */
510 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
511 /* 4. Turn On Single Carrier Tx and off the other test modes. */
512 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
513 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
514 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
515 } else { /* Stop Single Carrier.*/
516 /* Turn off all test modes.*/
517 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
518 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
519 bDisable);
520 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
521 msleep(20);
522 /*BB Reset*/
523 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
524 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
525 }
526 }
527
r8712_SetSingleToneTx(struct _adapter * pAdapter,u8 bStart)528 void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart)
529 {
530 u8 rfPath;
531
532 switch (pAdapter->mppriv.antenna_tx) {
533 case ANTENNA_B:
534 rfPath = RF_PATH_B;
535 break;
536 case ANTENNA_A:
537 default:
538 rfPath = RF_PATH_A;
539 break;
540 }
541 if (bStart) { /* Start Single Tone.*/
542 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable);
543 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable);
544 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
545 0xd4000);
546 msleep(100);
547 /* PAD all on.*/
548 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f);
549 msleep(100);
550 } else { /* Stop Single Tone.*/
551 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
552 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
553 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
554 0x54000);
555 msleep(100);
556 /* PAD all on.*/
557 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000);
558 msleep(100);
559 }
560 }
561
r8712_SetCarrierSuppressionTx(struct _adapter * pAdapter,u8 bStart)562 void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart)
563 {
564 if (bStart) { /* Start Carrier Suppression.*/
565 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
566 /* 1. if CCK block on? */
567 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
568 /*set CCK block on*/
569 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn,
570 bEnable);
571 }
572 /* Turn Off All Test Mode */
573 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx,
574 bDisable);
575 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
576 bDisable);
577 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone,
578 bDisable);
579 /*transmit mode*/
580 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
581 /*turn off scramble setting*/
582 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
583 bDisable);
584 /*Set CCK Tx Test Rate*/
585 /*Set FTxRate to 1Mbps*/
586 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);
587 }
588 } else { /* Stop Carrier Suppression. */
589 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
590 /*normal mode*/
591 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
592 /*turn on scramble setting*/
593 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
594 bEnable);
595 /*BB Reset*/
596 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
597 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
598 }
599 }
600 }
601
SetCCKContinuousTx(struct _adapter * pAdapter,u8 bStart)602 static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart)
603 {
604 u32 cckrate;
605
606 if (bStart) {
607 /* 1. if CCK block on? */
608 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
609 /*set CCK block on*/
610 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
611 }
612 /* Turn Off All Test Mode */
613 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
614 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
615 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
616 /*Set CCK Tx Test Rate*/
617 cckrate = pAdapter->mppriv.curr_rateidx;
618 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
619 /*transmit mode*/
620 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
621 /*turn on scramble setting*/
622 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
623 } else {
624 /*normal mode*/
625 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
626 /*turn on scramble setting*/
627 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
628 /*BB Reset*/
629 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
630 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
631 }
632 } /* mpt_StartCckContTx */
633
SetOFDMContinuousTx(struct _adapter * pAdapter,u8 bStart)634 static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart)
635 {
636 if (bStart) {
637 /* 1. if OFDM block on? */
638 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) {
639 /*set OFDM block on*/
640 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
641 }
642 /* 2. set CCK test mode off, set to CCK normal mode*/
643 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
644 /* 3. turn on scramble setting */
645 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
646 /* 4. Turn On Continue Tx and turn off the other test modes.*/
647 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
648 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
649 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
650 } else {
651 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
652 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
653 bDisable);
654 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
655 msleep(20);
656 /*BB Reset*/
657 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
658 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
659 }
660 } /* mpt_StartOfdmContTx */
661
r8712_SetContinuousTx(struct _adapter * pAdapter,u8 bStart)662 void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart)
663 {
664 /* ADC turn off [bit24-21] adc port0 ~ port1 */
665 if (bStart) {
666 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
667 r8712_bb_reg_read(pAdapter,
668 rRx_Wait_CCCA) & 0xFE1FFFFF);
669 msleep(100);
670 }
671 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M)
672 SetCCKContinuousTx(pAdapter, bStart);
673 else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) &&
674 (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15))
675 SetOFDMContinuousTx(pAdapter, bStart);
676 /* ADC turn on [bit24-21] adc port0 ~ port1 */
677 if (!bStart)
678 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
679 r8712_bb_reg_read(pAdapter,
680 rRx_Wait_CCCA) | 0x01E00000);
681 }
682
r8712_ResetPhyRxPktCount(struct _adapter * pAdapter)683 void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter)
684 {
685 u32 i, phyrx_set = 0;
686
687 for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) {
688 phyrx_set = 0;
689 phyrx_set |= (i << 28); /*select*/
690 phyrx_set |= 0x08000000; /* set counter to zero*/
691 r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
692 }
693 }
694
GetPhyRxPktCounts(struct _adapter * pAdapter,u32 selbit)695 static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit)
696 {
697 /*selection*/
698 u32 phyrx_set = 0;
699 u32 SelectBit;
700
701 SelectBit = selbit << 28;
702 phyrx_set |= (SelectBit & 0xF0000000);
703 r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
704 /*Read packet count*/
705 return r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount;
706 }
707
r8712_GetPhyRxPktReceived(struct _adapter * pAdapter)708 u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter)
709 {
710 u32 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT);
711 u32 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT);
712 u32 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT);
713
714 return OFDM_cnt + CCK_cnt + HT_cnt;
715 }
716
r8712_GetPhyRxPktCRC32Error(struct _adapter * pAdapter)717 u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter)
718 {
719 u32 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT);
720 u32 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT);
721 u32 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT);
722
723 return OFDM_cnt + CCK_cnt + HT_cnt;
724 }
725