1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * drivers/usb/gadget/emxx_udc.c
4 * EMXX FCD (Function Controller Driver) for USB.
5 *
6 * Copyright (C) 2010 Renesas Electronics Corporation
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/delay.h>
13 #include <linux/ioport.h>
14 #include <linux/slab.h>
15 #include <linux/errno.h>
16 #include <linux/list.h>
17 #include <linux/interrupt.h>
18 #include <linux/proc_fs.h>
19 #include <linux/clk.h>
20 #include <linux/ctype.h>
21 #include <linux/string.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/workqueue.h>
24 #include <linux/device.h>
25
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
28
29 #include <linux/irq.h>
30 #include <linux/gpio/consumer.h>
31
32 #include "emxx_udc.h"
33
34 #define DRIVER_DESC "EMXX UDC driver"
35 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
36
37 static struct gpio_desc *vbus_gpio;
38 static int vbus_irq;
39
40 static const char driver_name[] = "emxx_udc";
41
42 /*===========================================================================*/
43 /* Prototype */
44 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *);
45 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *);
46 /*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/
47 static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int);
48 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode);
49 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs);
50
51 static int _nbu2ss_pullup(struct nbu2ss_udc *, int);
52 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *);
53
54 /*===========================================================================*/
55 /* Macro */
56 #define _nbu2ss_zero_len_pkt(udc, epnum) \
57 _nbu2ss_ep_in_end(udc, epnum, 0, 0)
58
59 /*===========================================================================*/
60 /* Global */
61 static struct nbu2ss_udc udc_controller;
62
63 /*-------------------------------------------------------------------------*/
64 /* Read */
_nbu2ss_readl(void __iomem * address)65 static inline u32 _nbu2ss_readl(void __iomem *address)
66 {
67 return __raw_readl(address);
68 }
69
70 /*-------------------------------------------------------------------------*/
71 /* Write */
_nbu2ss_writel(void __iomem * address,u32 udata)72 static inline void _nbu2ss_writel(void __iomem *address, u32 udata)
73 {
74 __raw_writel(udata, address);
75 }
76
77 /*-------------------------------------------------------------------------*/
78 /* Set Bit */
_nbu2ss_bitset(void __iomem * address,u32 udata)79 static inline void _nbu2ss_bitset(void __iomem *address, u32 udata)
80 {
81 u32 reg_dt = __raw_readl(address) | (udata);
82
83 __raw_writel(reg_dt, address);
84 }
85
86 /*-------------------------------------------------------------------------*/
87 /* Clear Bit */
_nbu2ss_bitclr(void __iomem * address,u32 udata)88 static inline void _nbu2ss_bitclr(void __iomem *address, u32 udata)
89 {
90 u32 reg_dt = __raw_readl(address) & ~(udata);
91
92 __raw_writel(reg_dt, address);
93 }
94
95 #ifdef UDC_DEBUG_DUMP
96 /*-------------------------------------------------------------------------*/
_nbu2ss_dump_register(struct nbu2ss_udc * udc)97 static void _nbu2ss_dump_register(struct nbu2ss_udc *udc)
98 {
99 int i;
100 u32 reg_data;
101
102 pr_info("=== %s()\n", __func__);
103
104 if (!udc) {
105 pr_err("%s udc == NULL\n", __func__);
106 return;
107 }
108
109 spin_unlock(&udc->lock);
110
111 dev_dbg(&udc->dev, "\n-USB REG-\n");
112 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) {
113 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i));
114 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data);
115
116 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 4));
117 dev_dbg(&udc->dev, " %08x", (int)reg_data);
118
119 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 8));
120 dev_dbg(&udc->dev, " %08x", (int)reg_data);
121
122 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 12));
123 dev_dbg(&udc->dev, " %08x\n", (int)reg_data);
124 }
125
126 spin_lock(&udc->lock);
127 }
128 #endif /* UDC_DEBUG_DUMP */
129
130 /*-------------------------------------------------------------------------*/
131 /* Endpoint 0 Callback (Complete) */
_nbu2ss_ep0_complete(struct usb_ep * _ep,struct usb_request * _req)132 static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req)
133 {
134 u8 recipient;
135 u16 selector;
136 u16 wIndex;
137 u32 test_mode;
138 struct usb_ctrlrequest *p_ctrl;
139 struct nbu2ss_udc *udc;
140
141 if (!_ep || !_req)
142 return;
143
144 udc = (struct nbu2ss_udc *)_req->context;
145 p_ctrl = &udc->ctrl;
146 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
147 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) {
148 /*-------------------------------------------------*/
149 /* SET_FEATURE */
150 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK);
151 selector = le16_to_cpu(p_ctrl->wValue);
152 if ((recipient == USB_RECIP_DEVICE) &&
153 (selector == USB_DEVICE_TEST_MODE)) {
154 wIndex = le16_to_cpu(p_ctrl->wIndex);
155 test_mode = (u32)(wIndex >> 8);
156 _nbu2ss_set_test_mode(udc, test_mode);
157 }
158 }
159 }
160 }
161
162 /*-------------------------------------------------------------------------*/
163 /* Initialization usb_request */
_nbu2ss_create_ep0_packet(struct nbu2ss_udc * udc,void * p_buf,unsigned int length)164 static void _nbu2ss_create_ep0_packet(struct nbu2ss_udc *udc,
165 void *p_buf, unsigned int length)
166 {
167 udc->ep0_req.req.buf = p_buf;
168 udc->ep0_req.req.length = length;
169 udc->ep0_req.req.dma = 0;
170 udc->ep0_req.req.zero = true;
171 udc->ep0_req.req.complete = _nbu2ss_ep0_complete;
172 udc->ep0_req.req.status = -EINPROGRESS;
173 udc->ep0_req.req.context = udc;
174 udc->ep0_req.req.actual = 0;
175 }
176
177 /*-------------------------------------------------------------------------*/
178 /* Acquisition of the first address of RAM(FIFO) */
_nbu2ss_get_begin_ram_address(struct nbu2ss_udc * udc)179 static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc)
180 {
181 u32 num, buf_type;
182 u32 data, last_ram_adr, use_ram_size;
183
184 struct ep_regs __iomem *p_ep_regs;
185
186 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2;
187 use_ram_size = 0;
188
189 for (num = 0; num < NUM_ENDPOINTS - 1; num++) {
190 p_ep_regs = &udc->p_regs->EP_REGS[num];
191 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS);
192 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPN_BUF_TYPE;
193 if (buf_type == 0) {
194 /* Single Buffer */
195 use_ram_size += (data & EPN_MPKT) / sizeof(u32);
196 } else {
197 /* Double Buffer */
198 use_ram_size += ((data & EPN_MPKT) / sizeof(u32)) * 2;
199 }
200
201 if ((data >> 16) > last_ram_adr)
202 last_ram_adr = data >> 16;
203 }
204
205 return last_ram_adr + use_ram_size;
206 }
207
208 /*-------------------------------------------------------------------------*/
209 /* Construction of Endpoint */
_nbu2ss_ep_init(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)210 static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
211 {
212 u32 num;
213 u32 data;
214 u32 begin_adrs;
215
216 if (ep->epnum == 0)
217 return -EINVAL;
218
219 num = ep->epnum - 1;
220
221 /*-------------------------------------------------------------*/
222 /* RAM Transfer Address */
223 begin_adrs = _nbu2ss_get_begin_ram_address(udc);
224 data = (begin_adrs << 16) | ep->ep.maxpacket;
225 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data);
226
227 /*-------------------------------------------------------------*/
228 /* Interrupt Enable */
229 data = 1 << (ep->epnum + 8);
230 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data);
231
232 /*-------------------------------------------------------------*/
233 /* Endpoint Type(Mode) */
234 /* Bulk, Interrupt, ISO */
235 switch (ep->ep_type) {
236 case USB_ENDPOINT_XFER_BULK:
237 data = EPN_BULK;
238 break;
239
240 case USB_ENDPOINT_XFER_INT:
241 data = EPN_BUF_SINGLE | EPN_INTERRUPT;
242 break;
243
244 case USB_ENDPOINT_XFER_ISOC:
245 data = EPN_ISO;
246 break;
247
248 default:
249 data = 0;
250 break;
251 }
252
253 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
254 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum | ep->direct));
255
256 if (ep->direct == USB_DIR_OUT) {
257 /*---------------------------------------------------------*/
258 /* OUT */
259 data = EPN_EN | EPN_BCLR | EPN_DIR0;
260 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
261
262 data = EPN_ONAK | EPN_OSTL_EN | EPN_OSTL;
263 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
264
265 data = EPN_OUT_EN | EPN_OUT_END_EN;
266 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
267 } else {
268 /*---------------------------------------------------------*/
269 /* IN */
270 data = EPN_EN | EPN_BCLR | EPN_AUTO;
271 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
272
273 data = EPN_ISTL;
274 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
275
276 data = EPN_IN_EN | EPN_IN_END_EN;
277 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
278 }
279
280 return 0;
281 }
282
283 /*-------------------------------------------------------------------------*/
284 /* Release of Endpoint */
_nbu2ss_epn_exit(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)285 static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
286 {
287 u32 num;
288 u32 data;
289
290 if ((ep->epnum == 0) || (udc->vbus_active == 0))
291 return -EINVAL;
292
293 num = ep->epnum - 1;
294
295 /*-------------------------------------------------------------*/
296 /* RAM Transfer Address */
297 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0);
298
299 /*-------------------------------------------------------------*/
300 /* Interrupt Disable */
301 data = 1 << (ep->epnum + 8);
302 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data);
303
304 if (ep->direct == USB_DIR_OUT) {
305 /*---------------------------------------------------------*/
306 /* OUT */
307 data = EPN_ONAK | EPN_BCLR;
308 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
309
310 data = EPN_EN | EPN_DIR0;
311 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
312
313 data = EPN_OUT_EN | EPN_OUT_END_EN;
314 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
315 } else {
316 /*---------------------------------------------------------*/
317 /* IN */
318 data = EPN_BCLR;
319 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
320
321 data = EPN_EN | EPN_AUTO;
322 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
323
324 data = EPN_IN_EN | EPN_IN_END_EN;
325 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
326 }
327
328 return 0;
329 }
330
331 /*-------------------------------------------------------------------------*/
332 /* DMA setting (without Endpoint 0) */
_nbu2ss_ep_dma_init(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)333 static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
334 {
335 u32 num;
336 u32 data;
337
338 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF);
339 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0))
340 return; /* Not Support DMA */
341
342 num = ep->epnum - 1;
343
344 if (ep->direct == USB_DIR_OUT) {
345 /*---------------------------------------------------------*/
346 /* OUT */
347 data = ep->ep.maxpacket;
348 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data);
349
350 /*---------------------------------------------------------*/
351 /* Transfer Direct */
352 data = DCR1_EPN_DIR0;
353 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data);
354
355 /*---------------------------------------------------------*/
356 /* DMA Mode etc. */
357 data = EPN_STOP_MODE | EPN_STOP_SET | EPN_DMAMODE0;
358 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
359 } else {
360 /*---------------------------------------------------------*/
361 /* IN */
362 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPN_AUTO);
363
364 /*---------------------------------------------------------*/
365 /* DMA Mode etc. */
366 data = EPN_BURST_SET | EPN_DMAMODE0;
367 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
368 }
369 }
370
371 /*-------------------------------------------------------------------------*/
372 /* DMA setting release */
_nbu2ss_ep_dma_exit(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)373 static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
374 {
375 u32 num;
376 u32 data;
377 struct fc_regs __iomem *preg = udc->p_regs;
378
379 if (udc->vbus_active == 0)
380 return; /* VBUS OFF */
381
382 data = _nbu2ss_readl(&preg->USBSSCONF);
383 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0))
384 return; /* Not Support DMA */
385
386 num = ep->epnum - 1;
387
388 _nbu2ss_ep_dma_abort(udc, ep);
389
390 if (ep->direct == USB_DIR_OUT) {
391 /*---------------------------------------------------------*/
392 /* OUT */
393 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0);
394 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_DIR0);
395 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
396 } else {
397 /*---------------------------------------------------------*/
398 /* IN */
399 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
400 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
401 }
402 }
403
404 /*-------------------------------------------------------------------------*/
405 /* Abort DMA */
_nbu2ss_ep_dma_abort(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)406 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
407 {
408 struct fc_regs __iomem *preg = udc->p_regs;
409
410 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPN_REQEN);
411 mdelay(DMA_DISABLE_TIME); /* DCR1_EPN_REQEN Clear */
412 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPN_DMA_EN);
413 }
414
415 /*-------------------------------------------------------------------------*/
416 /* Start IN Transfer */
_nbu2ss_ep_in_end(struct nbu2ss_udc * udc,u32 epnum,u32 data32,u32 length)417 static void _nbu2ss_ep_in_end(struct nbu2ss_udc *udc,
418 u32 epnum, u32 data32, u32 length)
419 {
420 u32 data;
421 u32 num;
422 struct fc_regs __iomem *preg = udc->p_regs;
423
424 if (length >= sizeof(u32))
425 return;
426
427 if (epnum == 0) {
428 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO);
429
430 /* Writing of 1-4 bytes */
431 if (length)
432 _nbu2ss_writel(&preg->EP0_WRITE, data32);
433
434 data = ((length << 5) & EP0_DW) | EP0_DEND;
435 _nbu2ss_writel(&preg->EP0_CONTROL, data);
436
437 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO);
438 } else {
439 num = epnum - 1;
440
441 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
442
443 /* Writing of 1-4 bytes */
444 if (length)
445 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32);
446
447 data = (((length) << 5) & EPN_DW) | EPN_DEND;
448 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
449
450 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
451 }
452 }
453
454 #ifdef USE_DMA
455 /*-------------------------------------------------------------------------*/
_nbu2ss_dma_map_single(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u8 direct)456 static void _nbu2ss_dma_map_single(struct nbu2ss_udc *udc,
457 struct nbu2ss_ep *ep,
458 struct nbu2ss_req *req, u8 direct)
459 {
460 if (req->req.dma == DMA_ADDR_INVALID) {
461 if (req->unaligned) {
462 req->req.dma = ep->phys_buf;
463 } else {
464 req->req.dma = dma_map_single(udc->gadget.dev.parent,
465 req->req.buf,
466 req->req.length,
467 (direct == USB_DIR_IN)
468 ? DMA_TO_DEVICE
469 : DMA_FROM_DEVICE);
470 }
471 req->mapped = 1;
472 } else {
473 if (!req->unaligned)
474 dma_sync_single_for_device(udc->gadget.dev.parent,
475 req->req.dma,
476 req->req.length,
477 (direct == USB_DIR_IN)
478 ? DMA_TO_DEVICE
479 : DMA_FROM_DEVICE);
480
481 req->mapped = 0;
482 }
483 }
484
485 /*-------------------------------------------------------------------------*/
_nbu2ss_dma_unmap_single(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u8 direct)486 static void _nbu2ss_dma_unmap_single(struct nbu2ss_udc *udc,
487 struct nbu2ss_ep *ep,
488 struct nbu2ss_req *req, u8 direct)
489 {
490 u8 data[4];
491 u8 *p;
492 u32 count = 0;
493
494 if (direct == USB_DIR_OUT) {
495 count = req->req.actual % 4;
496 if (count) {
497 p = req->req.buf;
498 p += (req->req.actual - count);
499 memcpy(data, p, count);
500 }
501 }
502
503 if (req->mapped) {
504 if (req->unaligned) {
505 if (direct == USB_DIR_OUT)
506 memcpy(req->req.buf, ep->virt_buf,
507 req->req.actual & 0xfffffffc);
508 } else {
509 dma_unmap_single(udc->gadget.dev.parent,
510 req->req.dma, req->req.length,
511 (direct == USB_DIR_IN)
512 ? DMA_TO_DEVICE
513 : DMA_FROM_DEVICE);
514 }
515 req->req.dma = DMA_ADDR_INVALID;
516 req->mapped = 0;
517 } else {
518 if (!req->unaligned)
519 dma_sync_single_for_cpu(udc->gadget.dev.parent,
520 req->req.dma, req->req.length,
521 (direct == USB_DIR_IN)
522 ? DMA_TO_DEVICE
523 : DMA_FROM_DEVICE);
524 }
525
526 if (count) {
527 p = req->req.buf;
528 p += (req->req.actual - count);
529 memcpy(p, data, count);
530 }
531 }
532 #endif
533
534 /*-------------------------------------------------------------------------*/
535 /* Endpoint 0 OUT Transfer (PIO) */
ep0_out_pio(struct nbu2ss_udc * udc,u8 * buf,u32 length)536 static int ep0_out_pio(struct nbu2ss_udc *udc, u8 *buf, u32 length)
537 {
538 u32 i;
539 u32 numreads = length / sizeof(u32);
540 union usb_reg_access *buf32 = (union usb_reg_access *)buf;
541
542 if (!numreads)
543 return 0;
544
545 /* PIO Read */
546 for (i = 0; i < numreads; i++) {
547 buf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
548 buf32++;
549 }
550
551 return numreads * sizeof(u32);
552 }
553
554 /*-------------------------------------------------------------------------*/
555 /* Endpoint 0 OUT Transfer (PIO, OverBytes) */
ep0_out_overbytes(struct nbu2ss_udc * udc,u8 * p_buf,u32 length)556 static int ep0_out_overbytes(struct nbu2ss_udc *udc, u8 *p_buf, u32 length)
557 {
558 u32 i;
559 u32 i_read_size = 0;
560 union usb_reg_access temp_32;
561 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
562
563 if ((length > 0) && (length < sizeof(u32))) {
564 temp_32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
565 for (i = 0 ; i < length ; i++)
566 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i];
567 i_read_size += length;
568 }
569
570 return i_read_size;
571 }
572
573 /*-------------------------------------------------------------------------*/
574 /* Endpoint 0 IN Transfer (PIO) */
EP0_in_PIO(struct nbu2ss_udc * udc,u8 * p_buf,u32 length)575 static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *p_buf, u32 length)
576 {
577 u32 i;
578 u32 i_max_length = EP0_PACKETSIZE;
579 u32 i_word_length = 0;
580 u32 i_write_length = 0;
581 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
582
583 /*------------------------------------------------------------*/
584 /* Transfer Length */
585 if (i_max_length < length)
586 i_word_length = i_max_length / sizeof(u32);
587 else
588 i_word_length = length / sizeof(u32);
589
590 /*------------------------------------------------------------*/
591 /* PIO */
592 for (i = 0; i < i_word_length; i++) {
593 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, p_buf_32->dw);
594 p_buf_32++;
595 i_write_length += sizeof(u32);
596 }
597
598 return i_write_length;
599 }
600
601 /*-------------------------------------------------------------------------*/
602 /* Endpoint 0 IN Transfer (PIO, OverBytes) */
ep0_in_overbytes(struct nbu2ss_udc * udc,u8 * p_buf,u32 i_remain_size)603 static int ep0_in_overbytes(struct nbu2ss_udc *udc,
604 u8 *p_buf,
605 u32 i_remain_size)
606 {
607 u32 i;
608 union usb_reg_access temp_32;
609 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
610
611 if ((i_remain_size > 0) && (i_remain_size < sizeof(u32))) {
612 for (i = 0 ; i < i_remain_size ; i++)
613 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i];
614 _nbu2ss_ep_in_end(udc, 0, temp_32.dw, i_remain_size);
615
616 return i_remain_size;
617 }
618
619 return 0;
620 }
621
622 /*-------------------------------------------------------------------------*/
623 /* Transfer NULL Packet (Epndoint 0) */
EP0_send_NULL(struct nbu2ss_udc * udc,bool pid_flag)624 static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag)
625 {
626 u32 data;
627
628 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
629 data &= ~(u32)EP0_INAK;
630
631 if (pid_flag)
632 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND);
633 else
634 data |= (EP0_INAK_EN | EP0_DEND);
635
636 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
637
638 return 0;
639 }
640
641 /*-------------------------------------------------------------------------*/
642 /* Receive NULL Packet (Endpoint 0) */
EP0_receive_NULL(struct nbu2ss_udc * udc,bool pid_flag)643 static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag)
644 {
645 u32 data;
646
647 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
648 data &= ~(u32)EP0_ONAK;
649
650 if (pid_flag)
651 data |= EP0_PIDCLR;
652
653 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
654
655 return 0;
656 }
657
658 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_in_transfer(struct nbu2ss_udc * udc,struct nbu2ss_req * req)659 static int _nbu2ss_ep0_in_transfer(struct nbu2ss_udc *udc,
660 struct nbu2ss_req *req)
661 {
662 u8 *p_buffer; /* IN Data Buffer */
663 u32 data;
664 u32 i_remain_size = 0;
665 int result = 0;
666
667 /*-------------------------------------------------------------*/
668 /* End confirmation */
669 if (req->req.actual == req->req.length) {
670 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
671 if (req->zero) {
672 req->zero = false;
673 EP0_send_NULL(udc, false);
674 return 1;
675 }
676 }
677
678 return 0; /* Transfer End */
679 }
680
681 /*-------------------------------------------------------------*/
682 /* NAK release */
683 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
684 data |= EP0_INAK_EN;
685 data &= ~(u32)EP0_INAK;
686 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
687
688 i_remain_size = req->req.length - req->req.actual;
689 p_buffer = (u8 *)req->req.buf;
690 p_buffer += req->req.actual;
691
692 /*-------------------------------------------------------------*/
693 /* Data transfer */
694 result = EP0_in_PIO(udc, p_buffer, i_remain_size);
695
696 req->div_len = result;
697 i_remain_size -= result;
698
699 if (i_remain_size == 0) {
700 EP0_send_NULL(udc, false);
701 return result;
702 }
703
704 if ((i_remain_size < sizeof(u32)) && (result != EP0_PACKETSIZE)) {
705 p_buffer += result;
706 result += ep0_in_overbytes(udc, p_buffer, i_remain_size);
707 req->div_len = result;
708 }
709
710 return result;
711 }
712
713 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_out_transfer(struct nbu2ss_udc * udc,struct nbu2ss_req * req)714 static int _nbu2ss_ep0_out_transfer(struct nbu2ss_udc *udc,
715 struct nbu2ss_req *req)
716 {
717 u8 *p_buffer;
718 u32 i_remain_size;
719 u32 i_recv_length;
720 int result = 0;
721 int f_rcv_zero;
722
723 /*-------------------------------------------------------------*/
724 /* Receive data confirmation */
725 i_recv_length = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA;
726 if (i_recv_length != 0) {
727 f_rcv_zero = 0;
728
729 i_remain_size = req->req.length - req->req.actual;
730 p_buffer = (u8 *)req->req.buf;
731 p_buffer += req->req.actual;
732
733 result = ep0_out_pio(udc, p_buffer
734 , min(i_remain_size, i_recv_length));
735 if (result < 0)
736 return result;
737
738 req->req.actual += result;
739 i_recv_length -= result;
740
741 if ((i_recv_length > 0) && (i_recv_length < sizeof(u32))) {
742 p_buffer += result;
743 i_remain_size -= result;
744
745 result = ep0_out_overbytes(udc, p_buffer
746 , min(i_remain_size, i_recv_length));
747 req->req.actual += result;
748 }
749 } else {
750 f_rcv_zero = 1;
751 }
752
753 /*-------------------------------------------------------------*/
754 /* End confirmation */
755 if (req->req.actual == req->req.length) {
756 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
757 if (req->zero) {
758 req->zero = false;
759 EP0_receive_NULL(udc, false);
760 return 1;
761 }
762 }
763
764 return 0; /* Transfer End */
765 }
766
767 if ((req->req.actual % EP0_PACKETSIZE) != 0)
768 return 0; /* Short Packet Transfer End */
769
770 if (req->req.actual > req->req.length) {
771 dev_err(udc->dev, " *** Overrun Error\n");
772 return -EOVERFLOW;
773 }
774
775 if (f_rcv_zero != 0) {
776 i_remain_size = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
777 if (i_remain_size & EP0_ONAK) {
778 /*---------------------------------------------------*/
779 /* NACK release */
780 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK);
781 }
782 result = 1;
783 }
784
785 return result;
786 }
787
788 /*-------------------------------------------------------------------------*/
_nbu2ss_out_dma(struct nbu2ss_udc * udc,struct nbu2ss_req * req,u32 num,u32 length)789 static int _nbu2ss_out_dma(struct nbu2ss_udc *udc, struct nbu2ss_req *req,
790 u32 num, u32 length)
791 {
792 dma_addr_t p_buffer;
793 u32 mpkt;
794 u32 lmpkt;
795 u32 dmacnt;
796 u32 burst = 1;
797 u32 data;
798 int result;
799 struct fc_regs __iomem *preg = udc->p_regs;
800
801 if (req->dma_flag)
802 return 1; /* DMA is forwarded */
803
804 req->dma_flag = true;
805 p_buffer = req->req.dma;
806 p_buffer += req->req.actual;
807
808 /* DMA Address */
809 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer);
810
811 /* Number of transfer packets */
812 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT;
813 dmacnt = length / mpkt;
814 lmpkt = (length % mpkt) & ~(u32)0x03;
815
816 if (dmacnt > DMA_MAX_COUNT) {
817 dmacnt = DMA_MAX_COUNT;
818 lmpkt = 0;
819 } else if (lmpkt != 0) {
820 if (dmacnt == 0)
821 burst = 0; /* Burst OFF */
822 dmacnt++;
823 }
824
825 data = mpkt | (lmpkt << 16);
826 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
827
828 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_DIR0 | DCR1_EPN_REQEN;
829 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
830
831 if (burst == 0) {
832 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0);
833 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET);
834 } else {
835 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT
836 , (dmacnt << 16));
837 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET);
838 }
839 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN);
840
841 result = length & ~(u32)0x03;
842 req->div_len = result;
843
844 return result;
845 }
846
847 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_pio(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 length)848 static int _nbu2ss_epn_out_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
849 struct nbu2ss_req *req, u32 length)
850 {
851 u8 *p_buffer;
852 u32 i;
853 u32 data;
854 u32 i_word_length;
855 union usb_reg_access temp_32;
856 union usb_reg_access *p_buf_32;
857 int result = 0;
858 struct fc_regs __iomem *preg = udc->p_regs;
859
860 if (req->dma_flag)
861 return 1; /* DMA is forwarded */
862
863 if (length == 0)
864 return 0;
865
866 p_buffer = (u8 *)req->req.buf;
867 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual);
868
869 i_word_length = length / sizeof(u32);
870 if (i_word_length > 0) {
871 /*---------------------------------------------------------*/
872 /* Copy of every four bytes */
873 for (i = 0; i < i_word_length; i++) {
874 p_buf_32->dw =
875 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
876 p_buf_32++;
877 }
878 result = i_word_length * sizeof(u32);
879 }
880
881 data = length - result;
882 if (data > 0) {
883 /*---------------------------------------------------------*/
884 /* Copy of fraction byte */
885 temp_32.dw =
886 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
887 for (i = 0 ; i < data ; i++)
888 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i];
889 result += data;
890 }
891
892 req->req.actual += result;
893
894 if ((req->req.actual == req->req.length) ||
895 ((req->req.actual % ep->ep.maxpacket) != 0)) {
896 result = 0;
897 }
898
899 return result;
900 }
901
902 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_data(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 data_size)903 static int _nbu2ss_epn_out_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
904 struct nbu2ss_req *req, u32 data_size)
905 {
906 u32 num;
907 u32 i_buf_size;
908 int nret = 1;
909
910 if (ep->epnum == 0)
911 return -EINVAL;
912
913 num = ep->epnum - 1;
914
915 i_buf_size = min((req->req.length - req->req.actual), data_size);
916
917 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) &&
918 (i_buf_size >= sizeof(u32))) {
919 nret = _nbu2ss_out_dma(udc, req, num, i_buf_size);
920 } else {
921 i_buf_size = min_t(u32, i_buf_size, ep->ep.maxpacket);
922 nret = _nbu2ss_epn_out_pio(udc, ep, req, i_buf_size);
923 }
924
925 return nret;
926 }
927
928 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_transfer(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)929 static int _nbu2ss_epn_out_transfer(struct nbu2ss_udc *udc,
930 struct nbu2ss_ep *ep,
931 struct nbu2ss_req *req)
932 {
933 u32 num;
934 u32 i_recv_length;
935 int result = 1;
936 struct fc_regs __iomem *preg = udc->p_regs;
937
938 if (ep->epnum == 0)
939 return -EINVAL;
940
941 num = ep->epnum - 1;
942
943 /*-------------------------------------------------------------*/
944 /* Receive Length */
945 i_recv_length =
946 _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPN_LDATA;
947
948 if (i_recv_length != 0) {
949 result = _nbu2ss_epn_out_data(udc, ep, req, i_recv_length);
950 if (i_recv_length < ep->ep.maxpacket) {
951 if (i_recv_length == result) {
952 req->req.actual += result;
953 result = 0;
954 }
955 }
956 } else {
957 if ((req->req.actual == req->req.length) ||
958 ((req->req.actual % ep->ep.maxpacket) != 0)) {
959 result = 0;
960 }
961 }
962
963 if (result == 0) {
964 if ((req->req.actual % ep->ep.maxpacket) == 0) {
965 if (req->zero) {
966 req->zero = false;
967 return 1;
968 }
969 }
970 }
971
972 if (req->req.actual > req->req.length) {
973 dev_err(udc->dev, " Overrun Error\n");
974 dev_err(udc->dev, " actual = %d, length = %d\n",
975 req->req.actual, req->req.length);
976 result = -EOVERFLOW;
977 }
978
979 return result;
980 }
981
982 /*-------------------------------------------------------------------------*/
_nbu2ss_in_dma(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 num,u32 length)983 static int _nbu2ss_in_dma(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
984 struct nbu2ss_req *req, u32 num, u32 length)
985 {
986 dma_addr_t p_buffer;
987 u32 mpkt; /* MaxPacketSize */
988 u32 lmpkt; /* Last Packet Data Size */
989 u32 dmacnt; /* IN Data Size */
990 u32 i_write_length;
991 u32 data;
992 int result = -EINVAL;
993 struct fc_regs __iomem *preg = udc->p_regs;
994
995 if (req->dma_flag)
996 return 1; /* DMA is forwarded */
997
998 #ifdef USE_DMA
999 if (req->req.actual == 0)
1000 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN);
1001 #endif
1002 req->dma_flag = true;
1003
1004 /* MAX Packet Size */
1005 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT;
1006
1007 if ((DMA_MAX_COUNT * mpkt) < length)
1008 i_write_length = DMA_MAX_COUNT * mpkt;
1009 else
1010 i_write_length = length;
1011
1012 /*------------------------------------------------------------*/
1013 /* Number of transmission packets */
1014 if (mpkt < i_write_length) {
1015 dmacnt = i_write_length / mpkt;
1016 lmpkt = (i_write_length % mpkt) & ~(u32)0x3;
1017 if (lmpkt != 0)
1018 dmacnt++;
1019 else
1020 lmpkt = mpkt & ~(u32)0x3;
1021
1022 } else {
1023 dmacnt = 1;
1024 lmpkt = i_write_length & ~(u32)0x3;
1025 }
1026
1027 /* Packet setting */
1028 data = mpkt | (lmpkt << 16);
1029 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
1030
1031 /* Address setting */
1032 p_buffer = req->req.dma;
1033 p_buffer += req->req.actual;
1034 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer);
1035
1036 /* Packet and DMA setting */
1037 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_REQEN;
1038 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
1039
1040 /* Packet setting of EPC */
1041 data = dmacnt << 16;
1042 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data);
1043
1044 /*DMA setting of EPC */
1045 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN);
1046
1047 result = i_write_length & ~(u32)0x3;
1048 req->div_len = result;
1049
1050 return result;
1051 }
1052
1053 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_pio(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 length)1054 static int _nbu2ss_epn_in_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
1055 struct nbu2ss_req *req, u32 length)
1056 {
1057 u8 *p_buffer;
1058 u32 i;
1059 u32 data;
1060 u32 i_word_length;
1061 union usb_reg_access temp_32;
1062 union usb_reg_access *p_buf_32 = NULL;
1063 int result = 0;
1064 struct fc_regs __iomem *preg = udc->p_regs;
1065
1066 if (req->dma_flag)
1067 return 1; /* DMA is forwarded */
1068
1069 if (length > 0) {
1070 p_buffer = (u8 *)req->req.buf;
1071 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual);
1072
1073 i_word_length = length / sizeof(u32);
1074 if (i_word_length > 0) {
1075 for (i = 0; i < i_word_length; i++) {
1076 _nbu2ss_writel(&preg->EP_REGS[ep->epnum - 1].EP_WRITE,
1077 p_buf_32->dw);
1078
1079 p_buf_32++;
1080 }
1081 result = i_word_length * sizeof(u32);
1082 }
1083 }
1084
1085 if (result != ep->ep.maxpacket) {
1086 data = length - result;
1087 temp_32.dw = 0;
1088 for (i = 0 ; i < data ; i++)
1089 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i];
1090
1091 _nbu2ss_ep_in_end(udc, ep->epnum, temp_32.dw, data);
1092 result += data;
1093 }
1094
1095 req->div_len = result;
1096
1097 return result;
1098 }
1099
1100 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_data(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 data_size)1101 static int _nbu2ss_epn_in_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
1102 struct nbu2ss_req *req, u32 data_size)
1103 {
1104 u32 num;
1105 int nret = 1;
1106
1107 if (ep->epnum == 0)
1108 return -EINVAL;
1109
1110 num = ep->epnum - 1;
1111
1112 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) &&
1113 (data_size >= sizeof(u32))) {
1114 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size);
1115 } else {
1116 data_size = min_t(u32, data_size, ep->ep.maxpacket);
1117 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size);
1118 }
1119
1120 return nret;
1121 }
1122
1123 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_transfer(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1124 static int _nbu2ss_epn_in_transfer(struct nbu2ss_udc *udc,
1125 struct nbu2ss_ep *ep, struct nbu2ss_req *req)
1126 {
1127 u32 num;
1128 u32 i_buf_size;
1129 int result = 0;
1130 u32 status;
1131
1132 if (ep->epnum == 0)
1133 return -EINVAL;
1134
1135 num = ep->epnum - 1;
1136
1137 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
1138
1139 /*-------------------------------------------------------------*/
1140 /* State confirmation of FIFO */
1141 if (req->req.actual == 0) {
1142 if ((status & EPN_IN_EMPTY) == 0)
1143 return 1; /* Not Empty */
1144
1145 } else {
1146 if ((status & EPN_IN_FULL) != 0)
1147 return 1; /* Not Empty */
1148 }
1149
1150 /*-------------------------------------------------------------*/
1151 /* Start transfer */
1152 i_buf_size = req->req.length - req->req.actual;
1153 if (i_buf_size > 0)
1154 result = _nbu2ss_epn_in_data(udc, ep, req, i_buf_size);
1155 else if (req->req.length == 0)
1156 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1157
1158 return result;
1159 }
1160
1161 /*-------------------------------------------------------------------------*/
_nbu2ss_start_transfer(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,bool bflag)1162 static int _nbu2ss_start_transfer(struct nbu2ss_udc *udc,
1163 struct nbu2ss_ep *ep,
1164 struct nbu2ss_req *req,
1165 bool bflag)
1166 {
1167 int nret = -EINVAL;
1168
1169 req->dma_flag = false;
1170 req->div_len = 0;
1171
1172 if (req->req.length == 0) {
1173 req->zero = false;
1174 } else {
1175 if ((req->req.length % ep->ep.maxpacket) == 0)
1176 req->zero = req->req.zero;
1177 else
1178 req->zero = false;
1179 }
1180
1181 if (ep->epnum == 0) {
1182 /* EP0 */
1183 switch (udc->ep0state) {
1184 case EP0_IN_DATA_PHASE:
1185 nret = _nbu2ss_ep0_in_transfer(udc, req);
1186 break;
1187
1188 case EP0_OUT_DATA_PHASE:
1189 nret = _nbu2ss_ep0_out_transfer(udc, req);
1190 break;
1191
1192 case EP0_IN_STATUS_PHASE:
1193 nret = EP0_send_NULL(udc, true);
1194 break;
1195
1196 default:
1197 break;
1198 }
1199
1200 } else {
1201 /* EPN */
1202 if (ep->direct == USB_DIR_OUT) {
1203 /* OUT */
1204 if (!bflag)
1205 nret = _nbu2ss_epn_out_transfer(udc, ep, req);
1206 } else {
1207 /* IN */
1208 nret = _nbu2ss_epn_in_transfer(udc, ep, req);
1209 }
1210 }
1211
1212 return nret;
1213 }
1214
1215 /*-------------------------------------------------------------------------*/
_nbu2ss_restert_transfer(struct nbu2ss_ep * ep)1216 static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep)
1217 {
1218 u32 length;
1219 bool bflag = false;
1220 struct nbu2ss_req *req;
1221
1222 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1223 if (!req)
1224 return;
1225
1226 if (ep->epnum > 0) {
1227 length = _nbu2ss_readl(&ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT);
1228
1229 length &= EPN_LDATA;
1230 if (length < ep->ep.maxpacket)
1231 bflag = true;
1232 }
1233
1234 _nbu2ss_start_transfer(ep->udc, ep, req, bflag);
1235 }
1236
1237 /*-------------------------------------------------------------------------*/
1238 /* Endpoint Toggle Reset */
_nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc * udc,u8 ep_adrs)1239 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs)
1240 {
1241 u8 num;
1242 u32 data;
1243
1244 if ((ep_adrs == 0) || (ep_adrs == 0x80))
1245 return;
1246
1247 num = (ep_adrs & 0x7F) - 1;
1248
1249 if (ep_adrs & USB_DIR_IN)
1250 data = EPN_IPIDCLR;
1251 else
1252 data = EPN_BCLR | EPN_OPIDCLR;
1253
1254 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
1255 }
1256
1257 /*-------------------------------------------------------------------------*/
1258 /* Endpoint STALL set */
_nbu2ss_set_endpoint_stall(struct nbu2ss_udc * udc,u8 ep_adrs,bool bstall)1259 static void _nbu2ss_set_endpoint_stall(struct nbu2ss_udc *udc,
1260 u8 ep_adrs, bool bstall)
1261 {
1262 u8 num, epnum;
1263 u32 data;
1264 struct nbu2ss_ep *ep;
1265 struct fc_regs __iomem *preg = udc->p_regs;
1266
1267 if ((ep_adrs == 0) || (ep_adrs == 0x80)) {
1268 if (bstall) {
1269 /* Set STALL */
1270 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL);
1271 } else {
1272 /* Clear STALL */
1273 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL);
1274 }
1275 } else {
1276 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK;
1277 num = epnum - 1;
1278 ep = &udc->ep[epnum];
1279
1280 if (bstall) {
1281 /* Set STALL */
1282 ep->halted = true;
1283
1284 if (ep_adrs & USB_DIR_IN)
1285 data = EPN_BCLR | EPN_ISTL;
1286 else
1287 data = EPN_OSTL_EN | EPN_OSTL;
1288
1289 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
1290 } else {
1291 if (ep_adrs & USB_DIR_IN) {
1292 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL
1293 , EPN_ISTL);
1294 } else {
1295 data =
1296 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL);
1297
1298 data &= ~EPN_OSTL;
1299 data |= EPN_OSTL_EN;
1300
1301 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL
1302 , data);
1303 }
1304
1305 /* Clear STALL */
1306 ep->stalled = false;
1307 if (ep->halted) {
1308 ep->halted = false;
1309 _nbu2ss_restert_transfer(ep);
1310 }
1311 }
1312 }
1313 }
1314
1315 /*-------------------------------------------------------------------------*/
_nbu2ss_set_test_mode(struct nbu2ss_udc * udc,u32 mode)1316 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode)
1317 {
1318 u32 data;
1319
1320 if (mode > MAX_TEST_MODE_NUM)
1321 return;
1322
1323 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode);
1324
1325 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL);
1326 data &= ~TEST_FORCE_ENABLE;
1327 data |= mode << TEST_MODE_SHIFT;
1328
1329 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data);
1330 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN);
1331 }
1332
1333 /*-------------------------------------------------------------------------*/
_nbu2ss_set_feature_device(struct nbu2ss_udc * udc,u16 selector,u16 wIndex)1334 static int _nbu2ss_set_feature_device(struct nbu2ss_udc *udc,
1335 u16 selector, u16 wIndex)
1336 {
1337 int result = -EOPNOTSUPP;
1338
1339 switch (selector) {
1340 case USB_DEVICE_REMOTE_WAKEUP:
1341 if (wIndex == 0x0000) {
1342 udc->remote_wakeup = U2F_ENABLE;
1343 result = 0;
1344 }
1345 break;
1346
1347 case USB_DEVICE_TEST_MODE:
1348 wIndex >>= 8;
1349 if (wIndex <= MAX_TEST_MODE_NUM)
1350 result = 0;
1351 break;
1352
1353 default:
1354 break;
1355 }
1356
1357 return result;
1358 }
1359
1360 /*-------------------------------------------------------------------------*/
_nbu2ss_get_ep_stall(struct nbu2ss_udc * udc,u8 ep_adrs)1361 static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs)
1362 {
1363 u8 epnum;
1364 u32 data = 0, bit_data;
1365 struct fc_regs __iomem *preg = udc->p_regs;
1366
1367 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK;
1368 if (epnum == 0) {
1369 data = _nbu2ss_readl(&preg->EP0_CONTROL);
1370 bit_data = EP0_STL;
1371
1372 } else {
1373 data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL);
1374 if ((data & EPN_EN) == 0)
1375 return -1;
1376
1377 if (ep_adrs & USB_ENDPOINT_DIR_MASK)
1378 bit_data = EPN_ISTL;
1379 else
1380 bit_data = EPN_OSTL;
1381 }
1382
1383 if ((data & bit_data) == 0)
1384 return 0;
1385 return 1;
1386 }
1387
1388 /*-------------------------------------------------------------------------*/
_nbu2ss_req_feature(struct nbu2ss_udc * udc,bool bset)1389 static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset)
1390 {
1391 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1392 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1393 u16 selector = le16_to_cpu(udc->ctrl.wValue);
1394 u16 wIndex = le16_to_cpu(udc->ctrl.wIndex);
1395 u8 ep_adrs;
1396 int result = -EOPNOTSUPP;
1397
1398 if ((udc->ctrl.wLength != 0x0000) ||
1399 (direction != USB_DIR_OUT)) {
1400 return -EINVAL;
1401 }
1402
1403 switch (recipient) {
1404 case USB_RECIP_DEVICE:
1405 if (bset)
1406 result =
1407 _nbu2ss_set_feature_device(udc, selector, wIndex);
1408 break;
1409
1410 case USB_RECIP_ENDPOINT:
1411 if (0x0000 == (wIndex & 0xFF70)) {
1412 if (selector == USB_ENDPOINT_HALT) {
1413 ep_adrs = wIndex & 0xFF;
1414 if (!bset) {
1415 _nbu2ss_endpoint_toggle_reset(udc,
1416 ep_adrs);
1417 }
1418
1419 _nbu2ss_set_endpoint_stall(udc, ep_adrs, bset);
1420
1421 result = 0;
1422 }
1423 }
1424 break;
1425
1426 default:
1427 break;
1428 }
1429
1430 if (result >= 0)
1431 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1432
1433 return result;
1434 }
1435
1436 /*-------------------------------------------------------------------------*/
_nbu2ss_get_speed(struct nbu2ss_udc * udc)1437 static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc)
1438 {
1439 u32 data;
1440 enum usb_device_speed speed = USB_SPEED_FULL;
1441
1442 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS);
1443 if (data & HIGH_SPEED)
1444 speed = USB_SPEED_HIGH;
1445
1446 return speed;
1447 }
1448
1449 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_set_stall(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)1450 static void _nbu2ss_epn_set_stall(struct nbu2ss_udc *udc,
1451 struct nbu2ss_ep *ep)
1452 {
1453 u8 ep_adrs;
1454 u32 regdata;
1455 int limit_cnt = 0;
1456
1457 struct fc_regs __iomem *preg = udc->p_regs;
1458
1459 if (ep->direct == USB_DIR_IN) {
1460 for (limit_cnt = 0
1461 ; limit_cnt < IN_DATA_EMPTY_COUNT
1462 ; limit_cnt++) {
1463 regdata = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1464
1465 if ((regdata & EPN_IN_DATA) == 0)
1466 break;
1467
1468 mdelay(1);
1469 }
1470 }
1471
1472 ep_adrs = ep->epnum | ep->direct;
1473 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1);
1474 }
1475
1476 /*-------------------------------------------------------------------------*/
std_req_get_status(struct nbu2ss_udc * udc)1477 static int std_req_get_status(struct nbu2ss_udc *udc)
1478 {
1479 u32 length;
1480 u16 status_data = 0;
1481 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1482 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1483 u8 ep_adrs;
1484 int result = -EINVAL;
1485
1486 if ((udc->ctrl.wValue != 0x0000) || (direction != USB_DIR_IN))
1487 return result;
1488
1489 length =
1490 min_t(u16, le16_to_cpu(udc->ctrl.wLength), sizeof(status_data));
1491 switch (recipient) {
1492 case USB_RECIP_DEVICE:
1493 if (udc->ctrl.wIndex == 0x0000) {
1494 if (udc->gadget.is_selfpowered)
1495 status_data |= BIT(USB_DEVICE_SELF_POWERED);
1496
1497 if (udc->remote_wakeup)
1498 status_data |= BIT(USB_DEVICE_REMOTE_WAKEUP);
1499
1500 result = 0;
1501 }
1502 break;
1503
1504 case USB_RECIP_ENDPOINT:
1505 if (0x0000 == (le16_to_cpu(udc->ctrl.wIndex) & 0xFF70)) {
1506 ep_adrs = (u8)(le16_to_cpu(udc->ctrl.wIndex) & 0xFF);
1507 result = _nbu2ss_get_ep_stall(udc, ep_adrs);
1508
1509 if (result > 0)
1510 status_data |= BIT(USB_ENDPOINT_HALT);
1511 }
1512 break;
1513
1514 default:
1515 break;
1516 }
1517
1518 if (result >= 0) {
1519 memcpy(udc->ep0_buf, &status_data, length);
1520 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length);
1521 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req);
1522
1523 } else {
1524 dev_err(udc->dev, " Error GET_STATUS\n");
1525 }
1526
1527 return result;
1528 }
1529
1530 /*-------------------------------------------------------------------------*/
std_req_clear_feature(struct nbu2ss_udc * udc)1531 static int std_req_clear_feature(struct nbu2ss_udc *udc)
1532 {
1533 return _nbu2ss_req_feature(udc, false);
1534 }
1535
1536 /*-------------------------------------------------------------------------*/
std_req_set_feature(struct nbu2ss_udc * udc)1537 static int std_req_set_feature(struct nbu2ss_udc *udc)
1538 {
1539 return _nbu2ss_req_feature(udc, true);
1540 }
1541
1542 /*-------------------------------------------------------------------------*/
std_req_set_address(struct nbu2ss_udc * udc)1543 static int std_req_set_address(struct nbu2ss_udc *udc)
1544 {
1545 int result = 0;
1546 u32 wValue = le16_to_cpu(udc->ctrl.wValue);
1547
1548 if ((udc->ctrl.bRequestType != 0x00) ||
1549 (udc->ctrl.wIndex != 0x0000) ||
1550 (udc->ctrl.wLength != 0x0000)) {
1551 return -EINVAL;
1552 }
1553
1554 if (wValue != (wValue & 0x007F))
1555 return -EINVAL;
1556
1557 wValue <<= USB_ADRS_SHIFT;
1558
1559 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue);
1560 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1561
1562 return result;
1563 }
1564
1565 /*-------------------------------------------------------------------------*/
std_req_set_configuration(struct nbu2ss_udc * udc)1566 static int std_req_set_configuration(struct nbu2ss_udc *udc)
1567 {
1568 u32 config_value = (u32)(le16_to_cpu(udc->ctrl.wValue) & 0x00ff);
1569
1570 if ((udc->ctrl.wIndex != 0x0000) ||
1571 (udc->ctrl.wLength != 0x0000) ||
1572 (udc->ctrl.bRequestType != 0x00)) {
1573 return -EINVAL;
1574 }
1575
1576 udc->curr_config = config_value;
1577
1578 if (config_value > 0) {
1579 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF);
1580 udc->devstate = USB_STATE_CONFIGURED;
1581
1582 } else {
1583 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF);
1584 udc->devstate = USB_STATE_ADDRESS;
1585 }
1586
1587 return 0;
1588 }
1589
1590 /*-------------------------------------------------------------------------*/
_nbu2ss_read_request_data(struct nbu2ss_udc * udc,u32 * pdata)1591 static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata)
1592 {
1593 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0);
1594 pdata++;
1595 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1);
1596 }
1597
1598 /*-------------------------------------------------------------------------*/
_nbu2ss_decode_request(struct nbu2ss_udc * udc)1599 static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc)
1600 {
1601 bool bcall_back = true;
1602 int nret = -EINVAL;
1603 struct usb_ctrlrequest *p_ctrl;
1604
1605 p_ctrl = &udc->ctrl;
1606 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl);
1607
1608 /* ep0 state control */
1609 if (p_ctrl->wLength == 0) {
1610 udc->ep0state = EP0_IN_STATUS_PHASE;
1611
1612 } else {
1613 if (p_ctrl->bRequestType & USB_DIR_IN)
1614 udc->ep0state = EP0_IN_DATA_PHASE;
1615 else
1616 udc->ep0state = EP0_OUT_DATA_PHASE;
1617 }
1618
1619 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1620 switch (p_ctrl->bRequest) {
1621 case USB_REQ_GET_STATUS:
1622 nret = std_req_get_status(udc);
1623 bcall_back = false;
1624 break;
1625
1626 case USB_REQ_CLEAR_FEATURE:
1627 nret = std_req_clear_feature(udc);
1628 bcall_back = false;
1629 break;
1630
1631 case USB_REQ_SET_FEATURE:
1632 nret = std_req_set_feature(udc);
1633 bcall_back = false;
1634 break;
1635
1636 case USB_REQ_SET_ADDRESS:
1637 nret = std_req_set_address(udc);
1638 bcall_back = false;
1639 break;
1640
1641 case USB_REQ_SET_CONFIGURATION:
1642 nret = std_req_set_configuration(udc);
1643 break;
1644
1645 default:
1646 break;
1647 }
1648 }
1649
1650 if (!bcall_back) {
1651 if (udc->ep0state == EP0_IN_STATUS_PHASE) {
1652 if (nret >= 0) {
1653 /*--------------------------------------*/
1654 /* Status Stage */
1655 nret = EP0_send_NULL(udc, true);
1656 }
1657 }
1658
1659 } else {
1660 spin_unlock(&udc->lock);
1661 nret = udc->driver->setup(&udc->gadget, &udc->ctrl);
1662 spin_lock(&udc->lock);
1663 }
1664
1665 if (nret < 0)
1666 udc->ep0state = EP0_IDLE;
1667
1668 return nret;
1669 }
1670
1671 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_in_data_stage(struct nbu2ss_udc * udc)1672 static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc)
1673 {
1674 int nret;
1675 struct nbu2ss_req *req;
1676 struct nbu2ss_ep *ep = &udc->ep[0];
1677
1678 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1679 if (!req)
1680 req = &udc->ep0_req;
1681
1682 req->req.actual += req->div_len;
1683 req->div_len = 0;
1684
1685 nret = _nbu2ss_ep0_in_transfer(udc, req);
1686 if (nret == 0) {
1687 udc->ep0state = EP0_OUT_STATUS_PAHSE;
1688 EP0_receive_NULL(udc, true);
1689 }
1690
1691 return 0;
1692 }
1693
1694 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_out_data_stage(struct nbu2ss_udc * udc)1695 static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc)
1696 {
1697 int nret;
1698 struct nbu2ss_req *req;
1699 struct nbu2ss_ep *ep = &udc->ep[0];
1700
1701 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1702 if (!req)
1703 req = &udc->ep0_req;
1704
1705 nret = _nbu2ss_ep0_out_transfer(udc, req);
1706 if (nret == 0) {
1707 udc->ep0state = EP0_IN_STATUS_PHASE;
1708 EP0_send_NULL(udc, true);
1709
1710 } else if (nret < 0) {
1711 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR);
1712 req->req.status = nret;
1713 }
1714
1715 return 0;
1716 }
1717
1718 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_status_stage(struct nbu2ss_udc * udc)1719 static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc)
1720 {
1721 struct nbu2ss_req *req;
1722 struct nbu2ss_ep *ep = &udc->ep[0];
1723
1724 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1725 if (!req) {
1726 req = &udc->ep0_req;
1727 if (req->req.complete)
1728 req->req.complete(&ep->ep, &req->req);
1729
1730 } else {
1731 if (req->req.complete)
1732 _nbu2ss_ep_done(ep, req, 0);
1733 }
1734
1735 udc->ep0state = EP0_IDLE;
1736
1737 return 0;
1738 }
1739
1740 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_int(struct nbu2ss_udc * udc)1741 static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc)
1742 {
1743 int i;
1744 u32 status;
1745 u32 intr;
1746 int nret = -1;
1747
1748 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS);
1749 intr = status & EP0_STATUS_RW_BIT;
1750 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~intr);
1751
1752 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT
1753 | STG_END_INT | EP0_OUT_NULL_INT);
1754
1755 if (status == 0) {
1756 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__);
1757 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr);
1758 return;
1759 }
1760
1761 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1762 udc->gadget.speed = _nbu2ss_get_speed(udc);
1763
1764 for (i = 0; i < EP0_END_XFER; i++) {
1765 switch (udc->ep0state) {
1766 case EP0_IDLE:
1767 if (status & SETUP_INT) {
1768 status = 0;
1769 nret = _nbu2ss_decode_request(udc);
1770 }
1771 break;
1772
1773 case EP0_IN_DATA_PHASE:
1774 if (status & EP0_IN_INT) {
1775 status &= ~EP0_IN_INT;
1776 nret = _nbu2ss_ep0_in_data_stage(udc);
1777 }
1778 break;
1779
1780 case EP0_OUT_DATA_PHASE:
1781 if (status & EP0_OUT_INT) {
1782 status &= ~EP0_OUT_INT;
1783 nret = _nbu2ss_ep0_out_data_stage(udc);
1784 }
1785 break;
1786
1787 case EP0_IN_STATUS_PHASE:
1788 if ((status & STG_END_INT) || (status & SETUP_INT)) {
1789 status &= ~(STG_END_INT | EP0_IN_INT);
1790 nret = _nbu2ss_ep0_status_stage(udc);
1791 }
1792 break;
1793
1794 case EP0_OUT_STATUS_PAHSE:
1795 if ((status & STG_END_INT) || (status & SETUP_INT) ||
1796 (status & EP0_OUT_NULL_INT)) {
1797 status &= ~(STG_END_INT
1798 | EP0_OUT_INT
1799 | EP0_OUT_NULL_INT);
1800
1801 nret = _nbu2ss_ep0_status_stage(udc);
1802 }
1803
1804 break;
1805
1806 default:
1807 status = 0;
1808 break;
1809 }
1810
1811 if (status == 0)
1812 break;
1813 }
1814
1815 if (nret < 0) {
1816 /* Send Stall */
1817 _nbu2ss_set_endpoint_stall(udc, 0, true);
1818 }
1819 }
1820
1821 /*-------------------------------------------------------------------------*/
_nbu2ss_ep_done(struct nbu2ss_ep * ep,struct nbu2ss_req * req,int status)1822 static void _nbu2ss_ep_done(struct nbu2ss_ep *ep,
1823 struct nbu2ss_req *req,
1824 int status)
1825 {
1826 struct nbu2ss_udc *udc = ep->udc;
1827
1828 list_del_init(&req->queue);
1829
1830 if (status == -ECONNRESET)
1831 _nbu2ss_fifo_flush(udc, ep);
1832
1833 if (likely(req->req.status == -EINPROGRESS))
1834 req->req.status = status;
1835
1836 if (ep->stalled) {
1837 _nbu2ss_epn_set_stall(udc, ep);
1838 } else {
1839 if (!list_empty(&ep->queue))
1840 _nbu2ss_restert_transfer(ep);
1841 }
1842
1843 #ifdef USE_DMA
1844 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) &&
1845 (req->req.dma != 0))
1846 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT);
1847 #endif
1848
1849 spin_unlock(&udc->lock);
1850 req->req.complete(&ep->ep, &req->req);
1851 spin_lock(&udc->lock);
1852 }
1853
1854 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1855 static inline void _nbu2ss_epn_in_int(struct nbu2ss_udc *udc,
1856 struct nbu2ss_ep *ep,
1857 struct nbu2ss_req *req)
1858 {
1859 int result = 0;
1860 u32 status;
1861
1862 struct fc_regs __iomem *preg = udc->p_regs;
1863
1864 if (req->dma_flag)
1865 return; /* DMA is forwarded */
1866
1867 req->req.actual += req->div_len;
1868 req->div_len = 0;
1869
1870 if (req->req.actual != req->req.length) {
1871 /*---------------------------------------------------------*/
1872 /* remainder of data */
1873 result = _nbu2ss_epn_in_transfer(udc, ep, req);
1874
1875 } else {
1876 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) {
1877 status =
1878 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1879
1880 if ((status & EPN_IN_FULL) == 0) {
1881 /*-----------------------------------------*/
1882 /* 0 Length Packet */
1883 req->zero = false;
1884 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1885 }
1886 return;
1887 }
1888 }
1889
1890 if (result <= 0) {
1891 /*---------------------------------------------------------*/
1892 /* Complete */
1893 _nbu2ss_ep_done(ep, req, result);
1894 }
1895 }
1896
1897 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1898 static inline void _nbu2ss_epn_out_int(struct nbu2ss_udc *udc,
1899 struct nbu2ss_ep *ep,
1900 struct nbu2ss_req *req)
1901 {
1902 int result;
1903
1904 result = _nbu2ss_epn_out_transfer(udc, ep, req);
1905 if (result <= 0)
1906 _nbu2ss_ep_done(ep, req, result);
1907 }
1908
1909 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_dma_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1910 static inline void _nbu2ss_epn_in_dma_int(struct nbu2ss_udc *udc,
1911 struct nbu2ss_ep *ep,
1912 struct nbu2ss_req *req)
1913 {
1914 u32 mpkt;
1915 u32 size;
1916 struct usb_request *preq;
1917
1918 preq = &req->req;
1919
1920 if (!req->dma_flag)
1921 return;
1922
1923 preq->actual += req->div_len;
1924 req->div_len = 0;
1925 req->dma_flag = false;
1926
1927 #ifdef USE_DMA
1928 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN);
1929 #endif
1930
1931 if (preq->actual != preq->length) {
1932 _nbu2ss_epn_in_transfer(udc, ep, req);
1933 } else {
1934 mpkt = ep->ep.maxpacket;
1935 size = preq->actual % mpkt;
1936 if (size > 0) {
1937 if (((preq->actual & 0x03) == 0) && (size < mpkt))
1938 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0);
1939 } else {
1940 _nbu2ss_epn_in_int(udc, ep, req);
1941 }
1942 }
1943 }
1944
1945 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_dma_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1946 static inline void _nbu2ss_epn_out_dma_int(struct nbu2ss_udc *udc,
1947 struct nbu2ss_ep *ep,
1948 struct nbu2ss_req *req)
1949 {
1950 int i;
1951 u32 num;
1952 u32 dmacnt, ep_dmacnt;
1953 u32 mpkt;
1954 struct fc_regs __iomem *preg = udc->p_regs;
1955
1956 num = ep->epnum - 1;
1957
1958 if (req->req.actual == req->req.length) {
1959 if ((req->req.length % ep->ep.maxpacket) && !req->zero) {
1960 req->div_len = 0;
1961 req->dma_flag = false;
1962 _nbu2ss_ep_done(ep, req, 0);
1963 return;
1964 }
1965 }
1966
1967 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT)
1968 & EPN_DMACNT;
1969 ep_dmacnt >>= 16;
1970
1971 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
1972 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1)
1973 & DCR1_EPN_DMACNT;
1974 dmacnt >>= 16;
1975 if (ep_dmacnt == dmacnt)
1976 break;
1977 }
1978
1979 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_REQEN);
1980
1981 if (dmacnt != 0) {
1982 mpkt = ep->ep.maxpacket;
1983 if ((req->div_len % mpkt) == 0)
1984 req->div_len -= mpkt * dmacnt;
1985 }
1986
1987 if ((req->req.actual % ep->ep.maxpacket) > 0) {
1988 if (req->req.actual == req->div_len) {
1989 req->div_len = 0;
1990 req->dma_flag = false;
1991 _nbu2ss_ep_done(ep, req, 0);
1992 return;
1993 }
1994 }
1995
1996 req->req.actual += req->div_len;
1997 req->div_len = 0;
1998 req->dma_flag = false;
1999
2000 _nbu2ss_epn_out_int(udc, ep, req);
2001 }
2002
2003 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_int(struct nbu2ss_udc * udc,u32 epnum)2004 static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum)
2005 {
2006 u32 num;
2007 u32 status;
2008
2009 struct nbu2ss_req *req;
2010 struct nbu2ss_ep *ep = &udc->ep[epnum];
2011
2012 num = epnum - 1;
2013
2014 /* Interrupt Status */
2015 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
2016
2017 /* Interrupt Clear */
2018 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~status);
2019
2020 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
2021 if (!req) {
2022 /* pr_warn("=== %s(%d) req == NULL\n", __func__, epnum); */
2023 return;
2024 }
2025
2026 if (status & EPN_OUT_END_INT) {
2027 status &= ~EPN_OUT_INT;
2028 _nbu2ss_epn_out_dma_int(udc, ep, req);
2029 }
2030
2031 if (status & EPN_OUT_INT)
2032 _nbu2ss_epn_out_int(udc, ep, req);
2033
2034 if (status & EPN_IN_END_INT) {
2035 status &= ~EPN_IN_INT;
2036 _nbu2ss_epn_in_dma_int(udc, ep, req);
2037 }
2038
2039 if (status & EPN_IN_INT)
2040 _nbu2ss_epn_in_int(udc, ep, req);
2041 }
2042
2043 /*-------------------------------------------------------------------------*/
_nbu2ss_ep_int(struct nbu2ss_udc * udc,u32 epnum)2044 static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum)
2045 {
2046 if (epnum == 0)
2047 _nbu2ss_ep0_int(udc);
2048 else
2049 _nbu2ss_epn_int(udc, epnum);
2050 }
2051
2052 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_enable(struct nbu2ss_udc * udc)2053 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc)
2054 {
2055 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR));
2056 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT);
2057 }
2058
2059 /*-------------------------------------------------------------------------*/
_nbu2ss_nuke(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,int status)2060 static int _nbu2ss_nuke(struct nbu2ss_udc *udc,
2061 struct nbu2ss_ep *ep,
2062 int status)
2063 {
2064 struct nbu2ss_req *req, *n;
2065
2066 /* Endpoint Disable */
2067 _nbu2ss_epn_exit(udc, ep);
2068
2069 /* DMA Disable */
2070 _nbu2ss_ep_dma_exit(udc, ep);
2071
2072 if (list_empty(&ep->queue))
2073 return 0;
2074
2075 /* called with irqs blocked */
2076 list_for_each_entry_safe(req, n, &ep->queue, queue) {
2077 _nbu2ss_ep_done(ep, req, status);
2078 }
2079
2080 return 0;
2081 }
2082
2083 /*-------------------------------------------------------------------------*/
_nbu2ss_quiesce(struct nbu2ss_udc * udc)2084 static void _nbu2ss_quiesce(struct nbu2ss_udc *udc)
2085 {
2086 struct nbu2ss_ep *ep;
2087
2088 udc->gadget.speed = USB_SPEED_UNKNOWN;
2089
2090 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN);
2091
2092 /* Endpoint n */
2093 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2094 _nbu2ss_nuke(udc, ep, -ESHUTDOWN);
2095 }
2096 }
2097
2098 /*-------------------------------------------------------------------------*/
_nbu2ss_pullup(struct nbu2ss_udc * udc,int is_on)2099 static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on)
2100 {
2101 u32 reg_dt;
2102
2103 if (udc->vbus_active == 0)
2104 return -ESHUTDOWN;
2105
2106 if (is_on) {
2107 /* D+ Pullup */
2108 if (udc->driver) {
2109 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL)
2110 | PUE2) & ~(u32)CONNECTB;
2111
2112 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2113 }
2114
2115 } else {
2116 /* D+ Pulldown */
2117 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB)
2118 & ~(u32)PUE2;
2119
2120 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2121 udc->gadget.speed = USB_SPEED_UNKNOWN;
2122 }
2123
2124 return 0;
2125 }
2126
2127 /*-------------------------------------------------------------------------*/
_nbu2ss_fifo_flush(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)2128 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
2129 {
2130 struct fc_regs __iomem *p = udc->p_regs;
2131
2132 if (udc->vbus_active == 0)
2133 return;
2134
2135 if (ep->epnum == 0) {
2136 /* EP0 */
2137 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR);
2138
2139 } else {
2140 /* EPN */
2141 _nbu2ss_ep_dma_abort(udc, ep);
2142 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPN_BCLR);
2143 }
2144 }
2145
2146 /*-------------------------------------------------------------------------*/
_nbu2ss_enable_controller(struct nbu2ss_udc * udc)2147 static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc)
2148 {
2149 int waitcnt = 0;
2150
2151 if (udc->udc_enabled)
2152 return 0;
2153
2154 /* Reset */
2155 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2156 udelay(EPC_RST_DISABLE_TIME); /* 1us wait */
2157
2158 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD);
2159 mdelay(EPC_DIRPD_DISABLE_TIME); /* 1ms wait */
2160
2161 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2162
2163 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE);
2164
2165 _nbu2ss_writel(&udc->p_regs->AHBMCTR,
2166 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE);
2167
2168 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) {
2169 waitcnt++;
2170 udelay(1); /* 1us wait */
2171 if (waitcnt == EPC_PLL_LOCK_COUNT) {
2172 dev_err(udc->dev, "*** Reset Cancel failed\n");
2173 return -EINVAL;
2174 }
2175 }
2176
2177 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET);
2178
2179 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV));
2180
2181 /* EP0 */
2182 _nbu2ss_ep0_enable(udc);
2183
2184 /* USB Interrupt Enable */
2185 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT);
2186
2187 udc->udc_enabled = true;
2188
2189 return 0;
2190 }
2191
2192 /*-------------------------------------------------------------------------*/
_nbu2ss_reset_controller(struct nbu2ss_udc * udc)2193 static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc)
2194 {
2195 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST);
2196 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2197 }
2198
2199 /*-------------------------------------------------------------------------*/
_nbu2ss_disable_controller(struct nbu2ss_udc * udc)2200 static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc)
2201 {
2202 if (udc->udc_enabled) {
2203 udc->udc_enabled = false;
2204 _nbu2ss_reset_controller(udc);
2205 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2206 }
2207 }
2208
2209 /*-------------------------------------------------------------------------*/
_nbu2ss_check_vbus(struct nbu2ss_udc * udc)2210 static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)
2211 {
2212 int nret;
2213 u32 reg_dt;
2214
2215 /* chattering */
2216 mdelay(VBUS_CHATTERING_MDELAY); /* wait (ms) */
2217
2218 /* VBUS ON Check*/
2219 reg_dt = gpiod_get_value(vbus_gpio);
2220 if (reg_dt == 0) {
2221 udc->linux_suspended = 0;
2222
2223 _nbu2ss_reset_controller(udc);
2224 dev_info(udc->dev, " ----- VBUS OFF\n");
2225
2226 if (udc->vbus_active == 1) {
2227 /* VBUS OFF */
2228 udc->vbus_active = 0;
2229 if (udc->usb_suspended) {
2230 udc->usb_suspended = 0;
2231 /* _nbu2ss_reset_controller(udc); */
2232 }
2233 udc->devstate = USB_STATE_NOTATTACHED;
2234
2235 _nbu2ss_quiesce(udc);
2236 if (udc->driver) {
2237 spin_unlock(&udc->lock);
2238 udc->driver->disconnect(&udc->gadget);
2239 spin_lock(&udc->lock);
2240 }
2241
2242 _nbu2ss_disable_controller(udc);
2243 }
2244 } else {
2245 mdelay(5); /* wait (5ms) */
2246 reg_dt = gpiod_get_value(vbus_gpio);
2247 if (reg_dt == 0)
2248 return;
2249
2250 dev_info(udc->dev, " ----- VBUS ON\n");
2251
2252 if (udc->linux_suspended)
2253 return;
2254
2255 if (udc->vbus_active == 0) {
2256 /* VBUS ON */
2257 udc->vbus_active = 1;
2258 udc->devstate = USB_STATE_POWERED;
2259
2260 nret = _nbu2ss_enable_controller(udc);
2261 if (nret < 0) {
2262 _nbu2ss_disable_controller(udc);
2263 udc->vbus_active = 0;
2264 return;
2265 }
2266
2267 _nbu2ss_pullup(udc, 1);
2268
2269 #ifdef UDC_DEBUG_DUMP
2270 _nbu2ss_dump_register(udc);
2271 #endif /* UDC_DEBUG_DUMP */
2272
2273 } else {
2274 if (udc->devstate == USB_STATE_POWERED)
2275 _nbu2ss_pullup(udc, 1);
2276 }
2277 }
2278 }
2279
2280 /*-------------------------------------------------------------------------*/
_nbu2ss_int_bus_reset(struct nbu2ss_udc * udc)2281 static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc)
2282 {
2283 udc->devstate = USB_STATE_DEFAULT;
2284 udc->remote_wakeup = 0;
2285
2286 _nbu2ss_quiesce(udc);
2287
2288 udc->ep0state = EP0_IDLE;
2289 }
2290
2291 /*-------------------------------------------------------------------------*/
_nbu2ss_int_usb_resume(struct nbu2ss_udc * udc)2292 static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc)
2293 {
2294 if (udc->usb_suspended == 1) {
2295 udc->usb_suspended = 0;
2296 if (udc->driver && udc->driver->resume) {
2297 spin_unlock(&udc->lock);
2298 udc->driver->resume(&udc->gadget);
2299 spin_lock(&udc->lock);
2300 }
2301 }
2302 }
2303
2304 /*-------------------------------------------------------------------------*/
_nbu2ss_int_usb_suspend(struct nbu2ss_udc * udc)2305 static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc)
2306 {
2307 u32 reg_dt;
2308
2309 if (udc->usb_suspended == 0) {
2310 reg_dt = gpiod_get_value(vbus_gpio);
2311
2312 if (reg_dt == 0)
2313 return;
2314
2315 udc->usb_suspended = 1;
2316 if (udc->driver && udc->driver->suspend) {
2317 spin_unlock(&udc->lock);
2318 udc->driver->suspend(&udc->gadget);
2319 spin_lock(&udc->lock);
2320 }
2321
2322 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND);
2323 }
2324 }
2325
2326 /*-------------------------------------------------------------------------*/
2327 /* VBUS (GPIO153) Interrupt */
_nbu2ss_vbus_irq(int irq,void * _udc)2328 static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc)
2329 {
2330 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2331
2332 spin_lock(&udc->lock);
2333 _nbu2ss_check_vbus(udc);
2334 spin_unlock(&udc->lock);
2335
2336 return IRQ_HANDLED;
2337 }
2338
2339 /*-------------------------------------------------------------------------*/
2340 /* Interrupt (udc) */
_nbu2ss_udc_irq(int irq,void * _udc)2341 static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc)
2342 {
2343 u8 suspend_flag = 0;
2344 u32 status;
2345 u32 epnum, int_bit;
2346
2347 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2348 struct fc_regs __iomem *preg = udc->p_regs;
2349
2350 if (gpiod_get_value(vbus_gpio) == 0) {
2351 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2352 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2353 return IRQ_HANDLED;
2354 }
2355
2356 spin_lock(&udc->lock);
2357
2358 for (;;) {
2359 if (gpiod_get_value(vbus_gpio) == 0) {
2360 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2361 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2362 status = 0;
2363 } else {
2364 status = _nbu2ss_readl(&preg->USB_INT_STA);
2365 }
2366
2367 if (status == 0)
2368 break;
2369
2370 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW));
2371
2372 if (status & USB_RST_INT) {
2373 /* USB Reset */
2374 _nbu2ss_int_bus_reset(udc);
2375 }
2376
2377 if (status & RSUM_INT) {
2378 /* Resume */
2379 _nbu2ss_int_usb_resume(udc);
2380 }
2381
2382 if (status & SPND_INT) {
2383 /* Suspend */
2384 suspend_flag = 1;
2385 }
2386
2387 if (status & EPN_INT) {
2388 /* EP INT */
2389 int_bit = status >> 8;
2390
2391 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) {
2392 if (0x01 & int_bit)
2393 _nbu2ss_ep_int(udc, epnum);
2394
2395 int_bit >>= 1;
2396
2397 if (int_bit == 0)
2398 break;
2399 }
2400 }
2401 }
2402
2403 if (suspend_flag)
2404 _nbu2ss_int_usb_suspend(udc);
2405
2406 spin_unlock(&udc->lock);
2407
2408 return IRQ_HANDLED;
2409 }
2410
2411 /*-------------------------------------------------------------------------*/
2412 /* usb_ep_ops */
nbu2ss_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)2413 static int nbu2ss_ep_enable(struct usb_ep *_ep,
2414 const struct usb_endpoint_descriptor *desc)
2415 {
2416 u8 ep_type;
2417 unsigned long flags;
2418
2419 struct nbu2ss_ep *ep;
2420 struct nbu2ss_udc *udc;
2421
2422 if (!_ep || !desc) {
2423 pr_err(" *** %s, bad param\n", __func__);
2424 return -EINVAL;
2425 }
2426
2427 ep = container_of(_ep, struct nbu2ss_ep, ep);
2428 if (!ep->udc) {
2429 pr_err(" *** %s, ep == NULL !!\n", __func__);
2430 return -EINVAL;
2431 }
2432
2433 ep_type = usb_endpoint_type(desc);
2434 if ((ep_type == USB_ENDPOINT_XFER_CONTROL) ||
2435 (ep_type == USB_ENDPOINT_XFER_ISOC)) {
2436 pr_err(" *** %s, bat bmAttributes\n", __func__);
2437 return -EINVAL;
2438 }
2439
2440 udc = ep->udc;
2441 if (udc->vbus_active == 0)
2442 return -ESHUTDOWN;
2443
2444 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
2445 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__);
2446 return -ESHUTDOWN;
2447 }
2448
2449 spin_lock_irqsave(&udc->lock, flags);
2450
2451 ep->desc = desc;
2452 ep->epnum = usb_endpoint_num(desc);
2453 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
2454 ep->ep_type = ep_type;
2455 ep->wedged = 0;
2456 ep->halted = false;
2457 ep->stalled = false;
2458
2459 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
2460
2461 /* DMA setting */
2462 _nbu2ss_ep_dma_init(udc, ep);
2463
2464 /* Endpoint setting */
2465 _nbu2ss_ep_init(udc, ep);
2466
2467 spin_unlock_irqrestore(&udc->lock, flags);
2468
2469 return 0;
2470 }
2471
2472 /*-------------------------------------------------------------------------*/
nbu2ss_ep_disable(struct usb_ep * _ep)2473 static int nbu2ss_ep_disable(struct usb_ep *_ep)
2474 {
2475 struct nbu2ss_ep *ep;
2476 struct nbu2ss_udc *udc;
2477 unsigned long flags;
2478
2479 if (!_ep) {
2480 pr_err(" *** %s, bad param\n", __func__);
2481 return -EINVAL;
2482 }
2483
2484 ep = container_of(_ep, struct nbu2ss_ep, ep);
2485 if (!ep->udc) {
2486 pr_err("udc: *** %s, ep == NULL !!\n", __func__);
2487 return -EINVAL;
2488 }
2489
2490 udc = ep->udc;
2491 if (udc->vbus_active == 0)
2492 return -ESHUTDOWN;
2493
2494 spin_lock_irqsave(&udc->lock, flags);
2495 _nbu2ss_nuke(udc, ep, -EINPROGRESS); /* dequeue request */
2496 spin_unlock_irqrestore(&udc->lock, flags);
2497
2498 return 0;
2499 }
2500
2501 /*-------------------------------------------------------------------------*/
nbu2ss_ep_alloc_request(struct usb_ep * ep,gfp_t gfp_flags)2502 static struct usb_request *nbu2ss_ep_alloc_request(struct usb_ep *ep,
2503 gfp_t gfp_flags)
2504 {
2505 struct nbu2ss_req *req;
2506
2507 req = kzalloc(sizeof(*req), gfp_flags);
2508 if (!req)
2509 return NULL;
2510
2511 #ifdef USE_DMA
2512 req->req.dma = DMA_ADDR_INVALID;
2513 #endif
2514 INIT_LIST_HEAD(&req->queue);
2515
2516 return &req->req;
2517 }
2518
2519 /*-------------------------------------------------------------------------*/
nbu2ss_ep_free_request(struct usb_ep * _ep,struct usb_request * _req)2520 static void nbu2ss_ep_free_request(struct usb_ep *_ep,
2521 struct usb_request *_req)
2522 {
2523 struct nbu2ss_req *req;
2524
2525 if (_req) {
2526 req = container_of(_req, struct nbu2ss_req, req);
2527
2528 kfree(req);
2529 }
2530 }
2531
2532 /*-------------------------------------------------------------------------*/
nbu2ss_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)2533 static int nbu2ss_ep_queue(struct usb_ep *_ep,
2534 struct usb_request *_req, gfp_t gfp_flags)
2535 {
2536 struct nbu2ss_req *req;
2537 struct nbu2ss_ep *ep;
2538 struct nbu2ss_udc *udc;
2539 unsigned long flags;
2540 bool bflag;
2541 int result = -EINVAL;
2542
2543 /* catch various bogus parameters */
2544 if (!_ep || !_req) {
2545 if (!_ep)
2546 pr_err("udc: %s --- _ep == NULL\n", __func__);
2547
2548 if (!_req)
2549 pr_err("udc: %s --- _req == NULL\n", __func__);
2550
2551 return -EINVAL;
2552 }
2553
2554 req = container_of(_req, struct nbu2ss_req, req);
2555 if (unlikely(!_req->complete ||
2556 !_req->buf ||
2557 !list_empty(&req->queue))) {
2558 if (!_req->complete)
2559 pr_err("udc: %s --- !_req->complete\n", __func__);
2560
2561 if (!_req->buf)
2562 pr_err("udc:%s --- !_req->buf\n", __func__);
2563
2564 if (!list_empty(&req->queue))
2565 pr_err("%s --- !list_empty(&req->queue)\n", __func__);
2566
2567 return -EINVAL;
2568 }
2569
2570 ep = container_of(_ep, struct nbu2ss_ep, ep);
2571 udc = ep->udc;
2572
2573 if (udc->vbus_active == 0) {
2574 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n");
2575 return -ESHUTDOWN;
2576 }
2577
2578 if (unlikely(!udc->driver)) {
2579 dev_err(udc->dev, "%s, bogus device state %p\n", __func__,
2580 udc->driver);
2581 return -ESHUTDOWN;
2582 }
2583
2584 spin_lock_irqsave(&udc->lock, flags);
2585
2586 #ifdef USE_DMA
2587 if ((uintptr_t)req->req.buf & 0x3)
2588 req->unaligned = true;
2589 else
2590 req->unaligned = false;
2591
2592 if (req->unaligned) {
2593 if (!ep->virt_buf)
2594 ep->virt_buf = dma_alloc_coherent(udc->dev, PAGE_SIZE,
2595 &ep->phys_buf,
2596 GFP_ATOMIC | GFP_DMA);
2597 if (ep->epnum > 0) {
2598 if (ep->direct == USB_DIR_IN)
2599 memcpy(ep->virt_buf, req->req.buf,
2600 req->req.length);
2601 }
2602 }
2603
2604 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) &&
2605 (req->req.dma != 0))
2606 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT);
2607 #endif
2608
2609 _req->status = -EINPROGRESS;
2610 _req->actual = 0;
2611
2612 bflag = list_empty(&ep->queue);
2613 list_add_tail(&req->queue, &ep->queue);
2614
2615 if (bflag && !ep->stalled) {
2616 result = _nbu2ss_start_transfer(udc, ep, req, false);
2617 if (result < 0) {
2618 dev_err(udc->dev, " *** %s, result = %d\n", __func__,
2619 result);
2620 list_del(&req->queue);
2621 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) {
2622 #ifdef USE_DMA
2623 if (req->req.length < 4 &&
2624 req->req.length == req->req.actual)
2625 #else
2626 if (req->req.length == req->req.actual)
2627 #endif
2628 _nbu2ss_ep_done(ep, req, result);
2629 }
2630 }
2631
2632 spin_unlock_irqrestore(&udc->lock, flags);
2633
2634 return 0;
2635 }
2636
2637 /*-------------------------------------------------------------------------*/
nbu2ss_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)2638 static int nbu2ss_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
2639 {
2640 struct nbu2ss_req *req;
2641 struct nbu2ss_ep *ep;
2642 struct nbu2ss_udc *udc;
2643 unsigned long flags;
2644
2645 /* catch various bogus parameters */
2646 if (!_ep || !_req) {
2647 /* pr_err("%s, bad param(1)\n", __func__); */
2648 return -EINVAL;
2649 }
2650
2651 ep = container_of(_ep, struct nbu2ss_ep, ep);
2652
2653 udc = ep->udc;
2654 if (!udc)
2655 return -EINVAL;
2656
2657 spin_lock_irqsave(&udc->lock, flags);
2658
2659 /* make sure it's actually queued on this endpoint */
2660 list_for_each_entry(req, &ep->queue, queue) {
2661 if (&req->req == _req) {
2662 _nbu2ss_ep_done(ep, req, -ECONNRESET);
2663 spin_unlock_irqrestore(&udc->lock, flags);
2664 return 0;
2665 }
2666 }
2667
2668 spin_unlock_irqrestore(&udc->lock, flags);
2669
2670 pr_debug("%s no queue(EINVAL)\n", __func__);
2671
2672 return -EINVAL;
2673 }
2674
2675 /*-------------------------------------------------------------------------*/
nbu2ss_ep_set_halt(struct usb_ep * _ep,int value)2676 static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value)
2677 {
2678 u8 ep_adrs;
2679 unsigned long flags;
2680
2681 struct nbu2ss_ep *ep;
2682 struct nbu2ss_udc *udc;
2683
2684 if (!_ep) {
2685 pr_err("%s, bad param\n", __func__);
2686 return -EINVAL;
2687 }
2688
2689 ep = container_of(_ep, struct nbu2ss_ep, ep);
2690
2691 udc = ep->udc;
2692 if (!udc) {
2693 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__);
2694 return -EINVAL;
2695 }
2696
2697 spin_lock_irqsave(&udc->lock, flags);
2698
2699 ep_adrs = ep->epnum | ep->direct;
2700 if (value == 0) {
2701 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value);
2702 ep->stalled = false;
2703 } else {
2704 if (list_empty(&ep->queue))
2705 _nbu2ss_epn_set_stall(udc, ep);
2706 else
2707 ep->stalled = true;
2708 }
2709
2710 if (value == 0)
2711 ep->wedged = 0;
2712
2713 spin_unlock_irqrestore(&udc->lock, flags);
2714
2715 return 0;
2716 }
2717
nbu2ss_ep_set_wedge(struct usb_ep * _ep)2718 static int nbu2ss_ep_set_wedge(struct usb_ep *_ep)
2719 {
2720 return nbu2ss_ep_set_halt(_ep, 1);
2721 }
2722
2723 /*-------------------------------------------------------------------------*/
nbu2ss_ep_fifo_status(struct usb_ep * _ep)2724 static int nbu2ss_ep_fifo_status(struct usb_ep *_ep)
2725 {
2726 u32 data;
2727 struct nbu2ss_ep *ep;
2728 struct nbu2ss_udc *udc;
2729 unsigned long flags;
2730 struct fc_regs __iomem *preg;
2731
2732 if (!_ep) {
2733 pr_err("%s, bad param\n", __func__);
2734 return -EINVAL;
2735 }
2736
2737 ep = container_of(_ep, struct nbu2ss_ep, ep);
2738
2739 udc = ep->udc;
2740 if (!udc) {
2741 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2742 return -EINVAL;
2743 }
2744
2745 preg = udc->p_regs;
2746
2747 data = gpiod_get_value(vbus_gpio);
2748 if (data == 0)
2749 return -EINVAL;
2750
2751 spin_lock_irqsave(&udc->lock, flags);
2752
2753 if (ep->epnum == 0) {
2754 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA;
2755
2756 } else {
2757 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT)
2758 & EPN_LDATA;
2759 }
2760
2761 spin_unlock_irqrestore(&udc->lock, flags);
2762
2763 return 0;
2764 }
2765
2766 /*-------------------------------------------------------------------------*/
nbu2ss_ep_fifo_flush(struct usb_ep * _ep)2767 static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep)
2768 {
2769 u32 data;
2770 struct nbu2ss_ep *ep;
2771 struct nbu2ss_udc *udc;
2772 unsigned long flags;
2773
2774 if (!_ep) {
2775 pr_err("udc: %s, bad param\n", __func__);
2776 return;
2777 }
2778
2779 ep = container_of(_ep, struct nbu2ss_ep, ep);
2780
2781 udc = ep->udc;
2782 if (!udc) {
2783 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2784 return;
2785 }
2786
2787 data = gpiod_get_value(vbus_gpio);
2788 if (data == 0)
2789 return;
2790
2791 spin_lock_irqsave(&udc->lock, flags);
2792 _nbu2ss_fifo_flush(udc, ep);
2793 spin_unlock_irqrestore(&udc->lock, flags);
2794 }
2795
2796 /*-------------------------------------------------------------------------*/
2797 static const struct usb_ep_ops nbu2ss_ep_ops = {
2798 .enable = nbu2ss_ep_enable,
2799 .disable = nbu2ss_ep_disable,
2800
2801 .alloc_request = nbu2ss_ep_alloc_request,
2802 .free_request = nbu2ss_ep_free_request,
2803
2804 .queue = nbu2ss_ep_queue,
2805 .dequeue = nbu2ss_ep_dequeue,
2806
2807 .set_halt = nbu2ss_ep_set_halt,
2808 .set_wedge = nbu2ss_ep_set_wedge,
2809
2810 .fifo_status = nbu2ss_ep_fifo_status,
2811 .fifo_flush = nbu2ss_ep_fifo_flush,
2812 };
2813
2814 /*-------------------------------------------------------------------------*/
2815 /* usb_gadget_ops */
2816
2817 /*-------------------------------------------------------------------------*/
nbu2ss_gad_get_frame(struct usb_gadget * pgadget)2818 static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget)
2819 {
2820 u32 data;
2821 struct nbu2ss_udc *udc;
2822
2823 if (!pgadget) {
2824 pr_err("udc: %s, bad param\n", __func__);
2825 return -EINVAL;
2826 }
2827
2828 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2829 data = gpiod_get_value(vbus_gpio);
2830 if (data == 0)
2831 return -EINVAL;
2832
2833 return _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME;
2834 }
2835
2836 /*-------------------------------------------------------------------------*/
nbu2ss_gad_wakeup(struct usb_gadget * pgadget)2837 static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget)
2838 {
2839 int i;
2840 u32 data;
2841
2842 struct nbu2ss_udc *udc;
2843
2844 if (!pgadget) {
2845 pr_err("%s, bad param\n", __func__);
2846 return -EINVAL;
2847 }
2848
2849 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2850
2851 data = gpiod_get_value(vbus_gpio);
2852 if (data == 0) {
2853 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data);
2854 return -EINVAL;
2855 }
2856
2857 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME);
2858
2859 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
2860 data = _nbu2ss_readl(&udc->p_regs->EPCTR);
2861
2862 if (data & PLL_LOCK)
2863 break;
2864 }
2865
2866 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME);
2867
2868 return 0;
2869 }
2870
2871 /*-------------------------------------------------------------------------*/
nbu2ss_gad_set_selfpowered(struct usb_gadget * pgadget,int is_selfpowered)2872 static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget,
2873 int is_selfpowered)
2874 {
2875 struct nbu2ss_udc *udc;
2876 unsigned long flags;
2877
2878 if (!pgadget) {
2879 pr_err("%s, bad param\n", __func__);
2880 return -EINVAL;
2881 }
2882
2883 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2884
2885 spin_lock_irqsave(&udc->lock, flags);
2886 pgadget->is_selfpowered = (is_selfpowered != 0);
2887 spin_unlock_irqrestore(&udc->lock, flags);
2888
2889 return 0;
2890 }
2891
2892 /*-------------------------------------------------------------------------*/
nbu2ss_gad_vbus_session(struct usb_gadget * pgadget,int is_active)2893 static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active)
2894 {
2895 return 0;
2896 }
2897
2898 /*-------------------------------------------------------------------------*/
nbu2ss_gad_vbus_draw(struct usb_gadget * pgadget,unsigned int mA)2899 static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA)
2900 {
2901 struct nbu2ss_udc *udc;
2902 unsigned long flags;
2903
2904 if (!pgadget) {
2905 pr_err("%s, bad param\n", __func__);
2906 return -EINVAL;
2907 }
2908
2909 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2910
2911 spin_lock_irqsave(&udc->lock, flags);
2912 udc->mA = mA;
2913 spin_unlock_irqrestore(&udc->lock, flags);
2914
2915 return 0;
2916 }
2917
2918 /*-------------------------------------------------------------------------*/
nbu2ss_gad_pullup(struct usb_gadget * pgadget,int is_on)2919 static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on)
2920 {
2921 struct nbu2ss_udc *udc;
2922 unsigned long flags;
2923
2924 if (!pgadget) {
2925 pr_err("%s, bad param\n", __func__);
2926 return -EINVAL;
2927 }
2928
2929 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2930
2931 if (!udc->driver) {
2932 pr_warn("%s, Not Regist Driver\n", __func__);
2933 return -EINVAL;
2934 }
2935
2936 if (udc->vbus_active == 0)
2937 return -ESHUTDOWN;
2938
2939 spin_lock_irqsave(&udc->lock, flags);
2940 _nbu2ss_pullup(udc, is_on);
2941 spin_unlock_irqrestore(&udc->lock, flags);
2942
2943 return 0;
2944 }
2945
2946 /*-------------------------------------------------------------------------*/
nbu2ss_gad_ioctl(struct usb_gadget * pgadget,unsigned int code,unsigned long param)2947 static int nbu2ss_gad_ioctl(struct usb_gadget *pgadget,
2948 unsigned int code, unsigned long param)
2949 {
2950 return 0;
2951 }
2952
2953 static const struct usb_gadget_ops nbu2ss_gadget_ops = {
2954 .get_frame = nbu2ss_gad_get_frame,
2955 .wakeup = nbu2ss_gad_wakeup,
2956 .set_selfpowered = nbu2ss_gad_set_selfpowered,
2957 .vbus_session = nbu2ss_gad_vbus_session,
2958 .vbus_draw = nbu2ss_gad_vbus_draw,
2959 .pullup = nbu2ss_gad_pullup,
2960 .ioctl = nbu2ss_gad_ioctl,
2961 };
2962
2963 static const struct {
2964 const char *name;
2965 const struct usb_ep_caps caps;
2966 } ep_info[NUM_ENDPOINTS] = {
2967 #define EP_INFO(_name, _caps) \
2968 { \
2969 .name = _name, \
2970 .caps = _caps, \
2971 }
2972
2973 EP_INFO("ep0",
2974 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
2975 EP_INFO("ep1-bulk",
2976 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2977 EP_INFO("ep2-bulk",
2978 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2979 EP_INFO("ep3in-int",
2980 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
2981 EP_INFO("ep4-iso",
2982 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2983 EP_INFO("ep5-iso",
2984 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2985 EP_INFO("ep6-bulk",
2986 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2987 EP_INFO("ep7-bulk",
2988 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2989 EP_INFO("ep8in-int",
2990 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
2991 EP_INFO("ep9-iso",
2992 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2993 EP_INFO("epa-iso",
2994 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2995 EP_INFO("epb-bulk",
2996 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2997 EP_INFO("epc-bulk",
2998 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2999 EP_INFO("epdin-int",
3000 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3001
3002 #undef EP_INFO
3003 };
3004
3005 /*-------------------------------------------------------------------------*/
nbu2ss_drv_ep_init(struct nbu2ss_udc * udc)3006 static void nbu2ss_drv_ep_init(struct nbu2ss_udc *udc)
3007 {
3008 int i;
3009
3010 INIT_LIST_HEAD(&udc->gadget.ep_list);
3011 udc->gadget.ep0 = &udc->ep[0].ep;
3012
3013 for (i = 0; i < NUM_ENDPOINTS; i++) {
3014 struct nbu2ss_ep *ep = &udc->ep[i];
3015
3016 ep->udc = udc;
3017 ep->desc = NULL;
3018
3019 ep->ep.driver_data = NULL;
3020 ep->ep.name = ep_info[i].name;
3021 ep->ep.caps = ep_info[i].caps;
3022 ep->ep.ops = &nbu2ss_ep_ops;
3023
3024 usb_ep_set_maxpacket_limit(&ep->ep,
3025 i == 0 ? EP0_PACKETSIZE
3026 : EP_PACKETSIZE);
3027
3028 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3029 INIT_LIST_HEAD(&ep->queue);
3030 }
3031
3032 list_del_init(&udc->ep[0].ep.ep_list);
3033 }
3034
3035 /*-------------------------------------------------------------------------*/
3036 /* platform_driver */
nbu2ss_drv_contest_init(struct platform_device * pdev,struct nbu2ss_udc * udc)3037 static int nbu2ss_drv_contest_init(struct platform_device *pdev,
3038 struct nbu2ss_udc *udc)
3039 {
3040 spin_lock_init(&udc->lock);
3041 udc->dev = &pdev->dev;
3042
3043 udc->gadget.is_selfpowered = 1;
3044 udc->devstate = USB_STATE_NOTATTACHED;
3045 udc->pdev = pdev;
3046 udc->mA = 0;
3047
3048 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3049
3050 /* init Endpoint */
3051 nbu2ss_drv_ep_init(udc);
3052
3053 /* init Gadget */
3054 udc->gadget.ops = &nbu2ss_gadget_ops;
3055 udc->gadget.ep0 = &udc->ep[0].ep;
3056 udc->gadget.speed = USB_SPEED_UNKNOWN;
3057 udc->gadget.name = driver_name;
3058 /* udc->gadget.is_dualspeed = 1; */
3059
3060 device_initialize(&udc->gadget.dev);
3061
3062 dev_set_name(&udc->gadget.dev, "gadget");
3063 udc->gadget.dev.parent = &pdev->dev;
3064 udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
3065
3066 return 0;
3067 }
3068
3069 /*
3070 * probe - binds to the platform device
3071 */
nbu2ss_drv_probe(struct platform_device * pdev)3072 static int nbu2ss_drv_probe(struct platform_device *pdev)
3073 {
3074 int status;
3075 struct nbu2ss_udc *udc;
3076 int irq;
3077 void __iomem *mmio_base;
3078
3079 udc = &udc_controller;
3080 memset(udc, 0, sizeof(struct nbu2ss_udc));
3081
3082 platform_set_drvdata(pdev, udc);
3083
3084 /* require I/O memory and IRQ to be provided as resources */
3085 mmio_base = devm_platform_ioremap_resource(pdev, 0);
3086 if (IS_ERR(mmio_base))
3087 return PTR_ERR(mmio_base);
3088
3089 irq = platform_get_irq(pdev, 0);
3090 if (irq < 0)
3091 return irq;
3092 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq,
3093 0, driver_name, udc);
3094
3095 /* IO Memory */
3096 udc->p_regs = (struct fc_regs __iomem *)mmio_base;
3097
3098 /* USB Function Controller Interrupt */
3099 if (status != 0) {
3100 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n");
3101 return status;
3102 }
3103
3104 /* Driver Initialization */
3105 status = nbu2ss_drv_contest_init(pdev, udc);
3106 if (status < 0) {
3107 /* Error */
3108 return status;
3109 }
3110
3111 /* VBUS Interrupt */
3112 vbus_irq = gpiod_to_irq(vbus_gpio);
3113 irq_set_irq_type(vbus_irq, IRQ_TYPE_EDGE_BOTH);
3114 status = request_irq(vbus_irq,
3115 _nbu2ss_vbus_irq, IRQF_SHARED, driver_name, udc);
3116
3117 if (status != 0) {
3118 dev_err(udc->dev, "request_irq(vbus_irq) failed\n");
3119 return status;
3120 }
3121
3122 return status;
3123 }
3124
3125 /*-------------------------------------------------------------------------*/
nbu2ss_drv_shutdown(struct platform_device * pdev)3126 static void nbu2ss_drv_shutdown(struct platform_device *pdev)
3127 {
3128 struct nbu2ss_udc *udc;
3129
3130 udc = platform_get_drvdata(pdev);
3131 if (!udc)
3132 return;
3133
3134 _nbu2ss_disable_controller(udc);
3135 }
3136
3137 /*-------------------------------------------------------------------------*/
nbu2ss_drv_remove(struct platform_device * pdev)3138 static int nbu2ss_drv_remove(struct platform_device *pdev)
3139 {
3140 struct nbu2ss_udc *udc;
3141 struct nbu2ss_ep *ep;
3142 int i;
3143
3144 udc = &udc_controller;
3145
3146 for (i = 0; i < NUM_ENDPOINTS; i++) {
3147 ep = &udc->ep[i];
3148 if (ep->virt_buf)
3149 dma_free_coherent(udc->dev, PAGE_SIZE, (void *)ep->virt_buf,
3150 ep->phys_buf);
3151 }
3152
3153 /* Interrupt Handler - Release */
3154 free_irq(vbus_irq, udc);
3155
3156 return 0;
3157 }
3158
3159 /*-------------------------------------------------------------------------*/
nbu2ss_drv_suspend(struct platform_device * pdev,pm_message_t state)3160 static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state)
3161 {
3162 struct nbu2ss_udc *udc;
3163
3164 udc = platform_get_drvdata(pdev);
3165 if (!udc)
3166 return 0;
3167
3168 if (udc->vbus_active) {
3169 udc->vbus_active = 0;
3170 udc->devstate = USB_STATE_NOTATTACHED;
3171 udc->linux_suspended = 1;
3172
3173 if (udc->usb_suspended) {
3174 udc->usb_suspended = 0;
3175 _nbu2ss_reset_controller(udc);
3176 }
3177
3178 _nbu2ss_quiesce(udc);
3179 }
3180 _nbu2ss_disable_controller(udc);
3181
3182 return 0;
3183 }
3184
3185 /*-------------------------------------------------------------------------*/
nbu2ss_drv_resume(struct platform_device * pdev)3186 static int nbu2ss_drv_resume(struct platform_device *pdev)
3187 {
3188 u32 data;
3189 struct nbu2ss_udc *udc;
3190
3191 udc = platform_get_drvdata(pdev);
3192 if (!udc)
3193 return 0;
3194
3195 data = gpiod_get_value(vbus_gpio);
3196 if (data) {
3197 udc->vbus_active = 1;
3198 udc->devstate = USB_STATE_POWERED;
3199 _nbu2ss_enable_controller(udc);
3200 _nbu2ss_pullup(udc, 1);
3201 }
3202
3203 udc->linux_suspended = 0;
3204
3205 return 0;
3206 }
3207
3208 static struct platform_driver udc_driver = {
3209 .probe = nbu2ss_drv_probe,
3210 .shutdown = nbu2ss_drv_shutdown,
3211 .remove = nbu2ss_drv_remove,
3212 .suspend = nbu2ss_drv_suspend,
3213 .resume = nbu2ss_drv_resume,
3214 .driver = {
3215 .name = driver_name,
3216 },
3217 };
3218
3219 module_platform_driver(udc_driver);
3220
3221 MODULE_DESCRIPTION(DRIVER_DESC);
3222 MODULE_AUTHOR("Renesas Electronics Corporation");
3223 MODULE_LICENSE("GPL");
3224