1 /*
2  * Driver for Amlogic Meson SPI communication controller (SPICC)
3  *
4  * Copyright (C) BayLibre, SAS
5  * Author: Neil Armstrong <narmstrong@baylibre.com>
6  *
7  * SPDX-License-Identifier: GPL-2.0+
8  */
9 
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/device.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <linux/types.h>
22 #include <linux/interrupt.h>
23 #include <linux/reset.h>
24 
25 /*
26  * The Meson SPICC controller could support DMA based transfers, but is not
27  * implemented by the vendor code, and while having the registers documentation
28  * it has never worked on the GXL Hardware.
29  * The PIO mode is the only mode implemented, and due to badly designed HW :
30  * - all transfers are cutted in 16 words burst because the FIFO hangs on
31  *   TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
32  *   FIFO max size chunk only
33  * - CS management is dumb, and goes UP between every burst, so is really a
34  *   "Data Valid" signal than a Chip Select, GPIO link should be used instead
35  *   to have a CS go down over the full transfer
36  */
37 
38 #define SPICC_MAX_BURST	128
39 
40 /* Register Map */
41 #define SPICC_RXDATA	0x00
42 
43 #define SPICC_TXDATA	0x04
44 
45 #define SPICC_CONREG	0x08
46 #define SPICC_ENABLE		BIT(0)
47 #define SPICC_MODE_MASTER	BIT(1)
48 #define SPICC_XCH		BIT(2)
49 #define SPICC_SMC		BIT(3)
50 #define SPICC_POL		BIT(4)
51 #define SPICC_PHA		BIT(5)
52 #define SPICC_SSCTL		BIT(6)
53 #define SPICC_SSPOL		BIT(7)
54 #define SPICC_DRCTL_MASK	GENMASK(9, 8)
55 #define SPICC_DRCTL_IGNORE	0
56 #define SPICC_DRCTL_FALLING	1
57 #define SPICC_DRCTL_LOWLEVEL	2
58 #define SPICC_CS_MASK		GENMASK(13, 12)
59 #define SPICC_DATARATE_MASK	GENMASK(18, 16)
60 #define SPICC_DATARATE_DIV4	0
61 #define SPICC_DATARATE_DIV8	1
62 #define SPICC_DATARATE_DIV16	2
63 #define SPICC_DATARATE_DIV32	3
64 #define SPICC_BITLENGTH_MASK	GENMASK(24, 19)
65 #define SPICC_BURSTLENGTH_MASK	GENMASK(31, 25)
66 
67 #define SPICC_INTREG	0x0c
68 #define SPICC_TE_EN	BIT(0) /* TX FIFO Empty Interrupt */
69 #define SPICC_TH_EN	BIT(1) /* TX FIFO Half-Full Interrupt */
70 #define SPICC_TF_EN	BIT(2) /* TX FIFO Full Interrupt */
71 #define SPICC_RR_EN	BIT(3) /* RX FIFO Ready Interrupt */
72 #define SPICC_RH_EN	BIT(4) /* RX FIFO Half-Full Interrupt */
73 #define SPICC_RF_EN	BIT(5) /* RX FIFO Full Interrupt */
74 #define SPICC_RO_EN	BIT(6) /* RX FIFO Overflow Interrupt */
75 #define SPICC_TC_EN	BIT(7) /* Transfert Complete Interrupt */
76 
77 #define SPICC_DMAREG	0x10
78 #define SPICC_DMA_ENABLE		BIT(0)
79 #define SPICC_TXFIFO_THRESHOLD_MASK	GENMASK(5, 1)
80 #define SPICC_RXFIFO_THRESHOLD_MASK	GENMASK(10, 6)
81 #define SPICC_READ_BURST_MASK		GENMASK(14, 11)
82 #define SPICC_WRITE_BURST_MASK		GENMASK(18, 15)
83 #define SPICC_DMA_URGENT		BIT(19)
84 #define SPICC_DMA_THREADID_MASK		GENMASK(25, 20)
85 #define SPICC_DMA_BURSTNUM_MASK		GENMASK(31, 26)
86 
87 #define SPICC_STATREG	0x14
88 #define SPICC_TE	BIT(0) /* TX FIFO Empty Interrupt */
89 #define SPICC_TH	BIT(1) /* TX FIFO Half-Full Interrupt */
90 #define SPICC_TF	BIT(2) /* TX FIFO Full Interrupt */
91 #define SPICC_RR	BIT(3) /* RX FIFO Ready Interrupt */
92 #define SPICC_RH	BIT(4) /* RX FIFO Half-Full Interrupt */
93 #define SPICC_RF	BIT(5) /* RX FIFO Full Interrupt */
94 #define SPICC_RO	BIT(6) /* RX FIFO Overflow Interrupt */
95 #define SPICC_TC	BIT(7) /* Transfert Complete Interrupt */
96 
97 #define SPICC_PERIODREG	0x18
98 #define SPICC_PERIOD	GENMASK(14, 0)	/* Wait cycles */
99 
100 #define SPICC_TESTREG	0x1c
101 #define SPICC_TXCNT_MASK	GENMASK(4, 0)	/* TX FIFO Counter */
102 #define SPICC_RXCNT_MASK	GENMASK(9, 5)	/* RX FIFO Counter */
103 #define SPICC_SMSTATUS_MASK	GENMASK(12, 10)	/* State Machine Status */
104 #define SPICC_LBC_RO		BIT(13)	/* Loop Back Control Read-Only */
105 #define SPICC_LBC_W1		BIT(14) /* Loop Back Control Write-Only */
106 #define SPICC_SWAP_RO		BIT(14) /* RX FIFO Data Swap Read-Only */
107 #define SPICC_SWAP_W1		BIT(15) /* RX FIFO Data Swap Write-Only */
108 #define SPICC_DLYCTL_RO_MASK	GENMASK(20, 15) /* Delay Control Read-Only */
109 #define SPICC_MO_DELAY_MASK	GENMASK(17, 16) /* Master Output Delay */
110 #define SPICC_MO_NO_DELAY	0
111 #define SPICC_MO_DELAY_1_CYCLE	1
112 #define SPICC_MO_DELAY_2_CYCLE	2
113 #define SPICC_MO_DELAY_3_CYCLE	3
114 #define SPICC_MI_DELAY_MASK	GENMASK(19, 18) /* Master Input Delay */
115 #define SPICC_MI_NO_DELAY	0
116 #define SPICC_MI_DELAY_1_CYCLE	1
117 #define SPICC_MI_DELAY_2_CYCLE	2
118 #define SPICC_MI_DELAY_3_CYCLE	3
119 #define SPICC_MI_CAP_DELAY_MASK	GENMASK(21, 20) /* Master Capture Delay */
120 #define SPICC_CAP_AHEAD_2_CYCLE	0
121 #define SPICC_CAP_AHEAD_1_CYCLE	1
122 #define SPICC_CAP_NO_DELAY	2
123 #define SPICC_CAP_DELAY_1_CYCLE	3
124 #define SPICC_FIFORST_RO_MASK	GENMASK(22, 21) /* FIFO Softreset Read-Only */
125 #define SPICC_FIFORST_W1_MASK	GENMASK(23, 22) /* FIFO Softreset Write-Only */
126 
127 #define SPICC_DRADDR	0x20	/* Read Address of DMA */
128 
129 #define SPICC_DWADDR	0x24	/* Write Address of DMA */
130 
131 #define SPICC_ENH_CTL0	0x38	/* Enhanced Feature */
132 #define SPICC_ENH_CLK_CS_DELAY_MASK	GENMASK(15, 0)
133 #define SPICC_ENH_DATARATE_MASK		GENMASK(23, 16)
134 #define SPICC_ENH_DATARATE_EN		BIT(24)
135 #define SPICC_ENH_MOSI_OEN		BIT(25)
136 #define SPICC_ENH_CLK_OEN		BIT(26)
137 #define SPICC_ENH_CS_OEN		BIT(27)
138 #define SPICC_ENH_CLK_CS_DELAY_EN	BIT(28)
139 #define SPICC_ENH_MAIN_CLK_AO		BIT(29)
140 
141 #define writel_bits_relaxed(mask, val, addr) \
142 	writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
143 
144 struct meson_spicc_data {
145 	unsigned int			max_speed_hz;
146 	unsigned int			min_speed_hz;
147 	unsigned int			fifo_size;
148 	bool				has_oen;
149 	bool				has_enhance_clk_div;
150 	bool				has_pclk;
151 };
152 
153 struct meson_spicc_device {
154 	struct spi_master		*master;
155 	struct platform_device		*pdev;
156 	void __iomem			*base;
157 	struct clk			*core;
158 	struct clk			*pclk;
159 	struct clk_divider		pow2_div;
160 	struct clk			*clk;
161 	struct spi_message		*message;
162 	struct spi_transfer		*xfer;
163 	struct completion		done;
164 	const struct meson_spicc_data	*data;
165 	u8				*tx_buf;
166 	u8				*rx_buf;
167 	unsigned int			bytes_per_word;
168 	unsigned long			tx_remain;
169 	unsigned long			rx_remain;
170 	unsigned long			xfer_remain;
171 };
172 
173 #define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div)
174 
meson_spicc_oen_enable(struct meson_spicc_device * spicc)175 static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
176 {
177 	u32 conf;
178 
179 	if (!spicc->data->has_oen)
180 		return;
181 
182 	conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
183 		SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
184 
185 	writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
186 }
187 
meson_spicc_txfull(struct meson_spicc_device * spicc)188 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
189 {
190 	return !!FIELD_GET(SPICC_TF,
191 			   readl_relaxed(spicc->base + SPICC_STATREG));
192 }
193 
meson_spicc_rxready(struct meson_spicc_device * spicc)194 static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
195 {
196 	return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
197 			 readl_relaxed(spicc->base + SPICC_STATREG));
198 }
199 
meson_spicc_pull_data(struct meson_spicc_device * spicc)200 static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
201 {
202 	unsigned int bytes = spicc->bytes_per_word;
203 	unsigned int byte_shift = 0;
204 	u32 data = 0;
205 	u8 byte;
206 
207 	while (bytes--) {
208 		byte = *spicc->tx_buf++;
209 		data |= (byte & 0xff) << byte_shift;
210 		byte_shift += 8;
211 	}
212 
213 	spicc->tx_remain--;
214 	return data;
215 }
216 
meson_spicc_push_data(struct meson_spicc_device * spicc,u32 data)217 static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
218 					 u32 data)
219 {
220 	unsigned int bytes = spicc->bytes_per_word;
221 	unsigned int byte_shift = 0;
222 	u8 byte;
223 
224 	while (bytes--) {
225 		byte = (data >> byte_shift) & 0xff;
226 		*spicc->rx_buf++ = byte;
227 		byte_shift += 8;
228 	}
229 
230 	spicc->rx_remain--;
231 }
232 
meson_spicc_rx(struct meson_spicc_device * spicc)233 static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
234 {
235 	/* Empty RX FIFO */
236 	while (spicc->rx_remain &&
237 	       meson_spicc_rxready(spicc))
238 		meson_spicc_push_data(spicc,
239 				readl_relaxed(spicc->base + SPICC_RXDATA));
240 }
241 
meson_spicc_tx(struct meson_spicc_device * spicc)242 static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
243 {
244 	/* Fill Up TX FIFO */
245 	while (spicc->tx_remain &&
246 	       !meson_spicc_txfull(spicc))
247 		writel_relaxed(meson_spicc_pull_data(spicc),
248 			       spicc->base + SPICC_TXDATA);
249 }
250 
meson_spicc_setup_burst(struct meson_spicc_device * spicc)251 static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
252 {
253 
254 	unsigned int burst_len = min_t(unsigned int,
255 				       spicc->xfer_remain /
256 				       spicc->bytes_per_word,
257 				       spicc->data->fifo_size);
258 	/* Setup Xfer variables */
259 	spicc->tx_remain = burst_len;
260 	spicc->rx_remain = burst_len;
261 	spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
262 
263 	/* Setup burst length */
264 	writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
265 			FIELD_PREP(SPICC_BURSTLENGTH_MASK,
266 				burst_len - 1),
267 			spicc->base + SPICC_CONREG);
268 
269 	/* Fill TX FIFO */
270 	meson_spicc_tx(spicc);
271 }
272 
meson_spicc_irq(int irq,void * data)273 static irqreturn_t meson_spicc_irq(int irq, void *data)
274 {
275 	struct meson_spicc_device *spicc = (void *) data;
276 
277 	writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
278 
279 	/* Empty RX FIFO */
280 	meson_spicc_rx(spicc);
281 
282 	if (!spicc->xfer_remain) {
283 		/* Disable all IRQs */
284 		writel(0, spicc->base + SPICC_INTREG);
285 
286 		complete(&spicc->done);
287 
288 		return IRQ_HANDLED;
289 	}
290 
291 	/* Setup burst */
292 	meson_spicc_setup_burst(spicc);
293 
294 	/* Start burst */
295 	writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
296 
297 	return IRQ_HANDLED;
298 }
299 
meson_spicc_auto_io_delay(struct meson_spicc_device * spicc)300 static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
301 {
302 	u32 div, hz;
303 	u32 mi_delay, cap_delay;
304 	u32 conf;
305 
306 	if (spicc->data->has_enhance_clk_div) {
307 		div = FIELD_GET(SPICC_ENH_DATARATE_MASK,
308 				readl_relaxed(spicc->base + SPICC_ENH_CTL0));
309 		div++;
310 		div <<= 1;
311 	} else {
312 		div = FIELD_GET(SPICC_DATARATE_MASK,
313 				readl_relaxed(spicc->base + SPICC_CONREG));
314 		div += 2;
315 		div = 1 << div;
316 	}
317 
318 	mi_delay = SPICC_MI_NO_DELAY;
319 	cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
320 	hz = clk_get_rate(spicc->clk);
321 
322 	if (hz >= 100000000)
323 		cap_delay = SPICC_CAP_DELAY_1_CYCLE;
324 	else if (hz >= 80000000)
325 		cap_delay = SPICC_CAP_NO_DELAY;
326 	else if (hz >= 40000000)
327 		cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
328 	else if (div >= 16)
329 		mi_delay = SPICC_MI_DELAY_3_CYCLE;
330 	else if (div >= 8)
331 		mi_delay = SPICC_MI_DELAY_2_CYCLE;
332 	else if (div >= 6)
333 		mi_delay = SPICC_MI_DELAY_1_CYCLE;
334 
335 	conf = readl_relaxed(spicc->base + SPICC_TESTREG);
336 	conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
337 		  | SPICC_MI_CAP_DELAY_MASK);
338 	conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
339 	conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
340 	writel_relaxed(conf, spicc->base + SPICC_TESTREG);
341 }
342 
meson_spicc_setup_xfer(struct meson_spicc_device * spicc,struct spi_transfer * xfer)343 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
344 				   struct spi_transfer *xfer)
345 {
346 	u32 conf, conf_orig;
347 
348 	/* Read original configuration */
349 	conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
350 
351 	/* Setup word width */
352 	conf &= ~SPICC_BITLENGTH_MASK;
353 	conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
354 			   (spicc->bytes_per_word << 3) - 1);
355 
356 	/* Ignore if unchanged */
357 	if (conf != conf_orig)
358 		writel_relaxed(conf, spicc->base + SPICC_CONREG);
359 
360 	clk_set_rate(spicc->clk, xfer->speed_hz);
361 
362 	meson_spicc_auto_io_delay(spicc);
363 
364 	writel_relaxed(0, spicc->base + SPICC_DMAREG);
365 }
366 
meson_spicc_reset_fifo(struct meson_spicc_device * spicc)367 static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
368 {
369 	if (spicc->data->has_oen)
370 		writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
371 				    SPICC_ENH_MAIN_CLK_AO,
372 				    spicc->base + SPICC_ENH_CTL0);
373 
374 	writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
375 			    spicc->base + SPICC_TESTREG);
376 
377 	while (meson_spicc_rxready(spicc))
378 		readl_relaxed(spicc->base + SPICC_RXDATA);
379 
380 	if (spicc->data->has_oen)
381 		writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
382 				    spicc->base + SPICC_ENH_CTL0);
383 }
384 
meson_spicc_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)385 static int meson_spicc_transfer_one(struct spi_master *master,
386 				    struct spi_device *spi,
387 				    struct spi_transfer *xfer)
388 {
389 	struct meson_spicc_device *spicc = spi_master_get_devdata(master);
390 	uint64_t timeout;
391 
392 	/* Store current transfer */
393 	spicc->xfer = xfer;
394 
395 	/* Setup transfer parameters */
396 	spicc->tx_buf = (u8 *)xfer->tx_buf;
397 	spicc->rx_buf = (u8 *)xfer->rx_buf;
398 	spicc->xfer_remain = xfer->len;
399 
400 	/* Pre-calculate word size */
401 	spicc->bytes_per_word =
402 	   DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
403 
404 	if (xfer->len % spicc->bytes_per_word)
405 		return -EINVAL;
406 
407 	/* Setup transfer parameters */
408 	meson_spicc_setup_xfer(spicc, xfer);
409 
410 	meson_spicc_reset_fifo(spicc);
411 
412 	/* Setup burst */
413 	meson_spicc_setup_burst(spicc);
414 
415 	/* Setup wait for completion */
416 	reinit_completion(&spicc->done);
417 
418 	/* For each byte we wait for 8 cycles of the SPI clock */
419 	timeout = 8LL * MSEC_PER_SEC * xfer->len;
420 	do_div(timeout, xfer->speed_hz);
421 
422 	/* Add 10us delay between each fifo bursts */
423 	timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC;
424 
425 	/* Increase it twice and add 200 ms tolerance */
426 	timeout += timeout + 200;
427 
428 	/* Start burst */
429 	writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
430 
431 	/* Enable interrupts */
432 	writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
433 
434 	if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout)))
435 		return -ETIMEDOUT;
436 
437 	return 0;
438 }
439 
meson_spicc_prepare_message(struct spi_master * master,struct spi_message * message)440 static int meson_spicc_prepare_message(struct spi_master *master,
441 				       struct spi_message *message)
442 {
443 	struct meson_spicc_device *spicc = spi_master_get_devdata(master);
444 	struct spi_device *spi = message->spi;
445 	u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
446 
447 	/* Store current message */
448 	spicc->message = message;
449 
450 	/* Enable Master */
451 	conf |= SPICC_ENABLE;
452 	conf |= SPICC_MODE_MASTER;
453 
454 	/* SMC = 0 */
455 
456 	/* Setup transfer mode */
457 	if (spi->mode & SPI_CPOL)
458 		conf |= SPICC_POL;
459 	else
460 		conf &= ~SPICC_POL;
461 
462 	if (spi->mode & SPI_CPHA)
463 		conf |= SPICC_PHA;
464 	else
465 		conf &= ~SPICC_PHA;
466 
467 	/* SSCTL = 0 */
468 
469 	if (spi->mode & SPI_CS_HIGH)
470 		conf |= SPICC_SSPOL;
471 	else
472 		conf &= ~SPICC_SSPOL;
473 
474 	if (spi->mode & SPI_READY)
475 		conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
476 	else
477 		conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
478 
479 	/* Select CS */
480 	conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
481 
482 	/* Default 8bit word */
483 	conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
484 
485 	writel_relaxed(conf, spicc->base + SPICC_CONREG);
486 
487 	/* Setup no wait cycles by default */
488 	writel_relaxed(0, spicc->base + SPICC_PERIODREG);
489 
490 	writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
491 
492 	return 0;
493 }
494 
meson_spicc_unprepare_transfer(struct spi_master * master)495 static int meson_spicc_unprepare_transfer(struct spi_master *master)
496 {
497 	struct meson_spicc_device *spicc = spi_master_get_devdata(master);
498 	u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
499 
500 	/* Disable all IRQs */
501 	writel(0, spicc->base + SPICC_INTREG);
502 
503 	device_reset_optional(&spicc->pdev->dev);
504 
505 	/* Set default configuration, keeping datarate field */
506 	writel_relaxed(conf, spicc->base + SPICC_CONREG);
507 
508 	return 0;
509 }
510 
meson_spicc_setup(struct spi_device * spi)511 static int meson_spicc_setup(struct spi_device *spi)
512 {
513 	if (!spi->controller_state)
514 		spi->controller_state = spi_master_get_devdata(spi->master);
515 
516 	return 0;
517 }
518 
meson_spicc_cleanup(struct spi_device * spi)519 static void meson_spicc_cleanup(struct spi_device *spi)
520 {
521 	spi->controller_state = NULL;
522 }
523 
524 /*
525  * The Clock Mux
526  *            x-----------------x   x------------x    x------\
527  *        |---| pow2 fixed div  |---| pow2 div   |----|      |
528  *        |   x-----------------x   x------------x    |      |
529  * src ---|                                           | mux  |-- out
530  *        |   x-----------------x   x------------x    |      |
531  *        |---| enh fixed div   |---| enh div    |0---|      |
532  *            x-----------------x   x------------x    x------/
533  *
534  * Clk path for GX series:
535  *    src -> pow2 fixed div -> pow2 div -> out
536  *
537  * Clk path for AXG series:
538  *    src -> pow2 fixed div -> pow2 div -> mux -> out
539  *    src -> enh fixed div -> enh div -> mux -> out
540  *
541  * Clk path for G12A series:
542  *    pclk -> pow2 fixed div -> pow2 div -> mux -> out
543  *    pclk -> enh fixed div -> enh div -> mux -> out
544  *
545  * The pow2 divider is tied to the controller HW state, and the
546  * divider is only valid when the controller is initialized.
547  *
548  * A set of clock ops is added to make sure we don't read/set this
549  * clock rate while the controller is in an unknown state.
550  */
551 
meson_spicc_pow2_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)552 static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw,
553 						  unsigned long parent_rate)
554 {
555 	struct clk_divider *divider = to_clk_divider(hw);
556 	struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
557 
558 	if (!spicc->master->cur_msg)
559 		return 0;
560 
561 	return clk_divider_ops.recalc_rate(hw, parent_rate);
562 }
563 
meson_spicc_pow2_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)564 static int meson_spicc_pow2_determine_rate(struct clk_hw *hw,
565 					   struct clk_rate_request *req)
566 {
567 	struct clk_divider *divider = to_clk_divider(hw);
568 	struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
569 
570 	if (!spicc->master->cur_msg)
571 		return -EINVAL;
572 
573 	return clk_divider_ops.determine_rate(hw, req);
574 }
575 
meson_spicc_pow2_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)576 static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate,
577 				     unsigned long parent_rate)
578 {
579 	struct clk_divider *divider = to_clk_divider(hw);
580 	struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
581 
582 	if (!spicc->master->cur_msg)
583 		return -EINVAL;
584 
585 	return clk_divider_ops.set_rate(hw, rate, parent_rate);
586 }
587 
588 static const struct clk_ops meson_spicc_pow2_clk_ops = {
589 	.recalc_rate = meson_spicc_pow2_recalc_rate,
590 	.determine_rate = meson_spicc_pow2_determine_rate,
591 	.set_rate = meson_spicc_pow2_set_rate,
592 };
593 
meson_spicc_pow2_clk_init(struct meson_spicc_device * spicc)594 static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)
595 {
596 	struct device *dev = &spicc->pdev->dev;
597 	struct clk_fixed_factor *pow2_fixed_div;
598 	struct clk_init_data init;
599 	struct clk *clk;
600 	struct clk_parent_data parent_data[2];
601 	char name[64];
602 
603 	memset(&init, 0, sizeof(init));
604 	memset(&parent_data, 0, sizeof(parent_data));
605 
606 	init.parent_data = parent_data;
607 
608 	/* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
609 
610 	pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
611 	if (!pow2_fixed_div)
612 		return -ENOMEM;
613 
614 	snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
615 	init.name = name;
616 	init.ops = &clk_fixed_factor_ops;
617 	init.flags = 0;
618 	if (spicc->data->has_pclk)
619 		parent_data[0].hw = __clk_get_hw(spicc->pclk);
620 	else
621 		parent_data[0].hw = __clk_get_hw(spicc->core);
622 	init.num_parents = 1;
623 
624 	pow2_fixed_div->mult = 1,
625 	pow2_fixed_div->div = 4,
626 	pow2_fixed_div->hw.init = &init;
627 
628 	clk = devm_clk_register(dev, &pow2_fixed_div->hw);
629 	if (WARN_ON(IS_ERR(clk)))
630 		return PTR_ERR(clk);
631 
632 	snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
633 	init.name = name;
634 	init.ops = &meson_spicc_pow2_clk_ops;
635 	/*
636 	 * Set NOCACHE here to make sure we read the actual HW value
637 	 * since we reset the HW after each transfer.
638 	 */
639 	init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
640 	parent_data[0].hw = &pow2_fixed_div->hw;
641 	init.num_parents = 1;
642 
643 	spicc->pow2_div.shift = 16,
644 	spicc->pow2_div.width = 3,
645 	spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO,
646 	spicc->pow2_div.reg = spicc->base + SPICC_CONREG;
647 	spicc->pow2_div.hw.init = &init;
648 
649 	spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw);
650 	if (WARN_ON(IS_ERR(spicc->clk)))
651 		return PTR_ERR(spicc->clk);
652 
653 	return 0;
654 }
655 
meson_spicc_enh_clk_init(struct meson_spicc_device * spicc)656 static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)
657 {
658 	struct device *dev = &spicc->pdev->dev;
659 	struct clk_fixed_factor *enh_fixed_div;
660 	struct clk_divider *enh_div;
661 	struct clk_mux *mux;
662 	struct clk_init_data init;
663 	struct clk *clk;
664 	struct clk_parent_data parent_data[2];
665 	char name[64];
666 
667 	memset(&init, 0, sizeof(init));
668 	memset(&parent_data, 0, sizeof(parent_data));
669 
670 	init.parent_data = parent_data;
671 
672 	/* algorithm for enh div: rate = freq / 2 / (N + 1) */
673 
674 	enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
675 	if (!enh_fixed_div)
676 		return -ENOMEM;
677 
678 	snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
679 	init.name = name;
680 	init.ops = &clk_fixed_factor_ops;
681 	init.flags = 0;
682 	if (spicc->data->has_pclk)
683 		parent_data[0].hw = __clk_get_hw(spicc->pclk);
684 	else
685 		parent_data[0].hw = __clk_get_hw(spicc->core);
686 	init.num_parents = 1;
687 
688 	enh_fixed_div->mult = 1,
689 	enh_fixed_div->div = 2,
690 	enh_fixed_div->hw.init = &init;
691 
692 	clk = devm_clk_register(dev, &enh_fixed_div->hw);
693 	if (WARN_ON(IS_ERR(clk)))
694 		return PTR_ERR(clk);
695 
696 	enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
697 	if (!enh_div)
698 		return -ENOMEM;
699 
700 	snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
701 	init.name = name;
702 	init.ops = &clk_divider_ops;
703 	init.flags = CLK_SET_RATE_PARENT;
704 	parent_data[0].hw = &enh_fixed_div->hw;
705 	init.num_parents = 1;
706 
707 	enh_div->shift	= 16,
708 	enh_div->width	= 8,
709 	enh_div->reg = spicc->base + SPICC_ENH_CTL0;
710 	enh_div->hw.init = &init;
711 
712 	clk = devm_clk_register(dev, &enh_div->hw);
713 	if (WARN_ON(IS_ERR(clk)))
714 		return PTR_ERR(clk);
715 
716 	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
717 	if (!mux)
718 		return -ENOMEM;
719 
720 	snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
721 	init.name = name;
722 	init.ops = &clk_mux_ops;
723 	parent_data[0].hw = &spicc->pow2_div.hw;
724 	parent_data[1].hw = &enh_div->hw;
725 	init.num_parents = 2;
726 	init.flags = CLK_SET_RATE_PARENT;
727 
728 	mux->mask = 0x1,
729 	mux->shift = 24,
730 	mux->reg = spicc->base + SPICC_ENH_CTL0;
731 	mux->hw.init = &init;
732 
733 	spicc->clk = devm_clk_register(dev, &mux->hw);
734 	if (WARN_ON(IS_ERR(spicc->clk)))
735 		return PTR_ERR(spicc->clk);
736 
737 	return 0;
738 }
739 
meson_spicc_probe(struct platform_device * pdev)740 static int meson_spicc_probe(struct platform_device *pdev)
741 {
742 	struct spi_master *master;
743 	struct meson_spicc_device *spicc;
744 	int ret, irq;
745 
746 	master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
747 	if (!master) {
748 		dev_err(&pdev->dev, "master allocation failed\n");
749 		return -ENOMEM;
750 	}
751 	spicc = spi_master_get_devdata(master);
752 	spicc->master = master;
753 
754 	spicc->data = of_device_get_match_data(&pdev->dev);
755 	if (!spicc->data) {
756 		dev_err(&pdev->dev, "failed to get match data\n");
757 		ret = -EINVAL;
758 		goto out_master;
759 	}
760 
761 	spicc->pdev = pdev;
762 	platform_set_drvdata(pdev, spicc);
763 
764 	init_completion(&spicc->done);
765 
766 	spicc->base = devm_platform_ioremap_resource(pdev, 0);
767 	if (IS_ERR(spicc->base)) {
768 		dev_err(&pdev->dev, "io resource mapping failed\n");
769 		ret = PTR_ERR(spicc->base);
770 		goto out_master;
771 	}
772 
773 	/* Set master mode and enable controller */
774 	writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
775 		       spicc->base + SPICC_CONREG);
776 
777 	/* Disable all IRQs */
778 	writel_relaxed(0, spicc->base + SPICC_INTREG);
779 
780 	irq = platform_get_irq(pdev, 0);
781 	if (irq < 0) {
782 		ret = irq;
783 		goto out_master;
784 	}
785 
786 	ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
787 			       0, NULL, spicc);
788 	if (ret) {
789 		dev_err(&pdev->dev, "irq request failed\n");
790 		goto out_master;
791 	}
792 
793 	spicc->core = devm_clk_get(&pdev->dev, "core");
794 	if (IS_ERR(spicc->core)) {
795 		dev_err(&pdev->dev, "core clock request failed\n");
796 		ret = PTR_ERR(spicc->core);
797 		goto out_master;
798 	}
799 
800 	if (spicc->data->has_pclk) {
801 		spicc->pclk = devm_clk_get(&pdev->dev, "pclk");
802 		if (IS_ERR(spicc->pclk)) {
803 			dev_err(&pdev->dev, "pclk clock request failed\n");
804 			ret = PTR_ERR(spicc->pclk);
805 			goto out_master;
806 		}
807 	}
808 
809 	ret = clk_prepare_enable(spicc->core);
810 	if (ret) {
811 		dev_err(&pdev->dev, "core clock enable failed\n");
812 		goto out_master;
813 	}
814 
815 	ret = clk_prepare_enable(spicc->pclk);
816 	if (ret) {
817 		dev_err(&pdev->dev, "pclk clock enable failed\n");
818 		goto out_core_clk;
819 	}
820 
821 	device_reset_optional(&pdev->dev);
822 
823 	master->num_chipselect = 4;
824 	master->dev.of_node = pdev->dev.of_node;
825 	master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
826 	master->bits_per_word_mask = SPI_BPW_MASK(32) |
827 				     SPI_BPW_MASK(24) |
828 				     SPI_BPW_MASK(16) |
829 				     SPI_BPW_MASK(8);
830 	master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
831 	master->min_speed_hz = spicc->data->min_speed_hz;
832 	master->max_speed_hz = spicc->data->max_speed_hz;
833 	master->setup = meson_spicc_setup;
834 	master->cleanup = meson_spicc_cleanup;
835 	master->prepare_message = meson_spicc_prepare_message;
836 	master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
837 	master->transfer_one = meson_spicc_transfer_one;
838 	master->use_gpio_descriptors = true;
839 
840 	meson_spicc_oen_enable(spicc);
841 
842 	ret = meson_spicc_pow2_clk_init(spicc);
843 	if (ret) {
844 		dev_err(&pdev->dev, "pow2 clock registration failed\n");
845 		goto out_clk;
846 	}
847 
848 	if (spicc->data->has_enhance_clk_div) {
849 		ret = meson_spicc_enh_clk_init(spicc);
850 		if (ret) {
851 			dev_err(&pdev->dev, "clock registration failed\n");
852 			goto out_clk;
853 		}
854 	}
855 
856 	ret = devm_spi_register_master(&pdev->dev, master);
857 	if (ret) {
858 		dev_err(&pdev->dev, "spi master registration failed\n");
859 		goto out_clk;
860 	}
861 
862 	return 0;
863 
864 out_clk:
865 	clk_disable_unprepare(spicc->pclk);
866 
867 out_core_clk:
868 	clk_disable_unprepare(spicc->core);
869 
870 out_master:
871 	spi_master_put(master);
872 
873 	return ret;
874 }
875 
meson_spicc_remove(struct platform_device * pdev)876 static int meson_spicc_remove(struct platform_device *pdev)
877 {
878 	struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
879 
880 	/* Disable SPI */
881 	writel(0, spicc->base + SPICC_CONREG);
882 
883 	clk_disable_unprepare(spicc->core);
884 	clk_disable_unprepare(spicc->pclk);
885 
886 	spi_master_put(spicc->master);
887 
888 	return 0;
889 }
890 
891 static const struct meson_spicc_data meson_spicc_gx_data = {
892 	.max_speed_hz		= 30000000,
893 	.min_speed_hz		= 325000,
894 	.fifo_size		= 16,
895 };
896 
897 static const struct meson_spicc_data meson_spicc_axg_data = {
898 	.max_speed_hz		= 80000000,
899 	.min_speed_hz		= 325000,
900 	.fifo_size		= 16,
901 	.has_oen		= true,
902 	.has_enhance_clk_div	= true,
903 };
904 
905 static const struct meson_spicc_data meson_spicc_g12a_data = {
906 	.max_speed_hz		= 166666666,
907 	.min_speed_hz		= 50000,
908 	.fifo_size		= 15,
909 	.has_oen		= true,
910 	.has_enhance_clk_div	= true,
911 	.has_pclk		= true,
912 };
913 
914 static const struct of_device_id meson_spicc_of_match[] = {
915 	{
916 		.compatible	= "amlogic,meson-gx-spicc",
917 		.data		= &meson_spicc_gx_data,
918 	},
919 	{
920 		.compatible = "amlogic,meson-axg-spicc",
921 		.data		= &meson_spicc_axg_data,
922 	},
923 	{
924 		.compatible = "amlogic,meson-g12a-spicc",
925 		.data		= &meson_spicc_g12a_data,
926 	},
927 	{ /* sentinel */ }
928 };
929 MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
930 
931 static struct platform_driver meson_spicc_driver = {
932 	.probe   = meson_spicc_probe,
933 	.remove  = meson_spicc_remove,
934 	.driver  = {
935 		.name = "meson-spicc",
936 		.of_match_table = of_match_ptr(meson_spicc_of_match),
937 	},
938 };
939 
940 module_platform_driver(meson_spicc_driver);
941 
942 MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
943 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
944 MODULE_LICENSE("GPL");
945