1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip Generic power domain support.
4 *
5 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 */
7
8 #include <linux/io.h>
9 #include <linux/iopoll.h>
10 #include <linux/err.h>
11 #include <linux/mutex.h>
12 #include <linux/pm_clock.h>
13 #include <linux/pm_domain.h>
14 #include <linux/of_address.h>
15 #include <linux/of_clk.h>
16 #include <linux/of_platform.h>
17 #include <linux/clk.h>
18 #include <linux/regmap.h>
19 #include <linux/mfd/syscon.h>
20 #include <soc/rockchip/pm_domains.h>
21 #include <dt-bindings/power/px30-power.h>
22 #include <dt-bindings/power/rockchip,rv1126-power.h>
23 #include <dt-bindings/power/rk3036-power.h>
24 #include <dt-bindings/power/rk3066-power.h>
25 #include <dt-bindings/power/rk3128-power.h>
26 #include <dt-bindings/power/rk3188-power.h>
27 #include <dt-bindings/power/rk3228-power.h>
28 #include <dt-bindings/power/rk3288-power.h>
29 #include <dt-bindings/power/rk3328-power.h>
30 #include <dt-bindings/power/rk3366-power.h>
31 #include <dt-bindings/power/rk3368-power.h>
32 #include <dt-bindings/power/rk3399-power.h>
33 #include <dt-bindings/power/rk3568-power.h>
34 #include <dt-bindings/power/rk3588-power.h>
35
36 struct rockchip_domain_info {
37 const char *name;
38 int pwr_mask;
39 int status_mask;
40 int req_mask;
41 int idle_mask;
42 int ack_mask;
43 bool active_wakeup;
44 int pwr_w_mask;
45 int req_w_mask;
46 int repair_status_mask;
47 u32 pwr_offset;
48 u32 req_offset;
49 };
50
51 struct rockchip_pmu_info {
52 u32 pwr_offset;
53 u32 status_offset;
54 u32 req_offset;
55 u32 idle_offset;
56 u32 ack_offset;
57 u32 repair_status_offset;
58
59 u32 core_pwrcnt_offset;
60 u32 gpu_pwrcnt_offset;
61
62 unsigned int core_power_transition_time;
63 unsigned int gpu_power_transition_time;
64
65 int num_domains;
66 const struct rockchip_domain_info *domain_info;
67 };
68
69 #define MAX_QOS_REGS_NUM 5
70 #define QOS_PRIORITY 0x08
71 #define QOS_MODE 0x0c
72 #define QOS_BANDWIDTH 0x10
73 #define QOS_SATURATION 0x14
74 #define QOS_EXTCONTROL 0x18
75
76 struct rockchip_pm_domain {
77 struct generic_pm_domain genpd;
78 const struct rockchip_domain_info *info;
79 struct rockchip_pmu *pmu;
80 int num_qos;
81 struct regmap **qos_regmap;
82 u32 *qos_save_regs[MAX_QOS_REGS_NUM];
83 int num_clks;
84 struct clk_bulk_data *clks;
85 };
86
87 struct rockchip_pmu {
88 struct device *dev;
89 struct regmap *regmap;
90 const struct rockchip_pmu_info *info;
91 struct mutex mutex; /* mutex lock for pmu */
92 struct genpd_onecell_data genpd_data;
93 struct generic_pm_domain *domains[];
94 };
95
96 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
97
98 #define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
99 { \
100 .name = _name, \
101 .pwr_mask = (pwr), \
102 .status_mask = (status), \
103 .req_mask = (req), \
104 .idle_mask = (idle), \
105 .ack_mask = (ack), \
106 .active_wakeup = (wakeup), \
107 }
108
109 #define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
110 { \
111 .name = _name, \
112 .pwr_w_mask = (pwr) << 16, \
113 .pwr_mask = (pwr), \
114 .status_mask = (status), \
115 .req_w_mask = (req) << 16, \
116 .req_mask = (req), \
117 .idle_mask = (idle), \
118 .ack_mask = (ack), \
119 .active_wakeup = wakeup, \
120 }
121
122 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \
123 { \
124 .name = _name, \
125 .pwr_offset = p_offset, \
126 .pwr_w_mask = (pwr) << 16, \
127 .pwr_mask = (pwr), \
128 .status_mask = (status), \
129 .repair_status_mask = (r_status), \
130 .req_offset = r_offset, \
131 .req_w_mask = (req) << 16, \
132 .req_mask = (req), \
133 .idle_mask = (idle), \
134 .ack_mask = (ack), \
135 .active_wakeup = wakeup, \
136 }
137
138 #define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
139 { \
140 .name = _name, \
141 .req_mask = (req), \
142 .req_w_mask = (req) << 16, \
143 .ack_mask = (ack), \
144 .idle_mask = (idle), \
145 .active_wakeup = wakeup, \
146 }
147
148 #define DOMAIN_PX30(name, pwr, status, req, wakeup) \
149 DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
150
151 #define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
152 DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
153
154 #define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
155 DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
156
157 #define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
158 DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
159
160 #define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
161 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
162
163 #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
164 DOMAIN(name, pwr, status, req, req, req, wakeup)
165
166 #define DOMAIN_RK3568(name, pwr, req, wakeup) \
167 DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
168
169 /*
170 * Dynamic Memory Controller may need to coordinate with us -- see
171 * rockchip_pmu_block().
172 *
173 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
174 * block() while we're initializing the PMU.
175 */
176 static DEFINE_MUTEX(dmc_pmu_mutex);
177 static struct rockchip_pmu *dmc_pmu;
178
179 /*
180 * Block PMU transitions and make sure they don't interfere with ARM Trusted
181 * Firmware operations. There are two conflicts, noted in the comments below.
182 *
183 * Caller must unblock PMU transitions via rockchip_pmu_unblock().
184 */
rockchip_pmu_block(void)185 int rockchip_pmu_block(void)
186 {
187 struct rockchip_pmu *pmu;
188 struct generic_pm_domain *genpd;
189 struct rockchip_pm_domain *pd;
190 int i, ret;
191
192 mutex_lock(&dmc_pmu_mutex);
193
194 /* No PMU (yet)? Then we just block rockchip_pmu_probe(). */
195 if (!dmc_pmu)
196 return 0;
197 pmu = dmc_pmu;
198
199 /*
200 * mutex blocks all idle transitions: we can't touch the
201 * PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted
202 * Firmware might be using it.
203 */
204 mutex_lock(&pmu->mutex);
205
206 /*
207 * Power domain clocks: Per Rockchip, we *must* keep certain clocks
208 * enabled for the duration of power-domain transitions. Most
209 * transitions are handled by this driver, but some cases (in
210 * particular, DRAM DVFS / memory-controller idle) must be handled by
211 * firmware. Firmware can handle most clock management via a special
212 * "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this
213 * doesn't handle PLLs. We can assist this transition by doing the
214 * clock management on behalf of firmware.
215 */
216 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
217 genpd = pmu->genpd_data.domains[i];
218 if (genpd) {
219 pd = to_rockchip_pd(genpd);
220 ret = clk_bulk_enable(pd->num_clks, pd->clks);
221 if (ret < 0) {
222 dev_err(pmu->dev,
223 "failed to enable clks for domain '%s': %d\n",
224 genpd->name, ret);
225 goto err;
226 }
227 }
228 }
229
230 return 0;
231
232 err:
233 for (i = i - 1; i >= 0; i--) {
234 genpd = pmu->genpd_data.domains[i];
235 if (genpd) {
236 pd = to_rockchip_pd(genpd);
237 clk_bulk_disable(pd->num_clks, pd->clks);
238 }
239 }
240 mutex_unlock(&pmu->mutex);
241 mutex_unlock(&dmc_pmu_mutex);
242
243 return ret;
244 }
245 EXPORT_SYMBOL_GPL(rockchip_pmu_block);
246
247 /* Unblock PMU transitions. */
rockchip_pmu_unblock(void)248 void rockchip_pmu_unblock(void)
249 {
250 struct rockchip_pmu *pmu;
251 struct generic_pm_domain *genpd;
252 struct rockchip_pm_domain *pd;
253 int i;
254
255 if (dmc_pmu) {
256 pmu = dmc_pmu;
257 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
258 genpd = pmu->genpd_data.domains[i];
259 if (genpd) {
260 pd = to_rockchip_pd(genpd);
261 clk_bulk_disable(pd->num_clks, pd->clks);
262 }
263 }
264
265 mutex_unlock(&pmu->mutex);
266 }
267
268 mutex_unlock(&dmc_pmu_mutex);
269 }
270 EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
271
272 #define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \
273 DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup)
274
rockchip_pmu_domain_is_idle(struct rockchip_pm_domain * pd)275 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
276 {
277 struct rockchip_pmu *pmu = pd->pmu;
278 const struct rockchip_domain_info *pd_info = pd->info;
279 unsigned int val;
280
281 regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
282 return (val & pd_info->idle_mask) == pd_info->idle_mask;
283 }
284
rockchip_pmu_read_ack(struct rockchip_pmu * pmu)285 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
286 {
287 unsigned int val;
288
289 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
290 return val;
291 }
292
rockchip_pmu_set_idle_request(struct rockchip_pm_domain * pd,bool idle)293 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
294 bool idle)
295 {
296 const struct rockchip_domain_info *pd_info = pd->info;
297 struct generic_pm_domain *genpd = &pd->genpd;
298 struct rockchip_pmu *pmu = pd->pmu;
299 u32 pd_req_offset = pd_info->req_offset;
300 unsigned int target_ack;
301 unsigned int val;
302 bool is_idle;
303 int ret;
304
305 if (pd_info->req_mask == 0)
306 return 0;
307 else if (pd_info->req_w_mask)
308 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset,
309 idle ? (pd_info->req_mask | pd_info->req_w_mask) :
310 pd_info->req_w_mask);
311 else
312 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset,
313 pd_info->req_mask, idle ? -1U : 0);
314
315 wmb();
316
317 /* Wait util idle_ack = 1 */
318 target_ack = idle ? pd_info->ack_mask : 0;
319 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
320 (val & pd_info->ack_mask) == target_ack,
321 0, 10000);
322 if (ret) {
323 dev_err(pmu->dev,
324 "failed to get ack on domain '%s', val=0x%x\n",
325 genpd->name, val);
326 return ret;
327 }
328
329 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
330 is_idle, is_idle == idle, 0, 10000);
331 if (ret) {
332 dev_err(pmu->dev,
333 "failed to set idle on domain '%s', val=%d\n",
334 genpd->name, is_idle);
335 return ret;
336 }
337
338 return 0;
339 }
340
rockchip_pmu_save_qos(struct rockchip_pm_domain * pd)341 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
342 {
343 int i;
344
345 for (i = 0; i < pd->num_qos; i++) {
346 regmap_read(pd->qos_regmap[i],
347 QOS_PRIORITY,
348 &pd->qos_save_regs[0][i]);
349 regmap_read(pd->qos_regmap[i],
350 QOS_MODE,
351 &pd->qos_save_regs[1][i]);
352 regmap_read(pd->qos_regmap[i],
353 QOS_BANDWIDTH,
354 &pd->qos_save_regs[2][i]);
355 regmap_read(pd->qos_regmap[i],
356 QOS_SATURATION,
357 &pd->qos_save_regs[3][i]);
358 regmap_read(pd->qos_regmap[i],
359 QOS_EXTCONTROL,
360 &pd->qos_save_regs[4][i]);
361 }
362 return 0;
363 }
364
rockchip_pmu_restore_qos(struct rockchip_pm_domain * pd)365 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
366 {
367 int i;
368
369 for (i = 0; i < pd->num_qos; i++) {
370 regmap_write(pd->qos_regmap[i],
371 QOS_PRIORITY,
372 pd->qos_save_regs[0][i]);
373 regmap_write(pd->qos_regmap[i],
374 QOS_MODE,
375 pd->qos_save_regs[1][i]);
376 regmap_write(pd->qos_regmap[i],
377 QOS_BANDWIDTH,
378 pd->qos_save_regs[2][i]);
379 regmap_write(pd->qos_regmap[i],
380 QOS_SATURATION,
381 pd->qos_save_regs[3][i]);
382 regmap_write(pd->qos_regmap[i],
383 QOS_EXTCONTROL,
384 pd->qos_save_regs[4][i]);
385 }
386
387 return 0;
388 }
389
rockchip_pmu_domain_is_on(struct rockchip_pm_domain * pd)390 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
391 {
392 struct rockchip_pmu *pmu = pd->pmu;
393 unsigned int val;
394
395 if (pd->info->repair_status_mask) {
396 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
397 /* 1'b1: power on, 1'b0: power off */
398 return val & pd->info->repair_status_mask;
399 }
400
401 /* check idle status for idle-only domains */
402 if (pd->info->status_mask == 0)
403 return !rockchip_pmu_domain_is_idle(pd);
404
405 regmap_read(pmu->regmap, pmu->info->status_offset, &val);
406
407 /* 1'b0: power on, 1'b1: power off */
408 return !(val & pd->info->status_mask);
409 }
410
rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain * pd,bool on)411 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
412 bool on)
413 {
414 struct rockchip_pmu *pmu = pd->pmu;
415 struct generic_pm_domain *genpd = &pd->genpd;
416 u32 pd_pwr_offset = pd->info->pwr_offset;
417 bool is_on;
418
419 if (pd->info->pwr_mask == 0)
420 return;
421 else if (pd->info->pwr_w_mask)
422 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
423 on ? pd->info->pwr_w_mask :
424 (pd->info->pwr_mask | pd->info->pwr_w_mask));
425 else
426 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
427 pd->info->pwr_mask, on ? 0 : -1U);
428
429 wmb();
430
431 if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
432 is_on == on, 0, 10000)) {
433 dev_err(pmu->dev,
434 "failed to set domain '%s', val=%d\n",
435 genpd->name, is_on);
436 return;
437 }
438 }
439
rockchip_pd_power(struct rockchip_pm_domain * pd,bool power_on)440 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
441 {
442 struct rockchip_pmu *pmu = pd->pmu;
443 int ret;
444
445 mutex_lock(&pmu->mutex);
446
447 if (rockchip_pmu_domain_is_on(pd) != power_on) {
448 ret = clk_bulk_enable(pd->num_clks, pd->clks);
449 if (ret < 0) {
450 dev_err(pmu->dev, "failed to enable clocks\n");
451 mutex_unlock(&pmu->mutex);
452 return ret;
453 }
454
455 if (!power_on) {
456 rockchip_pmu_save_qos(pd);
457
458 /* if powering down, idle request to NIU first */
459 rockchip_pmu_set_idle_request(pd, true);
460 }
461
462 rockchip_do_pmu_set_power_domain(pd, power_on);
463
464 if (power_on) {
465 /* if powering up, leave idle mode */
466 rockchip_pmu_set_idle_request(pd, false);
467
468 rockchip_pmu_restore_qos(pd);
469 }
470
471 clk_bulk_disable(pd->num_clks, pd->clks);
472 }
473
474 mutex_unlock(&pmu->mutex);
475 return 0;
476 }
477
rockchip_pd_power_on(struct generic_pm_domain * domain)478 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
479 {
480 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
481
482 return rockchip_pd_power(pd, true);
483 }
484
rockchip_pd_power_off(struct generic_pm_domain * domain)485 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
486 {
487 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
488
489 return rockchip_pd_power(pd, false);
490 }
491
rockchip_pd_attach_dev(struct generic_pm_domain * genpd,struct device * dev)492 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
493 struct device *dev)
494 {
495 struct clk *clk;
496 int i;
497 int error;
498
499 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
500
501 error = pm_clk_create(dev);
502 if (error) {
503 dev_err(dev, "pm_clk_create failed %d\n", error);
504 return error;
505 }
506
507 i = 0;
508 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
509 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
510 error = pm_clk_add_clk(dev, clk);
511 if (error) {
512 dev_err(dev, "pm_clk_add_clk failed %d\n", error);
513 clk_put(clk);
514 pm_clk_destroy(dev);
515 return error;
516 }
517 }
518
519 return 0;
520 }
521
rockchip_pd_detach_dev(struct generic_pm_domain * genpd,struct device * dev)522 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
523 struct device *dev)
524 {
525 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
526
527 pm_clk_destroy(dev);
528 }
529
rockchip_pm_add_one_domain(struct rockchip_pmu * pmu,struct device_node * node)530 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
531 struct device_node *node)
532 {
533 const struct rockchip_domain_info *pd_info;
534 struct rockchip_pm_domain *pd;
535 struct device_node *qos_node;
536 int i, j;
537 u32 id;
538 int error;
539
540 error = of_property_read_u32(node, "reg", &id);
541 if (error) {
542 dev_err(pmu->dev,
543 "%pOFn: failed to retrieve domain id (reg): %d\n",
544 node, error);
545 return -EINVAL;
546 }
547
548 if (id >= pmu->info->num_domains) {
549 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
550 node, id);
551 return -EINVAL;
552 }
553 /* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */
554 if (pmu->genpd_data.domains[id])
555 return 0;
556
557 pd_info = &pmu->info->domain_info[id];
558 if (!pd_info) {
559 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
560 node, id);
561 return -EINVAL;
562 }
563
564 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
565 if (!pd)
566 return -ENOMEM;
567
568 pd->info = pd_info;
569 pd->pmu = pmu;
570
571 pd->num_clks = of_clk_get_parent_count(node);
572 if (pd->num_clks > 0) {
573 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
574 sizeof(*pd->clks), GFP_KERNEL);
575 if (!pd->clks)
576 return -ENOMEM;
577 } else {
578 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
579 node, pd->num_clks);
580 pd->num_clks = 0;
581 }
582
583 for (i = 0; i < pd->num_clks; i++) {
584 pd->clks[i].clk = of_clk_get(node, i);
585 if (IS_ERR(pd->clks[i].clk)) {
586 error = PTR_ERR(pd->clks[i].clk);
587 dev_err(pmu->dev,
588 "%pOFn: failed to get clk at index %d: %d\n",
589 node, i, error);
590 return error;
591 }
592 }
593
594 error = clk_bulk_prepare(pd->num_clks, pd->clks);
595 if (error)
596 goto err_put_clocks;
597
598 pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
599 NULL);
600
601 if (pd->num_qos > 0) {
602 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
603 sizeof(*pd->qos_regmap),
604 GFP_KERNEL);
605 if (!pd->qos_regmap) {
606 error = -ENOMEM;
607 goto err_unprepare_clocks;
608 }
609
610 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
611 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
612 pd->num_qos,
613 sizeof(u32),
614 GFP_KERNEL);
615 if (!pd->qos_save_regs[j]) {
616 error = -ENOMEM;
617 goto err_unprepare_clocks;
618 }
619 }
620
621 for (j = 0; j < pd->num_qos; j++) {
622 qos_node = of_parse_phandle(node, "pm_qos", j);
623 if (!qos_node) {
624 error = -ENODEV;
625 goto err_unprepare_clocks;
626 }
627 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
628 if (IS_ERR(pd->qos_regmap[j])) {
629 error = -ENODEV;
630 of_node_put(qos_node);
631 goto err_unprepare_clocks;
632 }
633 of_node_put(qos_node);
634 }
635 }
636
637 if (pd->info->name)
638 pd->genpd.name = pd->info->name;
639 else
640 pd->genpd.name = kbasename(node->full_name);
641 pd->genpd.power_off = rockchip_pd_power_off;
642 pd->genpd.power_on = rockchip_pd_power_on;
643 pd->genpd.attach_dev = rockchip_pd_attach_dev;
644 pd->genpd.detach_dev = rockchip_pd_detach_dev;
645 pd->genpd.flags = GENPD_FLAG_PM_CLK;
646 if (pd_info->active_wakeup)
647 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
648 pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
649
650 pmu->genpd_data.domains[id] = &pd->genpd;
651 return 0;
652
653 err_unprepare_clocks:
654 clk_bulk_unprepare(pd->num_clks, pd->clks);
655 err_put_clocks:
656 clk_bulk_put(pd->num_clks, pd->clks);
657 return error;
658 }
659
rockchip_pm_remove_one_domain(struct rockchip_pm_domain * pd)660 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
661 {
662 int ret;
663
664 /*
665 * We're in the error cleanup already, so we only complain,
666 * but won't emit another error on top of the original one.
667 */
668 ret = pm_genpd_remove(&pd->genpd);
669 if (ret < 0)
670 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
671 pd->genpd.name, ret);
672
673 clk_bulk_unprepare(pd->num_clks, pd->clks);
674 clk_bulk_put(pd->num_clks, pd->clks);
675
676 /* protect the zeroing of pm->num_clks */
677 mutex_lock(&pd->pmu->mutex);
678 pd->num_clks = 0;
679 mutex_unlock(&pd->pmu->mutex);
680
681 /* devm will free our memory */
682 }
683
rockchip_pm_domain_cleanup(struct rockchip_pmu * pmu)684 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
685 {
686 struct generic_pm_domain *genpd;
687 struct rockchip_pm_domain *pd;
688 int i;
689
690 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
691 genpd = pmu->genpd_data.domains[i];
692 if (genpd) {
693 pd = to_rockchip_pd(genpd);
694 rockchip_pm_remove_one_domain(pd);
695 }
696 }
697
698 /* devm will free our memory */
699 }
700
rockchip_configure_pd_cnt(struct rockchip_pmu * pmu,u32 domain_reg_offset,unsigned int count)701 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
702 u32 domain_reg_offset,
703 unsigned int count)
704 {
705 /* First configure domain power down transition count ... */
706 regmap_write(pmu->regmap, domain_reg_offset, count);
707 /* ... and then power up count. */
708 regmap_write(pmu->regmap, domain_reg_offset + 4, count);
709 }
710
rockchip_pm_add_subdomain(struct rockchip_pmu * pmu,struct device_node * parent)711 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
712 struct device_node *parent)
713 {
714 struct device_node *np;
715 struct generic_pm_domain *child_domain, *parent_domain;
716 int error;
717
718 for_each_child_of_node(parent, np) {
719 u32 idx;
720
721 error = of_property_read_u32(parent, "reg", &idx);
722 if (error) {
723 dev_err(pmu->dev,
724 "%pOFn: failed to retrieve domain id (reg): %d\n",
725 parent, error);
726 goto err_out;
727 }
728 parent_domain = pmu->genpd_data.domains[idx];
729
730 error = rockchip_pm_add_one_domain(pmu, np);
731 if (error) {
732 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
733 np, error);
734 goto err_out;
735 }
736
737 error = of_property_read_u32(np, "reg", &idx);
738 if (error) {
739 dev_err(pmu->dev,
740 "%pOFn: failed to retrieve domain id (reg): %d\n",
741 np, error);
742 goto err_out;
743 }
744 child_domain = pmu->genpd_data.domains[idx];
745
746 error = pm_genpd_add_subdomain(parent_domain, child_domain);
747 if (error) {
748 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
749 parent_domain->name, child_domain->name, error);
750 goto err_out;
751 } else {
752 dev_dbg(pmu->dev, "%s add subdomain: %s\n",
753 parent_domain->name, child_domain->name);
754 }
755
756 rockchip_pm_add_subdomain(pmu, np);
757 }
758
759 return 0;
760
761 err_out:
762 of_node_put(np);
763 return error;
764 }
765
rockchip_pm_domain_probe(struct platform_device * pdev)766 static int rockchip_pm_domain_probe(struct platform_device *pdev)
767 {
768 struct device *dev = &pdev->dev;
769 struct device_node *np = dev->of_node;
770 struct device_node *node;
771 struct device *parent;
772 struct rockchip_pmu *pmu;
773 const struct of_device_id *match;
774 const struct rockchip_pmu_info *pmu_info;
775 int error;
776
777 if (!np) {
778 dev_err(dev, "device tree node not found\n");
779 return -ENODEV;
780 }
781
782 match = of_match_device(dev->driver->of_match_table, dev);
783 if (!match || !match->data) {
784 dev_err(dev, "missing pmu data\n");
785 return -EINVAL;
786 }
787
788 pmu_info = match->data;
789
790 pmu = devm_kzalloc(dev,
791 struct_size(pmu, domains, pmu_info->num_domains),
792 GFP_KERNEL);
793 if (!pmu)
794 return -ENOMEM;
795
796 pmu->dev = &pdev->dev;
797 mutex_init(&pmu->mutex);
798
799 pmu->info = pmu_info;
800
801 pmu->genpd_data.domains = pmu->domains;
802 pmu->genpd_data.num_domains = pmu_info->num_domains;
803
804 parent = dev->parent;
805 if (!parent) {
806 dev_err(dev, "no parent for syscon devices\n");
807 return -ENODEV;
808 }
809
810 pmu->regmap = syscon_node_to_regmap(parent->of_node);
811 if (IS_ERR(pmu->regmap)) {
812 dev_err(dev, "no regmap available\n");
813 return PTR_ERR(pmu->regmap);
814 }
815
816 /*
817 * Configure power up and down transition delays for CORE
818 * and GPU domains.
819 */
820 if (pmu_info->core_power_transition_time)
821 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
822 pmu_info->core_power_transition_time);
823 if (pmu_info->gpu_pwrcnt_offset)
824 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
825 pmu_info->gpu_power_transition_time);
826
827 error = -ENODEV;
828
829 /*
830 * Prevent any rockchip_pmu_block() from racing with the remainder of
831 * setup (clocks, register initialization).
832 */
833 mutex_lock(&dmc_pmu_mutex);
834
835 for_each_available_child_of_node(np, node) {
836 error = rockchip_pm_add_one_domain(pmu, node);
837 if (error) {
838 dev_err(dev, "failed to handle node %pOFn: %d\n",
839 node, error);
840 of_node_put(node);
841 goto err_out;
842 }
843
844 error = rockchip_pm_add_subdomain(pmu, node);
845 if (error < 0) {
846 dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
847 node, error);
848 of_node_put(node);
849 goto err_out;
850 }
851 }
852
853 if (error) {
854 dev_dbg(dev, "no power domains defined\n");
855 goto err_out;
856 }
857
858 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
859 if (error) {
860 dev_err(dev, "failed to add provider: %d\n", error);
861 goto err_out;
862 }
863
864 /* We only expect one PMU. */
865 if (!WARN_ON_ONCE(dmc_pmu))
866 dmc_pmu = pmu;
867
868 mutex_unlock(&dmc_pmu_mutex);
869
870 return 0;
871
872 err_out:
873 rockchip_pm_domain_cleanup(pmu);
874 mutex_unlock(&dmc_pmu_mutex);
875 return error;
876 }
877
878 static const struct rockchip_domain_info px30_pm_domains[] = {
879 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
880 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
881 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
882 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
883 [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
884 [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false),
885 [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false),
886 [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
887 };
888
889 static const struct rockchip_domain_info rv1126_pm_domains[] = {
890 [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
891 [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
892 [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
893 [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
894 [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
895 [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
896 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
897 };
898
899 static const struct rockchip_domain_info rk3036_pm_domains[] = {
900 [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
901 [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
902 [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
903 [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
904 [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
905 [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
906 [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
907 };
908
909 static const struct rockchip_domain_info rk3066_pm_domains[] = {
910 [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
911 [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
912 [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
913 [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
914 [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false),
915 };
916
917 static const struct rockchip_domain_info rk3128_pm_domains[] = {
918 [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
919 [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
920 [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false),
921 [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
922 [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
923 };
924
925 static const struct rockchip_domain_info rk3188_pm_domains[] = {
926 [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
927 [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
928 [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
929 [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
930 [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
931 };
932
933 static const struct rockchip_domain_info rk3228_pm_domains[] = {
934 [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
935 [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
936 [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
937 [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
938 [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
939 [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
940 [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
941 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
942 [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
943 [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
944 [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
945 };
946
947 static const struct rockchip_domain_info rk3288_pm_domains[] = {
948 [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false),
949 [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
950 [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
951 [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
952 };
953
954 static const struct rockchip_domain_info rk3328_pm_domains[] = {
955 [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
956 [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
957 [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
958 [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
959 [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
960 [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
961 [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
962 [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
963 [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
964 };
965
966 static const struct rockchip_domain_info rk3366_pm_domains[] = {
967 [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
968 [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false),
969 [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
970 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
971 [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
972 [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
973 [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
974 };
975
976 static const struct rockchip_domain_info rk3368_pm_domains[] = {
977 [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
978 [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false),
979 [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
980 [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
981 [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
982 };
983
984 static const struct rockchip_domain_info rk3399_pm_domains[] = {
985 [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
986 [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
987 [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
988 [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
989 [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
990 [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
991 [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
992 [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
993 [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false),
994 [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
995 [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
996 [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
997 [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
998 [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
999 [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false),
1000 [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false),
1001 [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false),
1002 [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
1003 [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
1004 [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false),
1005 [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
1006 [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
1007 [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
1008 [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false),
1009 [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
1010 [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
1011 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
1012 };
1013
1014 static const struct rockchip_domain_info rk3568_pm_domains[] = {
1015 [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
1016 [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
1017 [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
1018 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
1019 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
1020 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
1021 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
1022 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
1023 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
1024 };
1025
1026 static const struct rockchip_domain_info rk3588_pm_domains[] = {
1027 [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false),
1028 [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false),
1029 [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false),
1030 [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false),
1031 [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false),
1032 [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false),
1033 [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false),
1034 [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false),
1035 [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false),
1036 [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false),
1037 [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false),
1038 [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false),
1039 [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false),
1040 [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false),
1041 [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false),
1042 [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false),
1043 [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false),
1044 [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
1045 [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false),
1046 [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false),
1047 [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false),
1048 [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false),
1049 [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false),
1050 [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true),
1051 [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false),
1052 [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false),
1053 [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false),
1054 [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true),
1055 [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false),
1056 };
1057
1058 static const struct rockchip_pmu_info px30_pmu = {
1059 .pwr_offset = 0x18,
1060 .status_offset = 0x20,
1061 .req_offset = 0x64,
1062 .idle_offset = 0x6c,
1063 .ack_offset = 0x6c,
1064
1065 .num_domains = ARRAY_SIZE(px30_pm_domains),
1066 .domain_info = px30_pm_domains,
1067 };
1068
1069 static const struct rockchip_pmu_info rk3036_pmu = {
1070 .req_offset = 0x148,
1071 .idle_offset = 0x14c,
1072 .ack_offset = 0x14c,
1073
1074 .num_domains = ARRAY_SIZE(rk3036_pm_domains),
1075 .domain_info = rk3036_pm_domains,
1076 };
1077
1078 static const struct rockchip_pmu_info rk3066_pmu = {
1079 .pwr_offset = 0x08,
1080 .status_offset = 0x0c,
1081 .req_offset = 0x38, /* PMU_MISC_CON1 */
1082 .idle_offset = 0x0c,
1083 .ack_offset = 0x0c,
1084
1085 .num_domains = ARRAY_SIZE(rk3066_pm_domains),
1086 .domain_info = rk3066_pm_domains,
1087 };
1088
1089 static const struct rockchip_pmu_info rk3128_pmu = {
1090 .pwr_offset = 0x04,
1091 .status_offset = 0x08,
1092 .req_offset = 0x0c,
1093 .idle_offset = 0x10,
1094 .ack_offset = 0x10,
1095
1096 .num_domains = ARRAY_SIZE(rk3128_pm_domains),
1097 .domain_info = rk3128_pm_domains,
1098 };
1099
1100 static const struct rockchip_pmu_info rk3188_pmu = {
1101 .pwr_offset = 0x08,
1102 .status_offset = 0x0c,
1103 .req_offset = 0x38, /* PMU_MISC_CON1 */
1104 .idle_offset = 0x0c,
1105 .ack_offset = 0x0c,
1106
1107 .num_domains = ARRAY_SIZE(rk3188_pm_domains),
1108 .domain_info = rk3188_pm_domains,
1109 };
1110
1111 static const struct rockchip_pmu_info rk3228_pmu = {
1112 .req_offset = 0x40c,
1113 .idle_offset = 0x488,
1114 .ack_offset = 0x488,
1115
1116 .num_domains = ARRAY_SIZE(rk3228_pm_domains),
1117 .domain_info = rk3228_pm_domains,
1118 };
1119
1120 static const struct rockchip_pmu_info rk3288_pmu = {
1121 .pwr_offset = 0x08,
1122 .status_offset = 0x0c,
1123 .req_offset = 0x10,
1124 .idle_offset = 0x14,
1125 .ack_offset = 0x14,
1126
1127 .core_pwrcnt_offset = 0x34,
1128 .gpu_pwrcnt_offset = 0x3c,
1129
1130 .core_power_transition_time = 24, /* 1us */
1131 .gpu_power_transition_time = 24, /* 1us */
1132
1133 .num_domains = ARRAY_SIZE(rk3288_pm_domains),
1134 .domain_info = rk3288_pm_domains,
1135 };
1136
1137 static const struct rockchip_pmu_info rk3328_pmu = {
1138 .req_offset = 0x414,
1139 .idle_offset = 0x484,
1140 .ack_offset = 0x484,
1141
1142 .num_domains = ARRAY_SIZE(rk3328_pm_domains),
1143 .domain_info = rk3328_pm_domains,
1144 };
1145
1146 static const struct rockchip_pmu_info rk3366_pmu = {
1147 .pwr_offset = 0x0c,
1148 .status_offset = 0x10,
1149 .req_offset = 0x3c,
1150 .idle_offset = 0x40,
1151 .ack_offset = 0x40,
1152
1153 .core_pwrcnt_offset = 0x48,
1154 .gpu_pwrcnt_offset = 0x50,
1155
1156 .core_power_transition_time = 24,
1157 .gpu_power_transition_time = 24,
1158
1159 .num_domains = ARRAY_SIZE(rk3366_pm_domains),
1160 .domain_info = rk3366_pm_domains,
1161 };
1162
1163 static const struct rockchip_pmu_info rk3368_pmu = {
1164 .pwr_offset = 0x0c,
1165 .status_offset = 0x10,
1166 .req_offset = 0x3c,
1167 .idle_offset = 0x40,
1168 .ack_offset = 0x40,
1169
1170 .core_pwrcnt_offset = 0x48,
1171 .gpu_pwrcnt_offset = 0x50,
1172
1173 .core_power_transition_time = 24,
1174 .gpu_power_transition_time = 24,
1175
1176 .num_domains = ARRAY_SIZE(rk3368_pm_domains),
1177 .domain_info = rk3368_pm_domains,
1178 };
1179
1180 static const struct rockchip_pmu_info rk3399_pmu = {
1181 .pwr_offset = 0x14,
1182 .status_offset = 0x18,
1183 .req_offset = 0x60,
1184 .idle_offset = 0x64,
1185 .ack_offset = 0x68,
1186
1187 /* ARM Trusted Firmware manages power transition times */
1188
1189 .num_domains = ARRAY_SIZE(rk3399_pm_domains),
1190 .domain_info = rk3399_pm_domains,
1191 };
1192
1193 static const struct rockchip_pmu_info rk3568_pmu = {
1194 .pwr_offset = 0xa0,
1195 .status_offset = 0x98,
1196 .req_offset = 0x50,
1197 .idle_offset = 0x68,
1198 .ack_offset = 0x60,
1199
1200 .num_domains = ARRAY_SIZE(rk3568_pm_domains),
1201 .domain_info = rk3568_pm_domains,
1202 };
1203
1204 static const struct rockchip_pmu_info rk3588_pmu = {
1205 .pwr_offset = 0x14c,
1206 .status_offset = 0x180,
1207 .req_offset = 0x10c,
1208 .idle_offset = 0x120,
1209 .ack_offset = 0x118,
1210 .repair_status_offset = 0x290,
1211
1212 .num_domains = ARRAY_SIZE(rk3588_pm_domains),
1213 .domain_info = rk3588_pm_domains,
1214 };
1215
1216 static const struct rockchip_pmu_info rv1126_pmu = {
1217 .pwr_offset = 0x110,
1218 .status_offset = 0x108,
1219 .req_offset = 0xc0,
1220 .idle_offset = 0xd8,
1221 .ack_offset = 0xd0,
1222
1223 .num_domains = ARRAY_SIZE(rv1126_pm_domains),
1224 .domain_info = rv1126_pm_domains,
1225 };
1226
1227 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1228 {
1229 .compatible = "rockchip,px30-power-controller",
1230 .data = (void *)&px30_pmu,
1231 },
1232 {
1233 .compatible = "rockchip,rk3036-power-controller",
1234 .data = (void *)&rk3036_pmu,
1235 },
1236 {
1237 .compatible = "rockchip,rk3066-power-controller",
1238 .data = (void *)&rk3066_pmu,
1239 },
1240 {
1241 .compatible = "rockchip,rk3128-power-controller",
1242 .data = (void *)&rk3128_pmu,
1243 },
1244 {
1245 .compatible = "rockchip,rk3188-power-controller",
1246 .data = (void *)&rk3188_pmu,
1247 },
1248 {
1249 .compatible = "rockchip,rk3228-power-controller",
1250 .data = (void *)&rk3228_pmu,
1251 },
1252 {
1253 .compatible = "rockchip,rk3288-power-controller",
1254 .data = (void *)&rk3288_pmu,
1255 },
1256 {
1257 .compatible = "rockchip,rk3328-power-controller",
1258 .data = (void *)&rk3328_pmu,
1259 },
1260 {
1261 .compatible = "rockchip,rk3366-power-controller",
1262 .data = (void *)&rk3366_pmu,
1263 },
1264 {
1265 .compatible = "rockchip,rk3368-power-controller",
1266 .data = (void *)&rk3368_pmu,
1267 },
1268 {
1269 .compatible = "rockchip,rk3399-power-controller",
1270 .data = (void *)&rk3399_pmu,
1271 },
1272 {
1273 .compatible = "rockchip,rk3568-power-controller",
1274 .data = (void *)&rk3568_pmu,
1275 },
1276 {
1277 .compatible = "rockchip,rk3588-power-controller",
1278 .data = (void *)&rk3588_pmu,
1279 },
1280 {
1281 .compatible = "rockchip,rv1126-power-controller",
1282 .data = (void *)&rv1126_pmu,
1283 },
1284 { /* sentinel */ },
1285 };
1286
1287 static struct platform_driver rockchip_pm_domain_driver = {
1288 .probe = rockchip_pm_domain_probe,
1289 .driver = {
1290 .name = "rockchip-pm-domain",
1291 .of_match_table = rockchip_pm_domain_dt_match,
1292 /*
1293 * We can't forcibly eject devices from the power
1294 * domain, so we can't really remove power domains
1295 * once they were added.
1296 */
1297 .suppress_bind_attrs = true,
1298 },
1299 };
1300
rockchip_pm_domain_drv_register(void)1301 static int __init rockchip_pm_domain_drv_register(void)
1302 {
1303 return platform_driver_register(&rockchip_pm_domain_driver);
1304 }
1305 postcore_initcall(rockchip_pm_domain_drv_register);
1306