1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015, Sony Mobile Communications AB.
4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11 #include <linux/regulator/driver.h>
12 #include <linux/regulator/of_regulator.h>
13 #include <linux/soc/qcom/smd-rpm.h>
14
15 struct qcom_rpm_reg {
16 struct device *dev;
17
18 struct qcom_smd_rpm *rpm;
19
20 u32 type;
21 u32 id;
22
23 struct regulator_desc desc;
24
25 int is_enabled;
26 int uV;
27 u32 load;
28
29 unsigned int enabled_updated:1;
30 unsigned int uv_updated:1;
31 unsigned int load_updated:1;
32 };
33
34 struct rpm_regulator_req {
35 __le32 key;
36 __le32 nbytes;
37 __le32 value;
38 };
39
40 #define RPM_KEY_SWEN 0x6e657773 /* "swen" */
41 #define RPM_KEY_UV 0x00007675 /* "uv" */
42 #define RPM_KEY_MA 0x0000616d /* "ma" */
43
rpm_reg_write_active(struct qcom_rpm_reg * vreg)44 static int rpm_reg_write_active(struct qcom_rpm_reg *vreg)
45 {
46 struct rpm_regulator_req req[3];
47 int reqlen = 0;
48 int ret;
49
50 if (vreg->enabled_updated) {
51 req[reqlen].key = cpu_to_le32(RPM_KEY_SWEN);
52 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
53 req[reqlen].value = cpu_to_le32(vreg->is_enabled);
54 reqlen++;
55 }
56
57 if (vreg->uv_updated && vreg->is_enabled) {
58 req[reqlen].key = cpu_to_le32(RPM_KEY_UV);
59 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
60 req[reqlen].value = cpu_to_le32(vreg->uV);
61 reqlen++;
62 }
63
64 if (vreg->load_updated && vreg->is_enabled) {
65 req[reqlen].key = cpu_to_le32(RPM_KEY_MA);
66 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
67 req[reqlen].value = cpu_to_le32(vreg->load / 1000);
68 reqlen++;
69 }
70
71 if (!reqlen)
72 return 0;
73
74 ret = qcom_rpm_smd_write(vreg->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
75 vreg->type, vreg->id,
76 req, sizeof(req[0]) * reqlen);
77 if (!ret) {
78 vreg->enabled_updated = 0;
79 vreg->uv_updated = 0;
80 vreg->load_updated = 0;
81 }
82
83 return ret;
84 }
85
rpm_reg_enable(struct regulator_dev * rdev)86 static int rpm_reg_enable(struct regulator_dev *rdev)
87 {
88 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
89 int ret;
90
91 vreg->is_enabled = 1;
92 vreg->enabled_updated = 1;
93
94 ret = rpm_reg_write_active(vreg);
95 if (ret)
96 vreg->is_enabled = 0;
97
98 return ret;
99 }
100
rpm_reg_is_enabled(struct regulator_dev * rdev)101 static int rpm_reg_is_enabled(struct regulator_dev *rdev)
102 {
103 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
104
105 return vreg->is_enabled;
106 }
107
rpm_reg_disable(struct regulator_dev * rdev)108 static int rpm_reg_disable(struct regulator_dev *rdev)
109 {
110 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
111 int ret;
112
113 vreg->is_enabled = 0;
114 vreg->enabled_updated = 1;
115
116 ret = rpm_reg_write_active(vreg);
117 if (ret)
118 vreg->is_enabled = 1;
119
120 return ret;
121 }
122
rpm_reg_get_voltage(struct regulator_dev * rdev)123 static int rpm_reg_get_voltage(struct regulator_dev *rdev)
124 {
125 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
126
127 return vreg->uV;
128 }
129
rpm_reg_set_voltage(struct regulator_dev * rdev,int min_uV,int max_uV,unsigned * selector)130 static int rpm_reg_set_voltage(struct regulator_dev *rdev,
131 int min_uV,
132 int max_uV,
133 unsigned *selector)
134 {
135 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
136 int ret;
137 int old_uV = vreg->uV;
138
139 vreg->uV = min_uV;
140 vreg->uv_updated = 1;
141
142 ret = rpm_reg_write_active(vreg);
143 if (ret)
144 vreg->uV = old_uV;
145
146 return ret;
147 }
148
rpm_reg_set_load(struct regulator_dev * rdev,int load_uA)149 static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
150 {
151 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
152 u32 old_load = vreg->load;
153 int ret;
154
155 vreg->load = load_uA;
156 vreg->load_updated = 1;
157 ret = rpm_reg_write_active(vreg);
158 if (ret)
159 vreg->load = old_load;
160
161 return ret;
162 }
163
164 static const struct regulator_ops rpm_smps_ldo_ops = {
165 .enable = rpm_reg_enable,
166 .disable = rpm_reg_disable,
167 .is_enabled = rpm_reg_is_enabled,
168 .list_voltage = regulator_list_voltage_linear_range,
169
170 .get_voltage = rpm_reg_get_voltage,
171 .set_voltage = rpm_reg_set_voltage,
172
173 .set_load = rpm_reg_set_load,
174 };
175
176 static const struct regulator_ops rpm_smps_ldo_ops_fixed = {
177 .enable = rpm_reg_enable,
178 .disable = rpm_reg_disable,
179 .is_enabled = rpm_reg_is_enabled,
180
181 .get_voltage = rpm_reg_get_voltage,
182 .set_voltage = rpm_reg_set_voltage,
183
184 .set_load = rpm_reg_set_load,
185 };
186
187 static const struct regulator_ops rpm_switch_ops = {
188 .enable = rpm_reg_enable,
189 .disable = rpm_reg_disable,
190 .is_enabled = rpm_reg_is_enabled,
191 };
192
193 static const struct regulator_ops rpm_bob_ops = {
194 .enable = rpm_reg_enable,
195 .disable = rpm_reg_disable,
196 .is_enabled = rpm_reg_is_enabled,
197
198 .get_voltage = rpm_reg_get_voltage,
199 .set_voltage = rpm_reg_set_voltage,
200 };
201
202 static const struct regulator_ops rpm_mp5496_ops = {
203 .enable = rpm_reg_enable,
204 .disable = rpm_reg_disable,
205 .is_enabled = rpm_reg_is_enabled,
206 .list_voltage = regulator_list_voltage_linear_range,
207
208 .get_voltage = rpm_reg_get_voltage,
209 .set_voltage = rpm_reg_set_voltage,
210 };
211
212 static const struct regulator_desc pma8084_hfsmps = {
213 .linear_ranges = (struct linear_range[]) {
214 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
215 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
216 },
217 .n_linear_ranges = 2,
218 .n_voltages = 159,
219 .ops = &rpm_smps_ldo_ops,
220 };
221
222 static const struct regulator_desc pma8084_ftsmps = {
223 .linear_ranges = (struct linear_range[]) {
224 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
225 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
226 },
227 .n_linear_ranges = 2,
228 .n_voltages = 262,
229 .ops = &rpm_smps_ldo_ops,
230 };
231
232 static const struct regulator_desc pma8084_pldo = {
233 .linear_ranges = (struct linear_range[]) {
234 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
235 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
236 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
237 },
238 .n_linear_ranges = 3,
239 .n_voltages = 164,
240 .ops = &rpm_smps_ldo_ops,
241 };
242
243 static const struct regulator_desc pma8084_nldo = {
244 .linear_ranges = (struct linear_range[]) {
245 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
246 },
247 .n_linear_ranges = 1,
248 .n_voltages = 64,
249 .ops = &rpm_smps_ldo_ops,
250 };
251
252 static const struct regulator_desc pma8084_switch = {
253 .ops = &rpm_switch_ops,
254 };
255
256 static const struct regulator_desc pm8226_hfsmps = {
257 .linear_ranges = (struct linear_range[]) {
258 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
259 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
260 },
261 .n_linear_ranges = 2,
262 .n_voltages = 159,
263 .ops = &rpm_smps_ldo_ops,
264 };
265
266 static const struct regulator_desc pm8226_ftsmps = {
267 .linear_ranges = (struct linear_range[]) {
268 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
269 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
270 },
271 .n_linear_ranges = 2,
272 .n_voltages = 262,
273 .ops = &rpm_smps_ldo_ops,
274 };
275
276 static const struct regulator_desc pm8226_pldo = {
277 .linear_ranges = (struct linear_range[]) {
278 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
279 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
280 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
281 },
282 .n_linear_ranges = 3,
283 .n_voltages = 164,
284 .ops = &rpm_smps_ldo_ops,
285 };
286
287 static const struct regulator_desc pm8226_nldo = {
288 .linear_ranges = (struct linear_range[]) {
289 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
290 },
291 .n_linear_ranges = 1,
292 .n_voltages = 64,
293 .ops = &rpm_smps_ldo_ops,
294 };
295
296 static const struct regulator_desc pm8226_switch = {
297 .ops = &rpm_switch_ops,
298 };
299
300 static const struct regulator_desc pm8x41_hfsmps = {
301 .linear_ranges = (struct linear_range[]) {
302 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
303 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
304 },
305 .n_linear_ranges = 2,
306 .n_voltages = 159,
307 .ops = &rpm_smps_ldo_ops,
308 };
309
310 static const struct regulator_desc pm8841_ftsmps = {
311 .linear_ranges = (struct linear_range[]) {
312 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
313 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
314 },
315 .n_linear_ranges = 2,
316 .n_voltages = 262,
317 .ops = &rpm_smps_ldo_ops,
318 };
319
320 static const struct regulator_desc pm8941_boost = {
321 .linear_ranges = (struct linear_range[]) {
322 REGULATOR_LINEAR_RANGE(4000000, 0, 30, 50000),
323 },
324 .n_linear_ranges = 1,
325 .n_voltages = 31,
326 .ops = &rpm_smps_ldo_ops,
327 };
328
329 static const struct regulator_desc pm8941_pldo = {
330 .linear_ranges = (struct linear_range[]) {
331 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
332 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
333 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
334 },
335 .n_linear_ranges = 3,
336 .n_voltages = 164,
337 .ops = &rpm_smps_ldo_ops,
338 };
339
340 static const struct regulator_desc pm8941_nldo = {
341 .linear_ranges = (struct linear_range[]) {
342 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
343 },
344 .n_linear_ranges = 1,
345 .n_voltages = 64,
346 .ops = &rpm_smps_ldo_ops,
347 };
348
349 static const struct regulator_desc pm8941_lnldo = {
350 .fixed_uV = 1740000,
351 .n_voltages = 1,
352 .ops = &rpm_smps_ldo_ops_fixed,
353 };
354
355 static const struct regulator_desc pm8941_switch = {
356 .ops = &rpm_switch_ops,
357 };
358
359 static const struct regulator_desc pm8916_pldo = {
360 .linear_ranges = (struct linear_range[]) {
361 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
362 },
363 .n_linear_ranges = 1,
364 .n_voltages = 128,
365 .ops = &rpm_smps_ldo_ops,
366 };
367
368 static const struct regulator_desc pm8916_nldo = {
369 .linear_ranges = (struct linear_range[]) {
370 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
371 },
372 .n_linear_ranges = 1,
373 .n_voltages = 94,
374 .ops = &rpm_smps_ldo_ops,
375 };
376
377 static const struct regulator_desc pm8916_buck_lvo_smps = {
378 .linear_ranges = (struct linear_range[]) {
379 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
380 REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000),
381 },
382 .n_linear_ranges = 2,
383 .n_voltages = 128,
384 .ops = &rpm_smps_ldo_ops,
385 };
386
387 static const struct regulator_desc pm8916_buck_hvo_smps = {
388 .linear_ranges = (struct linear_range[]) {
389 REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000),
390 },
391 .n_linear_ranges = 1,
392 .n_voltages = 32,
393 .ops = &rpm_smps_ldo_ops,
394 };
395
396 static const struct regulator_desc pm8950_hfsmps = {
397 .linear_ranges = (struct linear_range[]) {
398 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
399 REGULATOR_LINEAR_RANGE(1550000, 96, 127, 25000),
400 },
401 .n_linear_ranges = 2,
402 .n_voltages = 128,
403 .ops = &rpm_smps_ldo_ops,
404 };
405
406 static const struct regulator_desc pm8950_ftsmps2p5 = {
407 .linear_ranges = (struct linear_range[]) {
408 REGULATOR_LINEAR_RANGE(80000, 0, 255, 5000),
409 REGULATOR_LINEAR_RANGE(160000, 256, 460, 10000),
410 },
411 .n_linear_ranges = 2,
412 .n_voltages = 461,
413 .ops = &rpm_smps_ldo_ops,
414 };
415
416 static const struct regulator_desc pm8950_ult_nldo = {
417 .linear_ranges = (struct linear_range[]) {
418 REGULATOR_LINEAR_RANGE(375000, 0, 202, 12500),
419 },
420 .n_linear_ranges = 1,
421 .n_voltages = 203,
422 .ops = &rpm_smps_ldo_ops,
423 };
424
425 static const struct regulator_desc pm8950_ult_pldo = {
426 .linear_ranges = (struct linear_range[]) {
427 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
428 },
429 .n_linear_ranges = 1,
430 .n_voltages = 128,
431 .ops = &rpm_smps_ldo_ops,
432 };
433
434 static const struct regulator_desc pm8950_pldo_lv = {
435 .linear_ranges = (struct linear_range[]) {
436 REGULATOR_LINEAR_RANGE(1500000, 0, 16, 25000),
437 },
438 .n_linear_ranges = 1,
439 .n_voltages = 17,
440 .ops = &rpm_smps_ldo_ops,
441 };
442
443 static const struct regulator_desc pm8950_pldo = {
444 .linear_ranges = (struct linear_range[]) {
445 REGULATOR_LINEAR_RANGE(975000, 0, 164, 12500),
446 },
447 .n_linear_ranges = 1,
448 .n_voltages = 165,
449 .ops = &rpm_smps_ldo_ops,
450 };
451
452 static const struct regulator_desc pm8953_lnldo = {
453 .linear_ranges = (struct linear_range[]) {
454 REGULATOR_LINEAR_RANGE(690000, 0, 7, 60000),
455 REGULATOR_LINEAR_RANGE(1380000, 8, 15, 120000),
456 },
457 .n_linear_ranges = 2,
458 .n_voltages = 16,
459 .ops = &rpm_smps_ldo_ops,
460 };
461
462 static const struct regulator_desc pm8953_ult_nldo = {
463 .linear_ranges = (struct linear_range[]) {
464 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
465 },
466 .n_linear_ranges = 1,
467 .n_voltages = 94,
468 .ops = &rpm_smps_ldo_ops,
469 };
470
471 static const struct regulator_desc pm8994_hfsmps = {
472 .linear_ranges = (struct linear_range[]) {
473 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
474 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
475 },
476 .n_linear_ranges = 2,
477 .n_voltages = 159,
478 .ops = &rpm_smps_ldo_ops,
479 };
480
481 static const struct regulator_desc pm8994_ftsmps = {
482 .linear_ranges = (struct linear_range[]) {
483 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
484 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
485 },
486 .n_linear_ranges = 2,
487 .n_voltages = 350,
488 .ops = &rpm_smps_ldo_ops,
489 };
490
491 static const struct regulator_desc pm8994_nldo = {
492 .linear_ranges = (struct linear_range[]) {
493 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
494 },
495 .n_linear_ranges = 1,
496 .n_voltages = 64,
497 .ops = &rpm_smps_ldo_ops,
498 };
499
500 static const struct regulator_desc pm8994_pldo = {
501 .linear_ranges = (struct linear_range[]) {
502 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
503 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
504 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
505 },
506 .n_linear_ranges = 3,
507 .n_voltages = 164,
508 .ops = &rpm_smps_ldo_ops,
509 };
510
511 static const struct regulator_desc pm8994_switch = {
512 .ops = &rpm_switch_ops,
513 };
514
515 static const struct regulator_desc pm8994_lnldo = {
516 .fixed_uV = 1740000,
517 .n_voltages = 1,
518 .ops = &rpm_smps_ldo_ops_fixed,
519 };
520
521 static const struct regulator_desc pmi8994_ftsmps = {
522 .linear_ranges = (struct linear_range[]) {
523 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
524 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
525 },
526 .n_linear_ranges = 2,
527 .n_voltages = 350,
528 .ops = &rpm_smps_ldo_ops,
529 };
530
531 static const struct regulator_desc pmi8994_hfsmps = {
532 .linear_ranges = (struct linear_range[]) {
533 REGULATOR_LINEAR_RANGE(350000, 0, 80, 12500),
534 REGULATOR_LINEAR_RANGE(700000, 81, 141, 25000),
535 },
536 .n_linear_ranges = 2,
537 .n_voltages = 142,
538 .ops = &rpm_smps_ldo_ops,
539 };
540
541 static const struct regulator_desc pmi8994_bby = {
542 .linear_ranges = (struct linear_range[]) {
543 REGULATOR_LINEAR_RANGE(3000000, 0, 44, 50000),
544 },
545 .n_linear_ranges = 1,
546 .n_voltages = 45,
547 .ops = &rpm_bob_ops,
548 };
549
550 static const struct regulator_desc pm8998_ftsmps = {
551 .linear_ranges = (struct linear_range[]) {
552 REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000),
553 },
554 .n_linear_ranges = 1,
555 .n_voltages = 259,
556 .ops = &rpm_smps_ldo_ops,
557 };
558
559 static const struct regulator_desc pm8998_hfsmps = {
560 .linear_ranges = (struct linear_range[]) {
561 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
562 },
563 .n_linear_ranges = 1,
564 .n_voltages = 216,
565 .ops = &rpm_smps_ldo_ops,
566 };
567
568 static const struct regulator_desc pm8998_nldo = {
569 .linear_ranges = (struct linear_range[]) {
570 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
571 },
572 .n_linear_ranges = 1,
573 .n_voltages = 128,
574 .ops = &rpm_smps_ldo_ops,
575 };
576
577 static const struct regulator_desc pm8998_pldo = {
578 .linear_ranges = (struct linear_range[]) {
579 REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000),
580 },
581 .n_linear_ranges = 1,
582 .n_voltages = 256,
583 .ops = &rpm_smps_ldo_ops,
584 };
585
586 static const struct regulator_desc pm8998_pldo_lv = {
587 .linear_ranges = (struct linear_range[]) {
588 REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000),
589 },
590 .n_linear_ranges = 1,
591 .n_voltages = 128,
592 .ops = &rpm_smps_ldo_ops,
593 };
594
595 static const struct regulator_desc pm8998_switch = {
596 .ops = &rpm_switch_ops,
597 };
598
599 static const struct regulator_desc pmi8998_bob = {
600 .linear_ranges = (struct linear_range[]) {
601 REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000),
602 },
603 .n_linear_ranges = 1,
604 .n_voltages = 84,
605 .ops = &rpm_bob_ops,
606 };
607
608 static const struct regulator_desc pm660_ftsmps = {
609 .linear_ranges = (struct linear_range[]) {
610 REGULATOR_LINEAR_RANGE(355000, 0, 199, 5000),
611 },
612 .n_linear_ranges = 1,
613 .n_voltages = 200,
614 .ops = &rpm_smps_ldo_ops,
615 };
616
617 static const struct regulator_desc pm660_hfsmps = {
618 .linear_ranges = (struct linear_range[]) {
619 REGULATOR_LINEAR_RANGE(320000, 0, 216, 8000),
620 },
621 .n_linear_ranges = 1,
622 .n_voltages = 217,
623 .ops = &rpm_smps_ldo_ops,
624 };
625
626 static const struct regulator_desc pm660_ht_nldo = {
627 .linear_ranges = (struct linear_range[]) {
628 REGULATOR_LINEAR_RANGE(312000, 0, 124, 8000),
629 },
630 .n_linear_ranges = 1,
631 .n_voltages = 125,
632 .ops = &rpm_smps_ldo_ops,
633 };
634
635 static const struct regulator_desc pm660_ht_lvpldo = {
636 .linear_ranges = (struct linear_range[]) {
637 REGULATOR_LINEAR_RANGE(1504000, 0, 62, 8000),
638 },
639 .n_linear_ranges = 1,
640 .n_voltages = 63,
641 .ops = &rpm_smps_ldo_ops,
642 };
643
644 static const struct regulator_desc pm660_nldo660 = {
645 .linear_ranges = (struct linear_range[]) {
646 REGULATOR_LINEAR_RANGE(320000, 0, 123, 8000),
647 },
648 .n_linear_ranges = 1,
649 .n_voltages = 124,
650 .ops = &rpm_smps_ldo_ops,
651 };
652
653 static const struct regulator_desc pm660_pldo660 = {
654 .linear_ranges = (struct linear_range[]) {
655 REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
656 },
657 .n_linear_ranges = 1,
658 .n_voltages = 256,
659 .ops = &rpm_smps_ldo_ops,
660 };
661
662 static const struct regulator_desc pm660l_bob = {
663 .linear_ranges = (struct linear_range[]) {
664 REGULATOR_LINEAR_RANGE(1800000, 0, 84, 32000),
665 },
666 .n_linear_ranges = 1,
667 .n_voltages = 85,
668 .ops = &rpm_bob_ops,
669 };
670
671 static const struct regulator_desc pm6125_ftsmps = {
672 .linear_ranges = (struct linear_range[]) {
673 REGULATOR_LINEAR_RANGE(300000, 0, 268, 4000),
674 },
675 .n_linear_ranges = 1,
676 .n_voltages = 269,
677 .ops = &rpm_smps_ldo_ops,
678 };
679
680 static const struct regulator_desc pms405_hfsmps3 = {
681 .linear_ranges = (struct linear_range[]) {
682 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
683 },
684 .n_linear_ranges = 1,
685 .n_voltages = 216,
686 .ops = &rpm_smps_ldo_ops,
687 };
688
689 static const struct regulator_desc pms405_nldo300 = {
690 .linear_ranges = (struct linear_range[]) {
691 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
692 },
693 .n_linear_ranges = 1,
694 .n_voltages = 128,
695 .ops = &rpm_smps_ldo_ops,
696 };
697
698 static const struct regulator_desc pms405_nldo1200 = {
699 .linear_ranges = (struct linear_range[]) {
700 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
701 },
702 .n_linear_ranges = 1,
703 .n_voltages = 128,
704 .ops = &rpm_smps_ldo_ops,
705 };
706
707 static const struct regulator_desc pms405_pldo50 = {
708 .linear_ranges = (struct linear_range[]) {
709 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
710 },
711 .n_linear_ranges = 1,
712 .n_voltages = 129,
713 .ops = &rpm_smps_ldo_ops,
714 };
715
716 static const struct regulator_desc pms405_pldo150 = {
717 .linear_ranges = (struct linear_range[]) {
718 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
719 },
720 .n_linear_ranges = 1,
721 .n_voltages = 129,
722 .ops = &rpm_smps_ldo_ops,
723 };
724
725 static const struct regulator_desc pms405_pldo600 = {
726 .linear_ranges = (struct linear_range[]) {
727 REGULATOR_LINEAR_RANGE(1256000, 0, 98, 8000),
728 },
729 .n_linear_ranges = 1,
730 .n_voltages = 99,
731 .ops = &rpm_smps_ldo_ops,
732 };
733
734 static const struct regulator_desc mp5496_smpa2 = {
735 .linear_ranges = (struct linear_range[]) {
736 REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
737 },
738 .n_linear_ranges = 1,
739 .n_voltages = 128,
740 .ops = &rpm_mp5496_ops,
741 };
742
743 static const struct regulator_desc mp5496_ldoa2 = {
744 .linear_ranges = (struct linear_range[]) {
745 REGULATOR_LINEAR_RANGE(800000, 0, 127, 25000),
746 },
747 .n_linear_ranges = 1,
748 .n_voltages = 128,
749 .ops = &rpm_mp5496_ops,
750 };
751
752 static const struct regulator_desc pm2250_lvftsmps = {
753 .linear_ranges = (struct linear_range[]) {
754 REGULATOR_LINEAR_RANGE(320000, 0, 269, 4000),
755 },
756 .n_linear_ranges = 1,
757 .n_voltages = 270,
758 .ops = &rpm_smps_ldo_ops,
759 };
760
761 static const struct regulator_desc pm2250_ftsmps = {
762 .linear_ranges = (struct linear_range[]) {
763 REGULATOR_LINEAR_RANGE(640000, 0, 269, 8000),
764 },
765 .n_linear_ranges = 1,
766 .n_voltages = 270,
767 .ops = &rpm_smps_ldo_ops,
768 };
769
770 struct rpm_regulator_data {
771 const char *name;
772 u32 type;
773 u32 id;
774 const struct regulator_desc *desc;
775 const char *supply;
776 };
777
778 static const struct rpm_regulator_data rpm_mp5496_regulators[] = {
779 { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" },
780 { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" },
781 {}
782 };
783
784 static const struct rpm_regulator_data rpm_pm2250_regulators[] = {
785 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm2250_lvftsmps, "vdd_s1" },
786 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm2250_lvftsmps, "vdd_s2" },
787 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm2250_lvftsmps, "vdd_s3" },
788 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm2250_ftsmps, "vdd_s4" },
789 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
790 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
791 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
792 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
793 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
794 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
795 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
796 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
797 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
798 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
799 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
800 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
801 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
802 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
803 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
804 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
805 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
806 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
807 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
808 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
809 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
810 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
811 {}
812 };
813
814 static const struct rpm_regulator_data rpm_pm6125_regulators[] = {
815 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm6125_ftsmps, "vdd_s1" },
816 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm6125_ftsmps, "vdd_s2" },
817 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm6125_ftsmps, "vdd_s3" },
818 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm6125_ftsmps, "vdd_s4" },
819 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
820 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_hfsmps, "vdd_s6" },
821 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" },
822 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm6125_ftsmps, "vdd_s8" },
823 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
824 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l2_l3_l4" },
825 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3_l4" },
826 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_nldo660, "vdd_l2_l3_l4" },
827 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
828 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l6_l8" },
829 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
830 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l6_l8" },
831 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l9_l11" },
832 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
833 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l9_l11" },
834 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l12_l16" },
835 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
836 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
837 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
838 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l12_l16" },
839 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
840 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
841 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
842 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
843 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
844 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
845 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm660_pldo660, "vdd_l23_l24" },
846 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm660_pldo660, "vdd_l23_l24" },
847 { }
848 };
849
850 static const struct rpm_regulator_data rpm_pm660_regulators[] = {
851 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm660_ftsmps, "vdd_s1" },
852 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm660_ftsmps, "vdd_s2" },
853 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm660_ftsmps, "vdd_s3" },
854 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm660_hfsmps, "vdd_s4" },
855 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" },
856 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm660_hfsmps, "vdd_s6" },
857 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l6_l7" },
858 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_ht_nldo, "vdd_l2_l3" },
859 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3" },
860 /* l4 is unaccessible on PM660 */
861 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" },
862 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_ht_nldo, "vdd_l1_l6_l7" },
863 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_ht_nldo, "vdd_l1_l6_l7" },
864 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
865 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
866 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
867 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
868 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
869 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
870 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
871 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
872 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
873 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
874 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
875 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
876 { }
877 };
878
879 static const struct rpm_regulator_data rpm_pm660l_regulators[] = {
880 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm660_ftsmps, "vdd_s1" },
881 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm660_ftsmps, "vdd_s2" },
882 { "s3", QCOM_SMD_RPM_RWCX, 0, &pm660_ftsmps, "vdd_s3_s4" },
883 { "s5", QCOM_SMD_RPM_RWMX, 0, &pm660_ftsmps, "vdd_s5" },
884 { "l1", QCOM_SMD_RPM_LDOB, 1, &pm660_nldo660, "vdd_l1_l9_l10" },
885 { "l2", QCOM_SMD_RPM_LDOB, 2, &pm660_pldo660, "vdd_l2" },
886 { "l3", QCOM_SMD_RPM_LDOB, 3, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
887 { "l4", QCOM_SMD_RPM_LDOB, 4, &pm660_pldo660, "vdd_l4_l6" },
888 { "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
889 { "l6", QCOM_SMD_RPM_LDOB, 6, &pm660_pldo660, "vdd_l4_l6" },
890 { "l7", QCOM_SMD_RPM_LDOB, 7, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
891 { "l8", QCOM_SMD_RPM_LDOB, 8, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
892 { "l9", QCOM_SMD_RPM_RWLC, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
893 { "l10", QCOM_SMD_RPM_RWLM, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
894 { "bob", QCOM_SMD_RPM_BOBB, 1, &pm660l_bob, "vdd_bob", },
895 { }
896 };
897
898 static const struct rpm_regulator_data rpm_pm8226_regulators[] = {
899 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8226_hfsmps, "vdd_s1" },
900 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8226_ftsmps, "vdd_s2" },
901 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8226_hfsmps, "vdd_s3" },
902 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8226_hfsmps, "vdd_s4" },
903 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8226_hfsmps, "vdd_s5" },
904 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
905 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
906 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8226_nldo, "vdd_l3_l24_l26" },
907 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
908 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
909 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
910 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
911 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
912 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
913 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8226_pldo, "vdd_l10_l11_l13" },
914 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l10_l11_l13" },
915 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8226_pldo, "vdd_l12_l14" },
916 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8226_pldo, "vdd_l10_l11_l13" },
917 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8226_pldo, "vdd_l12_l14" },
918 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
919 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
920 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
921 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
922 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
923 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
924 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
925 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
926 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
927 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8226_nldo, "vdd_l3_l24_l26" },
928 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8226_pldo, "vdd_l25" },
929 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8226_nldo, "vdd_l3_l24_l26" },
930 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
931 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
932 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8226_switch, "vdd_lvs1" },
933 {}
934 };
935
936 static const struct rpm_regulator_data rpm_pm8841_regulators[] = {
937 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" },
938 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" },
939 { "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" },
940 { "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" },
941 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
942 { "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" },
943 { "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" },
944 { "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" },
945 {}
946 };
947
948 static const struct rpm_regulator_data rpm_pm8909_regulators[] = {
949 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
950 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_hvo_smps, "vdd_s2" },
951 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1" },
952 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l2_l5" },
953 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l3_l6_l10" },
954 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l7" },
955 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_pldo, "vdd_l2_l5" },
956 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l3_l6_l10" },
957 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l4_l7" },
958 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
959 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
960 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_nldo, "vdd_l3_l6_l10" },
961 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l8_l11_l15_l18" },
962 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
963 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l13" },
964 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
965 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
966 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
967 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
968 {}
969 };
970
971 static const struct rpm_regulator_data rpm_pm8916_regulators[] = {
972 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
973 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" },
974 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" },
975 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" },
976 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" },
977 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" },
978 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" },
979 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" },
980 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" },
981 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" },
982 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" },
983 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
984 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
985 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
986 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
987 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
988 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
989 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
990 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
991 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
992 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
993 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
994 {}
995 };
996
997 static const struct rpm_regulator_data rpm_pm8941_regulators[] = {
998 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" },
999 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" },
1000 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" },
1001 { "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost },
1002
1003 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" },
1004 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" },
1005 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" },
1006 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" },
1007 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" },
1008 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1009 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" },
1010 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1011 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1012 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1013 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" },
1014 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1015 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1016 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1017 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1018 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1019 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1020 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1021 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1022 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1023 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" },
1024 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1025 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1026 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1027
1028 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" },
1029 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" },
1030 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" },
1031
1032 { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" },
1033 { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" },
1034
1035 {}
1036 };
1037
1038 static const struct rpm_regulator_data rpm_pm8950_regulators[] = {
1039 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8950_hfsmps, "vdd_s1" },
1040 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8950_hfsmps, "vdd_s2" },
1041 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8950_hfsmps, "vdd_s3" },
1042 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8950_hfsmps, "vdd_s4" },
1043 /* S5 is managed via SPMI. */
1044 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_hfsmps, "vdd_s6" },
1045
1046 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8950_ult_nldo, "vdd_l1_l19" },
1047 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8950_ult_nldo, "vdd_l2_l23" },
1048 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8950_ult_nldo, "vdd_l3" },
1049 /* L4 seems not to exist. */
1050 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
1051 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
1052 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
1053 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1054 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1055 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_nldo, "vdd_l9_l10_l13_l14_l15_l18"},
1056 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1057 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1058 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1059 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1060 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1061 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l5_l6_l7_l16" },
1062 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1063 /* L18 seems not to exist. */
1064 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8950_pldo, "vdd_l1_l19" },
1065 /* L20 & L21 seem not to exist. */
1066 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_pldo, "vdd_l8_l11_l12_l17_l22" },
1067 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8950_pldo, "vdd_l2_l23" },
1068 {}
1069 };
1070
1071 static const struct rpm_regulator_data rpm_pm8953_regulators[] = {
1072 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_hfsmps, "vdd_s1" },
1073 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_hfsmps, "vdd_s2" },
1074 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
1075 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
1076 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8950_ftsmps2p5, "vdd_s5" },
1077 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_ftsmps2p5, "vdd_s6" },
1078 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" },
1079
1080 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8953_ult_nldo, "vdd_l1" },
1081 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8953_ult_nldo, "vdd_l2_l3" },
1082 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8953_ult_nldo, "vdd_l2_l3" },
1083 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1084 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1085 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1086 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1087 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1088 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1089 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1090 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1091 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1092 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1093 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1094 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1095 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1096 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1097 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1098 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8953_ult_nldo, "vdd_l4_l5_l6_l7_l16_l19" },
1099 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8953_lnldo, "vdd_l20" },
1100 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8953_lnldo, "vdd_l21" },
1101 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1102 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8953_ult_nldo, "vdd_l23" },
1103 {}
1104 };
1105
1106 static const struct rpm_regulator_data rpm_pm8994_regulators[] = {
1107 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" },
1108 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" },
1109 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" },
1110 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" },
1111 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" },
1112 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" },
1113 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" },
1114 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" },
1115 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" },
1116 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" },
1117 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" },
1118 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" },
1119 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" },
1120 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" },
1121 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" },
1122 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" },
1123 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" },
1124 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" },
1125 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" },
1126 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" },
1127 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1128 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1129 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" },
1130 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" },
1131 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1132 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" },
1133 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" },
1134 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" },
1135 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" },
1136 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1137 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1138 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" },
1139 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" },
1140 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1141 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1142 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1143 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" },
1144 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" },
1145 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" },
1146 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" },
1147 { "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" },
1148 { "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" },
1149 { "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" },
1150 { "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" },
1151 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" },
1152 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" },
1153
1154 {}
1155 };
1156
1157 static const struct rpm_regulator_data rpm_pm8998_regulators[] = {
1158 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" },
1159 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" },
1160 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
1161 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
1162 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
1163 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" },
1164 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" },
1165 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" },
1166 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" },
1167 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" },
1168 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" },
1169 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" },
1170 { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" },
1171 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" },
1172 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" },
1173 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" },
1174 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" },
1175 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" },
1176 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" },
1177 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1178 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" },
1179 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" },
1180 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" },
1181 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" },
1182 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1183 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" },
1184 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1185 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1186 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" },
1187 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" },
1188 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" },
1189 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" },
1190 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" },
1191 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" },
1192 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" },
1193 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" },
1194 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" },
1195 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" },
1196 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" },
1197 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" },
1198 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" },
1199 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" },
1200 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" },
1201 {}
1202 };
1203
1204 static const struct rpm_regulator_data rpm_pma8084_regulators[] = {
1205 { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" },
1206 { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" },
1207 { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" },
1208 { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" },
1209 { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" },
1210 { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" },
1211 { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" },
1212 { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" },
1213 { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" },
1214 { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" },
1215 { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" },
1216 { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" },
1217
1218 { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" },
1219 { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1220 { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1221 { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1222 { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" },
1223 { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1224 { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" },
1225 { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" },
1226 { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1227 { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1228 { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" },
1229 { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1230 { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1231 { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1232 { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1233 { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" },
1234 { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" },
1235 { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" },
1236 { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" },
1237 { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1238 { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" },
1239 { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" },
1240 { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1241 { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1242 { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" },
1243 { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1244 { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1245
1246 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch },
1247 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch },
1248 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch },
1249 { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch },
1250 { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch },
1251
1252 {}
1253 };
1254
1255 static const struct rpm_regulator_data rpm_pmi8994_regulators[] = {
1256 { "s1", QCOM_SMD_RPM_SMPB, 1, &pmi8994_ftsmps, "vdd_s1" },
1257 { "s2", QCOM_SMD_RPM_SMPB, 2, &pmi8994_hfsmps, "vdd_s2" },
1258 { "s3", QCOM_SMD_RPM_SMPB, 3, &pmi8994_hfsmps, "vdd_s3" },
1259 { "boost-bypass", QCOM_SMD_RPM_BBYB, 1, &pmi8994_bby, "vdd_bst_byp" },
1260 {}
1261 };
1262
1263 static const struct rpm_regulator_data rpm_pmi8998_regulators[] = {
1264 { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" },
1265 {}
1266 };
1267
1268 static const struct rpm_regulator_data rpm_pms405_regulators[] = {
1269 { "s1", QCOM_SMD_RPM_SMPA, 1, &pms405_hfsmps3, "vdd_s1" },
1270 { "s2", QCOM_SMD_RPM_SMPA, 2, &pms405_hfsmps3, "vdd_s2" },
1271 { "s3", QCOM_SMD_RPM_SMPA, 3, &pms405_hfsmps3, "vdd_s3" },
1272 { "s4", QCOM_SMD_RPM_SMPA, 4, &pms405_hfsmps3, "vdd_s4" },
1273 { "s5", QCOM_SMD_RPM_SMPA, 5, &pms405_hfsmps3, "vdd_s5" },
1274 { "l1", QCOM_SMD_RPM_LDOA, 1, &pms405_nldo1200, "vdd_l1_l2" },
1275 { "l2", QCOM_SMD_RPM_LDOA, 2, &pms405_nldo1200, "vdd_l1_l2" },
1276 { "l3", QCOM_SMD_RPM_LDOA, 3, &pms405_nldo1200, "vdd_l3_l8" },
1277 { "l4", QCOM_SMD_RPM_LDOA, 4, &pms405_nldo300, "vdd_l4" },
1278 { "l5", QCOM_SMD_RPM_LDOA, 5, &pms405_pldo600, "vdd_l5_l6" },
1279 { "l6", QCOM_SMD_RPM_LDOA, 6, &pms405_pldo600, "vdd_l5_l6" },
1280 { "l7", QCOM_SMD_RPM_LDOA, 7, &pms405_pldo150, "vdd_l7" },
1281 { "l8", QCOM_SMD_RPM_LDOA, 8, &pms405_nldo1200, "vdd_l3_l8" },
1282 { "l9", QCOM_SMD_RPM_LDOA, 9, &pms405_nldo1200, "vdd_l9" },
1283 { "l10", QCOM_SMD_RPM_LDOA, 10, &pms405_pldo50, "vdd_l10_l11_l12_l13" },
1284 { "l11", QCOM_SMD_RPM_LDOA, 11, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1285 { "l12", QCOM_SMD_RPM_LDOA, 12, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1286 { "l13", QCOM_SMD_RPM_LDOA, 13, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1287 {}
1288 };
1289
1290 static const struct of_device_id rpm_of_match[] = {
1291 { .compatible = "qcom,rpm-mp5496-regulators", .data = &rpm_mp5496_regulators },
1292 { .compatible = "qcom,rpm-pm2250-regulators", .data = &rpm_pm2250_regulators },
1293 { .compatible = "qcom,rpm-pm6125-regulators", .data = &rpm_pm6125_regulators },
1294 { .compatible = "qcom,rpm-pm660-regulators", .data = &rpm_pm660_regulators },
1295 { .compatible = "qcom,rpm-pm660l-regulators", .data = &rpm_pm660l_regulators },
1296 { .compatible = "qcom,rpm-pm8226-regulators", .data = &rpm_pm8226_regulators },
1297 { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators },
1298 { .compatible = "qcom,rpm-pm8909-regulators", .data = &rpm_pm8909_regulators },
1299 { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators },
1300 { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators },
1301 { .compatible = "qcom,rpm-pm8950-regulators", .data = &rpm_pm8950_regulators },
1302 { .compatible = "qcom,rpm-pm8953-regulators", .data = &rpm_pm8953_regulators },
1303 { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators },
1304 { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators },
1305 { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators },
1306 { .compatible = "qcom,rpm-pmi8994-regulators", .data = &rpm_pmi8994_regulators },
1307 { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators },
1308 { .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators },
1309 {}
1310 };
1311 MODULE_DEVICE_TABLE(of, rpm_of_match);
1312
1313 /**
1314 * rpm_regulator_init_vreg() - initialize all attributes of a qcom_smd-regulator
1315 * @vreg: Pointer to the individual qcom_smd-regulator resource
1316 * @dev: Pointer to the top level qcom_smd-regulator PMIC device
1317 * @node: Pointer to the individual qcom_smd-regulator resource
1318 * device node
1319 * @rpm: Pointer to the rpm bus node
1320 * @pmic_rpm_data: Pointer to a null-terminated array of qcom_smd-regulator
1321 * resources defined for the top level PMIC device
1322 *
1323 * Return: 0 on success, errno on failure
1324 */
rpm_regulator_init_vreg(struct qcom_rpm_reg * vreg,struct device * dev,struct device_node * node,struct qcom_smd_rpm * rpm,const struct rpm_regulator_data * pmic_rpm_data)1325 static int rpm_regulator_init_vreg(struct qcom_rpm_reg *vreg, struct device *dev,
1326 struct device_node *node, struct qcom_smd_rpm *rpm,
1327 const struct rpm_regulator_data *pmic_rpm_data)
1328 {
1329 struct regulator_config config = {};
1330 const struct rpm_regulator_data *rpm_data;
1331 struct regulator_dev *rdev;
1332 int ret;
1333
1334 for (rpm_data = pmic_rpm_data; rpm_data->name; rpm_data++)
1335 if (of_node_name_eq(node, rpm_data->name))
1336 break;
1337
1338 if (!rpm_data->name) {
1339 dev_err(dev, "Unknown regulator %pOFn\n", node);
1340 return -EINVAL;
1341 }
1342
1343 vreg->dev = dev;
1344 vreg->rpm = rpm;
1345 vreg->type = rpm_data->type;
1346 vreg->id = rpm_data->id;
1347
1348 memcpy(&vreg->desc, rpm_data->desc, sizeof(vreg->desc));
1349 vreg->desc.name = rpm_data->name;
1350 vreg->desc.supply_name = rpm_data->supply;
1351 vreg->desc.owner = THIS_MODULE;
1352 vreg->desc.type = REGULATOR_VOLTAGE;
1353 vreg->desc.of_match = rpm_data->name;
1354
1355 config.dev = dev;
1356 config.of_node = node;
1357 config.driver_data = vreg;
1358
1359 rdev = devm_regulator_register(dev, &vreg->desc, &config);
1360 if (IS_ERR(rdev)) {
1361 ret = PTR_ERR(rdev);
1362 dev_err(dev, "%pOFn: devm_regulator_register() failed, ret=%d\n", node, ret);
1363 return ret;
1364 }
1365
1366 return 0;
1367 }
1368
rpm_reg_probe(struct platform_device * pdev)1369 static int rpm_reg_probe(struct platform_device *pdev)
1370 {
1371 struct device *dev = &pdev->dev;
1372 const struct rpm_regulator_data *vreg_data;
1373 struct device_node *node;
1374 struct qcom_rpm_reg *vreg;
1375 struct qcom_smd_rpm *rpm;
1376 int ret;
1377
1378 rpm = dev_get_drvdata(pdev->dev.parent);
1379 if (!rpm) {
1380 dev_err(&pdev->dev, "Unable to retrieve handle to rpm\n");
1381 return -ENODEV;
1382 }
1383
1384 vreg_data = of_device_get_match_data(dev);
1385 if (!vreg_data)
1386 return -ENODEV;
1387
1388 for_each_available_child_of_node(dev->of_node, node) {
1389 vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
1390 if (!vreg) {
1391 of_node_put(node);
1392 return -ENOMEM;
1393 }
1394
1395 ret = rpm_regulator_init_vreg(vreg, dev, node, rpm, vreg_data);
1396
1397 if (ret < 0) {
1398 of_node_put(node);
1399 return ret;
1400 }
1401 }
1402
1403 return 0;
1404 }
1405
1406 static struct platform_driver rpm_reg_driver = {
1407 .probe = rpm_reg_probe,
1408 .driver = {
1409 .name = "qcom_rpm_smd_regulator",
1410 .of_match_table = rpm_of_match,
1411 },
1412 };
1413
rpm_reg_init(void)1414 static int __init rpm_reg_init(void)
1415 {
1416 return platform_driver_register(&rpm_reg_driver);
1417 }
1418 subsys_initcall(rpm_reg_init);
1419
rpm_reg_exit(void)1420 static void __exit rpm_reg_exit(void)
1421 {
1422 platform_driver_unregister(&rpm_reg_driver);
1423 }
1424 module_exit(rpm_reg_exit)
1425
1426 MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
1427 MODULE_LICENSE("GPL v2");
1428