1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Intel Gemini Lake SoC pinctrl/GPIO driver
4  *
5  * Copyright (C) 2017 Intel Corporation
6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7  */
8 
9 #include <linux/mod_devicetable.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 
13 #include <linux/pinctrl/pinctrl.h>
14 
15 #include "pinctrl-intel.h"
16 
17 #define GLK_PAD_OWN	0x020
18 #define GLK_PADCFGLOCK	0x080
19 #define GLK_HOSTSW_OWN	0x0b0
20 #define GLK_GPI_IS	0x100
21 #define GLK_GPI_IE	0x110
22 
23 #define GLK_COMMUNITY(s, e)				\
24 	{						\
25 		.padown_offset = GLK_PAD_OWN,		\
26 		.padcfglock_offset = GLK_PADCFGLOCK,	\
27 		.hostown_offset = GLK_HOSTSW_OWN,	\
28 		.is_offset = GLK_GPI_IS,		\
29 		.ie_offset = GLK_GPI_IE,		\
30 		.gpp_size = 32,                         \
31 		.pin_base = (s),			\
32 		.npins = ((e) - (s) + 1),		\
33 	}
34 
35 /* GLK */
36 static const struct pinctrl_pin_desc glk_northwest_pins[] = {
37 	PINCTRL_PIN(0, "TCK"),
38 	PINCTRL_PIN(1, "TRST_B"),
39 	PINCTRL_PIN(2, "TMS"),
40 	PINCTRL_PIN(3, "TDI"),
41 	PINCTRL_PIN(4, "TDO"),
42 	PINCTRL_PIN(5, "JTAGX"),
43 	PINCTRL_PIN(6, "CX_PREQ_B"),
44 	PINCTRL_PIN(7, "CX_PRDY_B"),
45 	PINCTRL_PIN(8, "GPIO_8"),
46 	PINCTRL_PIN(9, "GPIO_9"),
47 	PINCTRL_PIN(10, "GPIO_10"),
48 	PINCTRL_PIN(11, "GPIO_11"),
49 	PINCTRL_PIN(12, "GPIO_12"),
50 	PINCTRL_PIN(13, "GPIO_13"),
51 	PINCTRL_PIN(14, "GPIO_14"),
52 	PINCTRL_PIN(15, "GPIO_15"),
53 	PINCTRL_PIN(16, "GPIO_16"),
54 	PINCTRL_PIN(17, "GPIO_17"),
55 	PINCTRL_PIN(18, "GPIO_18"),
56 	PINCTRL_PIN(19, "GPIO_19"),
57 	PINCTRL_PIN(20, "GPIO_20"),
58 	PINCTRL_PIN(21, "GPIO_21"),
59 	PINCTRL_PIN(22, "GPIO_22"),
60 	PINCTRL_PIN(23, "GPIO_23"),
61 	PINCTRL_PIN(24, "GPIO_24"),
62 	PINCTRL_PIN(25, "GPIO_25"),
63 	PINCTRL_PIN(26, "ISH_GPIO_0"),
64 	PINCTRL_PIN(27, "ISH_GPIO_1"),
65 	PINCTRL_PIN(28, "ISH_GPIO_2"),
66 	PINCTRL_PIN(29, "ISH_GPIO_3"),
67 	PINCTRL_PIN(30, "ISH_GPIO_4"),
68 	PINCTRL_PIN(31, "ISH_GPIO_5"),
69 	PINCTRL_PIN(32, "ISH_GPIO_6"),
70 	PINCTRL_PIN(33, "ISH_GPIO_7"),
71 	PINCTRL_PIN(34, "ISH_GPIO_8"),
72 	PINCTRL_PIN(35, "ISH_GPIO_9"),
73 	PINCTRL_PIN(36, "GPIO_36"),
74 	PINCTRL_PIN(37, "GPIO_37"),
75 	PINCTRL_PIN(38, "GPIO_38"),
76 	PINCTRL_PIN(39, "GPIO_39"),
77 	PINCTRL_PIN(40, "GPIO_40"),
78 	PINCTRL_PIN(41, "GPIO_41"),
79 	PINCTRL_PIN(42, "GP_INTD_DSI_TE1"),
80 	PINCTRL_PIN(43, "GP_INTD_DSI_TE2"),
81 	PINCTRL_PIN(44, "USB_OC0_B"),
82 	PINCTRL_PIN(45, "USB_OC1_B"),
83 	PINCTRL_PIN(46, "DSI_I2C_SDA"),
84 	PINCTRL_PIN(47, "DSI_I2C_SCL"),
85 	PINCTRL_PIN(48, "PMC_I2C_SDA"),
86 	PINCTRL_PIN(49, "PMC_I2C_SCL"),
87 	PINCTRL_PIN(50, "LPSS_I2C0_SDA"),
88 	PINCTRL_PIN(51, "LPSS_I2C0_SCL"),
89 	PINCTRL_PIN(52, "LPSS_I2C1_SDA"),
90 	PINCTRL_PIN(53, "LPSS_I2C1_SCL"),
91 	PINCTRL_PIN(54, "LPSS_I2C2_SDA"),
92 	PINCTRL_PIN(55, "LPSS_I2C2_SCL"),
93 	PINCTRL_PIN(56, "LPSS_I2C3_SDA"),
94 	PINCTRL_PIN(57, "LPSS_I2C3_SCL"),
95 	PINCTRL_PIN(58, "LPSS_I2C4_SDA"),
96 	PINCTRL_PIN(59, "LPSS_I2C4_SCL"),
97 	PINCTRL_PIN(60, "LPSS_UART0_RXD"),
98 	PINCTRL_PIN(61, "LPSS_UART0_TXD"),
99 	PINCTRL_PIN(62, "LPSS_UART0_RTS_B"),
100 	PINCTRL_PIN(63, "LPSS_UART0_CTS_B"),
101 	PINCTRL_PIN(64, "LPSS_UART2_RXD"),
102 	PINCTRL_PIN(65, "LPSS_UART2_TXD"),
103 	PINCTRL_PIN(66, "LPSS_UART2_RTS_B"),
104 	PINCTRL_PIN(67, "LPSS_UART2_CTS_B"),
105 	PINCTRL_PIN(68, "PMC_SPI_FS0"),
106 	PINCTRL_PIN(69, "PMC_SPI_FS1"),
107 	PINCTRL_PIN(70, "PMC_SPI_FS2"),
108 	PINCTRL_PIN(71, "PMC_SPI_RXD"),
109 	PINCTRL_PIN(72, "PMC_SPI_TXD"),
110 	PINCTRL_PIN(73, "PMC_SPI_CLK"),
111 	PINCTRL_PIN(74, "THERMTRIP_B"),
112 	PINCTRL_PIN(75, "PROCHOT_B"),
113 	PINCTRL_PIN(76, "EMMC_RST_B"),
114 	PINCTRL_PIN(77, "GPIO_212"),
115 	PINCTRL_PIN(78, "GPIO_213"),
116 	PINCTRL_PIN(79, "GPIO_214"),
117 };
118 
119 static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 };
120 static const unsigned int glk_northwest_pwm0_pins[] = { 42 };
121 static const unsigned int glk_northwest_pwm1_pins[] = { 43 };
122 static const unsigned int glk_northwest_pwm2_pins[] = { 44 };
123 static const unsigned int glk_northwest_pwm3_pins[] = { 45 };
124 static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 };
125 static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 };
126 static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 };
127 static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 };
128 static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 };
129 static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 };
130 static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 };
131 
132 static const struct intel_pingroup glk_northwest_groups[] = {
133 	PIN_GROUP("uart1_grp", glk_northwest_uart1_pins, 2),
134 	PIN_GROUP("pwm0_grp", glk_northwest_pwm0_pins, 2),
135 	PIN_GROUP("pwm1_grp", glk_northwest_pwm1_pins, 2),
136 	PIN_GROUP("pwm2_grp", glk_northwest_pwm2_pins, 2),
137 	PIN_GROUP("pwm3_grp", glk_northwest_pwm3_pins, 2),
138 	PIN_GROUP("i2c0_grp", glk_northwest_i2c0_pins, 1),
139 	PIN_GROUP("i2c1_grp", glk_northwest_i2c1_pins, 1),
140 	PIN_GROUP("i2c2_grp", glk_northwest_i2c2_pins, 1),
141 	PIN_GROUP("i2c3_grp", glk_northwest_i2c3_pins, 1),
142 	PIN_GROUP("i2c4_grp", glk_northwest_i2c4_pins, 1),
143 	PIN_GROUP("uart0_grp", glk_northwest_uart0_pins, 1),
144 	PIN_GROUP("uart2_grp", glk_northwest_uart2_pins, 1),
145 };
146 
147 static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" };
148 static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" };
149 static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" };
150 static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" };
151 static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" };
152 static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" };
153 static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" };
154 static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" };
155 static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" };
156 static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" };
157 static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" };
158 static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" };
159 
160 static const struct intel_function glk_northwest_functions[] = {
161 	FUNCTION("uart1", glk_northwest_uart1_groups),
162 	FUNCTION("pmw0", glk_northwest_pwm0_groups),
163 	FUNCTION("pmw1", glk_northwest_pwm1_groups),
164 	FUNCTION("pmw2", glk_northwest_pwm2_groups),
165 	FUNCTION("pmw3", glk_northwest_pwm3_groups),
166 	FUNCTION("i2c0", glk_northwest_i2c0_groups),
167 	FUNCTION("i2c1", glk_northwest_i2c1_groups),
168 	FUNCTION("i2c2", glk_northwest_i2c2_groups),
169 	FUNCTION("i2c3", glk_northwest_i2c3_groups),
170 	FUNCTION("i2c4", glk_northwest_i2c4_groups),
171 	FUNCTION("uart0", glk_northwest_uart0_groups),
172 	FUNCTION("uart2", glk_northwest_uart2_groups),
173 };
174 
175 static const struct intel_community glk_northwest_communities[] = {
176 	GLK_COMMUNITY(0, 79),
177 };
178 
179 static const struct intel_pinctrl_soc_data glk_northwest_soc_data = {
180 	.uid = "1",
181 	.pins = glk_northwest_pins,
182 	.npins = ARRAY_SIZE(glk_northwest_pins),
183 	.groups = glk_northwest_groups,
184 	.ngroups = ARRAY_SIZE(glk_northwest_groups),
185 	.functions = glk_northwest_functions,
186 	.nfunctions = ARRAY_SIZE(glk_northwest_functions),
187 	.communities = glk_northwest_communities,
188 	.ncommunities = ARRAY_SIZE(glk_northwest_communities),
189 };
190 
191 static const struct pinctrl_pin_desc glk_north_pins[] = {
192 	PINCTRL_PIN(0, "SVID0_ALERT_B"),
193 	PINCTRL_PIN(1, "SVID0_DATA"),
194 	PINCTRL_PIN(2, "SVID0_CLK"),
195 	PINCTRL_PIN(3, "LPSS_SPI_0_CLK"),
196 	PINCTRL_PIN(4, "LPSS_SPI_0_FS0"),
197 	PINCTRL_PIN(5, "LPSS_SPI_0_FS1"),
198 	PINCTRL_PIN(6, "LPSS_SPI_0_RXD"),
199 	PINCTRL_PIN(7, "LPSS_SPI_0_TXD"),
200 	PINCTRL_PIN(8, "LPSS_SPI_2_CLK"),
201 	PINCTRL_PIN(9, "LPSS_SPI_2_FS0"),
202 	PINCTRL_PIN(10, "LPSS_SPI_2_FS1"),
203 	PINCTRL_PIN(11, "LPSS_SPI_2_FS2"),
204 	PINCTRL_PIN(12, "LPSS_SPI_2_RXD"),
205 	PINCTRL_PIN(13, "LPSS_SPI_2_TXD"),
206 	PINCTRL_PIN(14, "FST_SPI_CS0_B"),
207 	PINCTRL_PIN(15, "FST_SPI_CS1_B"),
208 	PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"),
209 	PINCTRL_PIN(17, "FST_SPI_MISO_IO1"),
210 	PINCTRL_PIN(18, "FST_SPI_IO2"),
211 	PINCTRL_PIN(19, "FST_SPI_IO3"),
212 	PINCTRL_PIN(20, "FST_SPI_CLK"),
213 	PINCTRL_PIN(21, "FST_SPI_CLK_FB"),
214 	PINCTRL_PIN(22, "PMU_PLTRST_B"),
215 	PINCTRL_PIN(23, "PMU_PWRBTN_B"),
216 	PINCTRL_PIN(24, "PMU_SLP_S0_B"),
217 	PINCTRL_PIN(25, "PMU_SLP_S3_B"),
218 	PINCTRL_PIN(26, "PMU_SLP_S4_B"),
219 	PINCTRL_PIN(27, "SUSPWRDNACK"),
220 	PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B"),
221 	PINCTRL_PIN(29, "GPIO_105"),
222 	PINCTRL_PIN(30, "PMU_BATLOW_B"),
223 	PINCTRL_PIN(31, "PMU_RESETBUTTON_B"),
224 	PINCTRL_PIN(32, "PMU_SUSCLK"),
225 	PINCTRL_PIN(33, "SUS_STAT_B"),
226 	PINCTRL_PIN(34, "LPSS_I2C5_SDA"),
227 	PINCTRL_PIN(35, "LPSS_I2C5_SCL"),
228 	PINCTRL_PIN(36, "LPSS_I2C6_SDA"),
229 	PINCTRL_PIN(37, "LPSS_I2C6_SCL"),
230 	PINCTRL_PIN(38, "LPSS_I2C7_SDA"),
231 	PINCTRL_PIN(39, "LPSS_I2C7_SCL"),
232 	PINCTRL_PIN(40, "PCIE_WAKE0_B"),
233 	PINCTRL_PIN(41, "PCIE_WAKE1_B"),
234 	PINCTRL_PIN(42, "PCIE_WAKE2_B"),
235 	PINCTRL_PIN(43, "PCIE_WAKE3_B"),
236 	PINCTRL_PIN(44, "PCIE_CLKREQ0_B"),
237 	PINCTRL_PIN(45, "PCIE_CLKREQ1_B"),
238 	PINCTRL_PIN(46, "PCIE_CLKREQ2_B"),
239 	PINCTRL_PIN(47, "PCIE_CLKREQ3_B"),
240 	PINCTRL_PIN(48, "HV_DDI0_DDC_SDA"),
241 	PINCTRL_PIN(49, "HV_DDI0_DDC_SCL"),
242 	PINCTRL_PIN(50, "HV_DDI1_DDC_SDA"),
243 	PINCTRL_PIN(51, "HV_DDI1_DDC_SCL"),
244 	PINCTRL_PIN(52, "PANEL0_VDDEN"),
245 	PINCTRL_PIN(53, "PANEL0_BKLTEN"),
246 	PINCTRL_PIN(54, "PANEL0_BKLTCTL"),
247 	PINCTRL_PIN(55, "HV_DDI0_HPD"),
248 	PINCTRL_PIN(56, "HV_DDI1_HPD"),
249 	PINCTRL_PIN(57, "HV_EDP_HPD"),
250 	PINCTRL_PIN(58, "GPIO_134"),
251 	PINCTRL_PIN(59, "GPIO_135"),
252 	PINCTRL_PIN(60, "GPIO_136"),
253 	PINCTRL_PIN(61, "GPIO_137"),
254 	PINCTRL_PIN(62, "GPIO_138"),
255 	PINCTRL_PIN(63, "GPIO_139"),
256 	PINCTRL_PIN(64, "GPIO_140"),
257 	PINCTRL_PIN(65, "GPIO_141"),
258 	PINCTRL_PIN(66, "GPIO_142"),
259 	PINCTRL_PIN(67, "GPIO_143"),
260 	PINCTRL_PIN(68, "GPIO_144"),
261 	PINCTRL_PIN(69, "GPIO_145"),
262 	PINCTRL_PIN(70, "GPIO_146"),
263 	PINCTRL_PIN(71, "LPC_ILB_SERIRQ"),
264 	PINCTRL_PIN(72, "LPC_CLKOUT0"),
265 	PINCTRL_PIN(73, "LPC_CLKOUT1"),
266 	PINCTRL_PIN(74, "LPC_AD0"),
267 	PINCTRL_PIN(75, "LPC_AD1"),
268 	PINCTRL_PIN(76, "LPC_AD2"),
269 	PINCTRL_PIN(77, "LPC_AD3"),
270 	PINCTRL_PIN(78, "LPC_CLKRUNB"),
271 	PINCTRL_PIN(79, "LPC_FRAMEB"),
272 };
273 
274 static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 };
275 static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 };
276 static const unsigned int glk_north_i2c5_pins[] = { 34, 35 };
277 static const unsigned int glk_north_i2c6_pins[] = { 36, 37 };
278 static const unsigned int glk_north_i2c7_pins[] = { 38, 39 };
279 static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 };
280 static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 };
281 
282 static const struct intel_pingroup glk_north_groups[] = {
283 	PIN_GROUP("spi0_grp", glk_north_spi0_pins, 1),
284 	PIN_GROUP("spi1_grp", glk_north_spi1_pins, 1),
285 	PIN_GROUP("i2c5_grp", glk_north_i2c5_pins, 1),
286 	PIN_GROUP("i2c6_grp", glk_north_i2c6_pins, 1),
287 	PIN_GROUP("i2c7_grp", glk_north_i2c7_pins, 1),
288 	PIN_GROUP("uart0_grp", glk_north_uart0_pins, 2),
289 	PIN_GROUP("spi0b_grp", glk_north_spi0b_pins, 2),
290 };
291 
292 static const char * const glk_north_spi0_groups[] = { "spi0_grp", "spi0b_grp" };
293 static const char * const glk_north_spi1_groups[] = { "spi1_grp" };
294 static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" };
295 static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" };
296 static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" };
297 static const char * const glk_north_uart0_groups[] = { "uart0_grp" };
298 
299 static const struct intel_function glk_north_functions[] = {
300 	FUNCTION("spi0", glk_north_spi0_groups),
301 	FUNCTION("spi1", glk_north_spi1_groups),
302 	FUNCTION("i2c5", glk_north_i2c5_groups),
303 	FUNCTION("i2c6", glk_north_i2c6_groups),
304 	FUNCTION("i2c7", glk_north_i2c7_groups),
305 	FUNCTION("uart0", glk_north_uart0_groups),
306 };
307 
308 static const struct intel_community glk_north_communities[] = {
309 	GLK_COMMUNITY(0, 79),
310 };
311 
312 static const struct intel_pinctrl_soc_data glk_north_soc_data = {
313 	.uid = "2",
314 	.pins = glk_north_pins,
315 	.npins = ARRAY_SIZE(glk_north_pins),
316 	.groups = glk_north_groups,
317 	.ngroups = ARRAY_SIZE(glk_north_groups),
318 	.functions = glk_north_functions,
319 	.nfunctions = ARRAY_SIZE(glk_north_functions),
320 	.communities = glk_north_communities,
321 	.ncommunities = ARRAY_SIZE(glk_north_communities),
322 };
323 
324 static const struct pinctrl_pin_desc glk_audio_pins[] = {
325 	PINCTRL_PIN(0, "AVS_I2S0_MCLK"),
326 	PINCTRL_PIN(1, "AVS_I2S0_BCLK"),
327 	PINCTRL_PIN(2, "AVS_I2S0_WS_SYNC"),
328 	PINCTRL_PIN(3, "AVS_I2S0_SDI"),
329 	PINCTRL_PIN(4, "AVS_I2S0_SDO"),
330 	PINCTRL_PIN(5, "AVS_I2S1_MCLK"),
331 	PINCTRL_PIN(6, "AVS_I2S1_BCLK"),
332 	PINCTRL_PIN(7, "AVS_I2S1_WS_SYNC"),
333 	PINCTRL_PIN(8, "AVS_I2S1_SDI"),
334 	PINCTRL_PIN(9, "AVS_I2S1_SDO"),
335 	PINCTRL_PIN(10, "AVS_HDA_BCLK"),
336 	PINCTRL_PIN(11, "AVS_HDA_WS_SYNC"),
337 	PINCTRL_PIN(12, "AVS_HDA_SDI"),
338 	PINCTRL_PIN(13, "AVS_HDA_SDO"),
339 	PINCTRL_PIN(14, "AVS_HDA_RSTB"),
340 	PINCTRL_PIN(15, "AVS_M_CLK_A1"),
341 	PINCTRL_PIN(16, "AVS_M_CLK_B1"),
342 	PINCTRL_PIN(17, "AVS_M_DATA_1"),
343 	PINCTRL_PIN(18, "AVS_M_CLK_AB2"),
344 	PINCTRL_PIN(19, "AVS_M_DATA_2"),
345 };
346 
347 static const struct intel_community glk_audio_communities[] = {
348 	GLK_COMMUNITY(0, 19),
349 };
350 
351 static const struct intel_pinctrl_soc_data glk_audio_soc_data = {
352 	.uid = "3",
353 	.pins = glk_audio_pins,
354 	.npins = ARRAY_SIZE(glk_audio_pins),
355 	.communities = glk_audio_communities,
356 	.ncommunities = ARRAY_SIZE(glk_audio_communities),
357 };
358 
359 static const struct pinctrl_pin_desc glk_scc_pins[] = {
360 	PINCTRL_PIN(0, "SMB_ALERTB"),
361 	PINCTRL_PIN(1, "SMB_CLK"),
362 	PINCTRL_PIN(2, "SMB_DATA"),
363 	PINCTRL_PIN(3, "SDCARD_LVL_WP"),
364 	PINCTRL_PIN(4, "SDCARD_CLK"),
365 	PINCTRL_PIN(5, "SDCARD_CLK_FB"),
366 	PINCTRL_PIN(6, "SDCARD_D0"),
367 	PINCTRL_PIN(7, "SDCARD_D1"),
368 	PINCTRL_PIN(8, "SDCARD_D2"),
369 	PINCTRL_PIN(9, "SDCARD_D3"),
370 	PINCTRL_PIN(10, "SDCARD_CMD"),
371 	PINCTRL_PIN(11, "SDCARD_CD_B"),
372 	PINCTRL_PIN(12, "SDCARD_PWR_DOWN_B"),
373 	PINCTRL_PIN(13, "GPIO_210"),
374 	PINCTRL_PIN(14, "OSC_CLK_OUT_0"),
375 	PINCTRL_PIN(15, "OSC_CLK_OUT_1"),
376 	PINCTRL_PIN(16, "CNV_BRI_DT"),
377 	PINCTRL_PIN(17, "CNV_BRI_RSP"),
378 	PINCTRL_PIN(18, "CNV_RGI_DT"),
379 	PINCTRL_PIN(19, "CNV_RGI_RSP"),
380 	PINCTRL_PIN(20, "CNV_RF_RESET_B"),
381 	PINCTRL_PIN(21, "XTAL_CLKREQ"),
382 	PINCTRL_PIN(22, "SDIO_CLK_FB"),
383 	PINCTRL_PIN(23, "EMMC0_CLK"),
384 	PINCTRL_PIN(24, "EMMC0_CLK_FB"),
385 	PINCTRL_PIN(25, "EMMC0_D0"),
386 	PINCTRL_PIN(26, "EMMC0_D1"),
387 	PINCTRL_PIN(27, "EMMC0_D2"),
388 	PINCTRL_PIN(28, "EMMC0_D3"),
389 	PINCTRL_PIN(29, "EMMC0_D4"),
390 	PINCTRL_PIN(30, "EMMC0_D5"),
391 	PINCTRL_PIN(31, "EMMC0_D6"),
392 	PINCTRL_PIN(32, "EMMC0_D7"),
393 	PINCTRL_PIN(33, "EMMC0_CMD"),
394 	PINCTRL_PIN(34, "EMMC0_STROBE"),
395 };
396 
397 static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 };
398 static const unsigned int glk_scc_sdcard_pins[] = {
399 	3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
400 };
401 static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 };
402 static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 };
403 static const unsigned int glk_scc_emmc_pins[] = {
404 	23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
405 };
406 
407 static const struct intel_pingroup glk_scc_groups[] = {
408 	PIN_GROUP("i2c7_grp", glk_scc_i2c7_pins, 2),
409 	PIN_GROUP("sdcard_grp", glk_scc_sdcard_pins, 1),
410 	PIN_GROUP("sdio_grp", glk_scc_sdio_pins, 2),
411 	PIN_GROUP("uart1_grp", glk_scc_uart1_pins, 3),
412 	PIN_GROUP("emmc_grp", glk_scc_emmc_pins, 1),
413 };
414 
415 static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" };
416 static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" };
417 static const char * const glk_scc_sdio_groups[] = { "sdio_grp" };
418 static const char * const glk_scc_uart1_groups[] = { "uart1_grp" };
419 static const char * const glk_scc_emmc_groups[] = { "emmc_grp" };
420 
421 static const struct intel_function glk_scc_functions[] = {
422 	FUNCTION("i2c7", glk_scc_i2c7_groups),
423 	FUNCTION("sdcard", glk_scc_sdcard_groups),
424 	FUNCTION("sdio", glk_scc_sdio_groups),
425 	FUNCTION("uart1", glk_scc_uart1_groups),
426 	FUNCTION("emmc", glk_scc_emmc_groups),
427 };
428 
429 static const struct intel_community glk_scc_communities[] = {
430 	GLK_COMMUNITY(0, 34),
431 };
432 
433 static const struct intel_pinctrl_soc_data glk_scc_soc_data = {
434 	.uid = "4",
435 	.pins = glk_scc_pins,
436 	.npins = ARRAY_SIZE(glk_scc_pins),
437 	.groups = glk_scc_groups,
438 	.ngroups = ARRAY_SIZE(glk_scc_groups),
439 	.functions = glk_scc_functions,
440 	.nfunctions = ARRAY_SIZE(glk_scc_functions),
441 	.communities = glk_scc_communities,
442 	.ncommunities = ARRAY_SIZE(glk_scc_communities),
443 };
444 
445 static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {
446 	&glk_northwest_soc_data,
447 	&glk_north_soc_data,
448 	&glk_audio_soc_data,
449 	&glk_scc_soc_data,
450 	NULL
451 };
452 
453 static const struct acpi_device_id glk_pinctrl_acpi_match[] = {
454 	{ "INT3453", (kernel_ulong_t)glk_pinctrl_soc_data },
455 	{ }
456 };
457 MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match);
458 
459 static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops);
460 
461 static struct platform_driver glk_pinctrl_driver = {
462 	.probe = intel_pinctrl_probe_by_uid,
463 	.driver = {
464 		.name = "geminilake-pinctrl",
465 		.acpi_match_table = glk_pinctrl_acpi_match,
466 		.pm = &glk_pinctrl_pm_ops,
467 	},
468 };
469 
glk_pinctrl_init(void)470 static int __init glk_pinctrl_init(void)
471 {
472 	return platform_driver_register(&glk_pinctrl_driver);
473 }
474 subsys_initcall(glk_pinctrl_init);
475 
glk_pinctrl_exit(void)476 static void __exit glk_pinctrl_exit(void)
477 {
478 	platform_driver_unregister(&glk_pinctrl_driver);
479 }
480 module_exit(glk_pinctrl_exit);
481 
482 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
483 MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver");
484 MODULE_LICENSE("GPL v2");
485