1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Wrapper driver for SERDES used in J721E
4 *
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
11 #include <linux/slab.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/gpio.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mux/consumer.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/reset-controller.h>
26
27 #define REF_CLK_19_2MHZ 19200000
28 #define REF_CLK_25MHZ 25000000
29 #define REF_CLK_100MHZ 100000000
30 #define REF_CLK_156_25MHZ 156250000
31
32 /* SCM offsets */
33 #define SERDES_SUP_CTRL 0x4400
34
35 /* SERDES offsets */
36 #define WIZ_SERDES_CTRL 0x404
37 #define WIZ_SERDES_TOP_CTRL 0x408
38 #define WIZ_SERDES_RST 0x40c
39 #define WIZ_SERDES_TYPEC 0x410
40 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
41 #define WIZ_LANEDIV(n) (0x484 + (0x40 * (n)))
42
43 #define WIZ_MAX_INPUT_CLOCKS 4
44 /* To include mux clocks, divider clocks and gate clocks */
45 #define WIZ_MAX_OUTPUT_CLOCKS 32
46
47 #define WIZ_MAX_LANES 4
48 #define WIZ_MUX_NUM_CLOCKS 3
49 #define WIZ_DIV_NUM_CLOCKS_16G 2
50 #define WIZ_DIV_NUM_CLOCKS_10G 1
51
52 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
53
54 enum wiz_lane_standard_mode {
55 LANE_MODE_GEN1,
56 LANE_MODE_GEN2,
57 LANE_MODE_GEN3,
58 LANE_MODE_GEN4,
59 };
60
61 enum wiz_refclk_mux_sel {
62 PLL0_REFCLK,
63 PLL1_REFCLK,
64 REFCLK_DIG,
65 };
66
67 enum wiz_refclk_div_sel {
68 CMN_REFCLK_DIG_DIV,
69 CMN_REFCLK1_DIG_DIV,
70 };
71
72 enum wiz_clock_input {
73 WIZ_CORE_REFCLK,
74 WIZ_EXT_REFCLK,
75 WIZ_CORE_REFCLK1,
76 WIZ_EXT_REFCLK1,
77 };
78
79 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
80 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
81 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30);
82 static const struct reg_field pll1_refclk_mux_sel =
83 REG_FIELD(WIZ_SERDES_RST, 29, 29);
84 static const struct reg_field pll0_refclk_mux_sel =
85 REG_FIELD(WIZ_SERDES_RST, 28, 28);
86 static const struct reg_field refclk_dig_sel_16g =
87 REG_FIELD(WIZ_SERDES_RST, 24, 25);
88 static const struct reg_field refclk_dig_sel_10g =
89 REG_FIELD(WIZ_SERDES_RST, 24, 24);
90 static const struct reg_field pma_cmn_refclk_int_mode =
91 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
92 static const struct reg_field pma_cmn_refclk_mode =
93 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
94 static const struct reg_field pma_cmn_refclk_dig_div =
95 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
96 static const struct reg_field pma_cmn_refclk1_dig_div =
97 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
98
99 static const struct reg_field sup_pll0_refclk_mux_sel =
100 REG_FIELD(SERDES_SUP_CTRL, 0, 1);
101 static const struct reg_field sup_pll1_refclk_mux_sel =
102 REG_FIELD(SERDES_SUP_CTRL, 2, 3);
103 static const struct reg_field sup_pma_cmn_refclk1_int_mode =
104 REG_FIELD(SERDES_SUP_CTRL, 4, 5);
105 static const struct reg_field sup_refclk_dig_sel_10g =
106 REG_FIELD(SERDES_SUP_CTRL, 6, 7);
107 static const struct reg_field sup_legacy_clk_override =
108 REG_FIELD(SERDES_SUP_CTRL, 8, 8);
109
110 static const char * const output_clk_names[] = {
111 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
112 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
113 [TI_WIZ_REFCLK_DIG] = "refclk-dig",
114 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
115 };
116
117 static const struct reg_field p_enable[WIZ_MAX_LANES] = {
118 REG_FIELD(WIZ_LANECTL(0), 30, 31),
119 REG_FIELD(WIZ_LANECTL(1), 30, 31),
120 REG_FIELD(WIZ_LANECTL(2), 30, 31),
121 REG_FIELD(WIZ_LANECTL(3), 30, 31),
122 };
123
124 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
125
126 static const struct reg_field p_align[WIZ_MAX_LANES] = {
127 REG_FIELD(WIZ_LANECTL(0), 29, 29),
128 REG_FIELD(WIZ_LANECTL(1), 29, 29),
129 REG_FIELD(WIZ_LANECTL(2), 29, 29),
130 REG_FIELD(WIZ_LANECTL(3), 29, 29),
131 };
132
133 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
134 REG_FIELD(WIZ_LANECTL(0), 28, 28),
135 REG_FIELD(WIZ_LANECTL(1), 28, 28),
136 REG_FIELD(WIZ_LANECTL(2), 28, 28),
137 REG_FIELD(WIZ_LANECTL(3), 28, 28),
138 };
139
140 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
141 REG_FIELD(WIZ_LANECTL(0), 24, 25),
142 REG_FIELD(WIZ_LANECTL(1), 24, 25),
143 REG_FIELD(WIZ_LANECTL(2), 24, 25),
144 REG_FIELD(WIZ_LANECTL(3), 24, 25),
145 };
146
147 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
148 REG_FIELD(WIZ_LANECTL(0), 22, 23),
149 REG_FIELD(WIZ_LANECTL(1), 22, 23),
150 REG_FIELD(WIZ_LANECTL(2), 22, 23),
151 REG_FIELD(WIZ_LANECTL(3), 22, 23),
152 };
153
154 static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = {
155 REG_FIELD(WIZ_LANECTL(0), 20, 21),
156 REG_FIELD(WIZ_LANECTL(1), 20, 21),
157 REG_FIELD(WIZ_LANECTL(2), 20, 21),
158 REG_FIELD(WIZ_LANECTL(3), 20, 21),
159 };
160
161 static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = {
162 REG_FIELD(WIZ_LANECTL(0), 6, 7),
163 REG_FIELD(WIZ_LANECTL(1), 6, 7),
164 REG_FIELD(WIZ_LANECTL(2), 6, 7),
165 REG_FIELD(WIZ_LANECTL(3), 6, 7),
166 };
167
168 static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = {
169 REG_FIELD(WIZ_LANECTL(0), 18, 19),
170 REG_FIELD(WIZ_LANECTL(1), 18, 19),
171 REG_FIELD(WIZ_LANECTL(2), 18, 19),
172 REG_FIELD(WIZ_LANECTL(3), 18, 19),
173 };
174 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
175 REG_FIELD(WIZ_LANEDIV(0), 16, 22),
176 REG_FIELD(WIZ_LANEDIV(1), 16, 22),
177 REG_FIELD(WIZ_LANEDIV(2), 16, 22),
178 REG_FIELD(WIZ_LANEDIV(3), 16, 22),
179 };
180
181 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
182 REG_FIELD(WIZ_LANEDIV(0), 0, 8),
183 REG_FIELD(WIZ_LANEDIV(1), 0, 8),
184 REG_FIELD(WIZ_LANEDIV(2), 0, 8),
185 REG_FIELD(WIZ_LANEDIV(3), 0, 8),
186 };
187
188 static const struct reg_field typec_ln10_swap =
189 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
190
191 struct wiz_clk_mux {
192 struct clk_hw hw;
193 struct regmap_field *field;
194 const u32 *table;
195 struct clk_init_data clk_data;
196 };
197
198 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw)
199
200 struct wiz_clk_divider {
201 struct clk_hw hw;
202 struct regmap_field *field;
203 const struct clk_div_table *table;
204 struct clk_init_data clk_data;
205 };
206
207 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
208
209 struct wiz_clk_mux_sel {
210 u32 table[WIZ_MAX_INPUT_CLOCKS];
211 const char *node_name;
212 u32 num_parents;
213 u32 parents[WIZ_MAX_INPUT_CLOCKS];
214 };
215
216 struct wiz_clk_div_sel {
217 const struct clk_div_table *table;
218 const char *node_name;
219 };
220
221 struct wiz_phy_en_refclk {
222 struct clk_hw hw;
223 struct regmap_field *phy_en_refclk;
224 struct clk_init_data clk_data;
225 };
226
227 #define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw)
228
229 static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
230 {
231 /*
232 * Mux value to be configured for each of the input clocks
233 * in the order populated in device tree
234 */
235 .table = { 1, 0 },
236 .node_name = "pll0-refclk",
237 },
238 {
239 .table = { 1, 0 },
240 .node_name = "pll1-refclk",
241 },
242 {
243 .table = { 1, 3, 0, 2 },
244 .node_name = "refclk-dig",
245 },
246 };
247
248 static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
249 {
250 /*
251 * Mux value to be configured for each of the input clocks
252 * in the order populated in device tree
253 */
254 .num_parents = 2,
255 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
256 .table = { 1, 0 },
257 .node_name = "pll0-refclk",
258 },
259 {
260 .num_parents = 2,
261 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
262 .table = { 1, 0 },
263 .node_name = "pll1-refclk",
264 },
265 {
266 .num_parents = 2,
267 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
268 .table = { 1, 0 },
269 .node_name = "refclk-dig",
270 },
271 };
272
273 static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
274 {
275 .num_parents = 3,
276 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
277 .table = { 2, 3, 0 },
278 .node_name = "pll0-refclk",
279 },
280 {
281 .num_parents = 3,
282 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
283 .table = { 2, 3, 0 },
284 .node_name = "pll1-refclk",
285 },
286 {
287 .num_parents = 3,
288 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
289 .table = { 2, 3, 0 },
290 .node_name = "refclk-dig",
291 },
292 };
293
294 static const struct clk_div_table clk_div_table[] = {
295 { .val = 0, .div = 1, },
296 { .val = 1, .div = 2, },
297 { .val = 2, .div = 4, },
298 { .val = 3, .div = 8, },
299 { /* sentinel */ },
300 };
301
302 static const struct wiz_clk_div_sel clk_div_sel[] = {
303 {
304 .table = clk_div_table,
305 .node_name = "cmn-refclk-dig-div",
306 },
307 {
308 .table = clk_div_table,
309 .node_name = "cmn-refclk1-dig-div",
310 },
311 };
312
313 enum wiz_type {
314 J721E_WIZ_16G,
315 J721E_WIZ_10G, /* Also for J7200 SR1.0 */
316 AM64_WIZ_10G,
317 J7200_WIZ_10G, /* J7200 SR2.0 */
318 };
319
320 struct wiz_data {
321 enum wiz_type type;
322 const struct reg_field *pll0_refclk_mux_sel;
323 const struct reg_field *pll1_refclk_mux_sel;
324 const struct reg_field *refclk_dig_sel;
325 const struct reg_field *pma_cmn_refclk1_dig_div;
326 const struct reg_field *pma_cmn_refclk1_int_mode;
327 const struct wiz_clk_mux_sel *clk_mux_sel;
328 unsigned int clk_div_sel_num;
329 };
330
331 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
332 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
333
334 struct wiz {
335 struct regmap *regmap;
336 struct regmap *scm_regmap;
337 enum wiz_type type;
338 const struct wiz_clk_mux_sel *clk_mux_sel;
339 const struct wiz_clk_div_sel *clk_div_sel;
340 unsigned int clk_div_sel_num;
341 struct regmap_field *por_en;
342 struct regmap_field *phy_reset_n;
343 struct regmap_field *phy_en_refclk;
344 struct regmap_field *p_enable[WIZ_MAX_LANES];
345 struct regmap_field *p_align[WIZ_MAX_LANES];
346 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
347 struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
348 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];
349 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
350 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
351 struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES];
352 struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES];
353 struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES];
354 struct regmap_field *pma_cmn_refclk_int_mode;
355 struct regmap_field *pma_cmn_refclk1_int_mode;
356 struct regmap_field *pma_cmn_refclk_mode;
357 struct regmap_field *pma_cmn_refclk_dig_div;
358 struct regmap_field *pma_cmn_refclk1_dig_div;
359 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
360 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
361 struct regmap_field *typec_ln10_swap;
362 struct regmap_field *sup_legacy_clk_override;
363
364 struct device *dev;
365 u32 num_lanes;
366 struct platform_device *serdes_pdev;
367 struct reset_controller_dev wiz_phy_reset_dev;
368 struct gpio_desc *gpio_typec_dir;
369 int typec_dir_delay;
370 u32 lane_phy_type[WIZ_MAX_LANES];
371 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
372 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
373 struct clk_onecell_data clk_data;
374 const struct wiz_data *data;
375 };
376
wiz_reset(struct wiz * wiz)377 static int wiz_reset(struct wiz *wiz)
378 {
379 int ret;
380
381 ret = regmap_field_write(wiz->por_en, 0x1);
382 if (ret)
383 return ret;
384
385 mdelay(1);
386
387 ret = regmap_field_write(wiz->por_en, 0x0);
388 if (ret)
389 return ret;
390
391 return 0;
392 }
393
wiz_p_mac_div_sel(struct wiz * wiz)394 static int wiz_p_mac_div_sel(struct wiz *wiz)
395 {
396 u32 num_lanes = wiz->num_lanes;
397 int ret;
398 int i;
399
400 for (i = 0; i < num_lanes; i++) {
401 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
402 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII ||
403 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
404 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
405 if (ret)
406 return ret;
407
408 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
409 if (ret)
410 return ret;
411 }
412 }
413
414 return 0;
415 }
416
wiz_mode_select(struct wiz * wiz)417 static int wiz_mode_select(struct wiz *wiz)
418 {
419 u32 num_lanes = wiz->num_lanes;
420 enum wiz_lane_standard_mode mode;
421 int ret;
422 int i;
423
424 for (i = 0; i < num_lanes; i++) {
425 if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
426 mode = LANE_MODE_GEN1;
427 else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII)
428 mode = LANE_MODE_GEN2;
429 else
430 continue;
431
432 if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
433 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);
434 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);
435 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);
436 mode = LANE_MODE_GEN1;
437 }
438
439 ret = regmap_field_write(wiz->p_standard_mode[i], mode);
440 if (ret)
441 return ret;
442 }
443
444 return 0;
445 }
446
wiz_init_raw_interface(struct wiz * wiz,bool enable)447 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
448 {
449 u32 num_lanes = wiz->num_lanes;
450 int i;
451 int ret;
452
453 for (i = 0; i < num_lanes; i++) {
454 ret = regmap_field_write(wiz->p_align[i], enable);
455 if (ret)
456 return ret;
457
458 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
459 if (ret)
460 return ret;
461 }
462
463 return 0;
464 }
465
wiz_init(struct wiz * wiz)466 static int wiz_init(struct wiz *wiz)
467 {
468 struct device *dev = wiz->dev;
469 int ret;
470
471 ret = wiz_reset(wiz);
472 if (ret) {
473 dev_err(dev, "WIZ reset failed\n");
474 return ret;
475 }
476
477 ret = wiz_mode_select(wiz);
478 if (ret) {
479 dev_err(dev, "WIZ mode select failed\n");
480 return ret;
481 }
482
483 ret = wiz_p_mac_div_sel(wiz);
484 if (ret) {
485 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n");
486 return ret;
487 }
488
489 ret = wiz_init_raw_interface(wiz, true);
490 if (ret) {
491 dev_err(dev, "WIZ interface initialization failed\n");
492 return ret;
493 }
494
495 return 0;
496 }
497
wiz_regfield_init(struct wiz * wiz)498 static int wiz_regfield_init(struct wiz *wiz)
499 {
500 struct regmap *regmap = wiz->regmap;
501 struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */
502 int num_lanes = wiz->num_lanes;
503 struct device *dev = wiz->dev;
504 const struct wiz_data *data = wiz->data;
505 int i;
506
507 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
508 if (IS_ERR(wiz->por_en)) {
509 dev_err(dev, "POR_EN reg field init failed\n");
510 return PTR_ERR(wiz->por_en);
511 }
512
513 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
514 phy_reset_n);
515 if (IS_ERR(wiz->phy_reset_n)) {
516 dev_err(dev, "PHY_RESET_N reg field init failed\n");
517 return PTR_ERR(wiz->phy_reset_n);
518 }
519
520 wiz->pma_cmn_refclk_int_mode =
521 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
522 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
523 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
524 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
525 }
526
527 wiz->pma_cmn_refclk_mode =
528 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
529 if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
530 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
531 return PTR_ERR(wiz->pma_cmn_refclk_mode);
532 }
533
534 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] =
535 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div);
536 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) {
537 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
538 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]);
539 }
540
541 if (data->pma_cmn_refclk1_dig_div) {
542 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =
543 devm_regmap_field_alloc(dev, regmap,
544 *data->pma_cmn_refclk1_dig_div);
545 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {
546 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
547 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);
548 }
549 }
550
551 if (wiz->scm_regmap) {
552 scm_regmap = wiz->scm_regmap;
553 wiz->sup_legacy_clk_override =
554 devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override);
555 if (IS_ERR(wiz->sup_legacy_clk_override)) {
556 dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n");
557 return PTR_ERR(wiz->sup_legacy_clk_override);
558 }
559 }
560
561 wiz->mux_sel_field[PLL0_REFCLK] =
562 devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel);
563 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
564 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
565 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
566 }
567
568 wiz->mux_sel_field[PLL1_REFCLK] =
569 devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel);
570 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
571 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
572 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
573 }
574
575 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap,
576 *data->refclk_dig_sel);
577 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
578 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
579 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
580 }
581
582 if (data->pma_cmn_refclk1_int_mode) {
583 wiz->pma_cmn_refclk1_int_mode =
584 devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode);
585 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
586 dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
587 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
588 }
589 }
590
591 for (i = 0; i < num_lanes; i++) {
592 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
593 p_enable[i]);
594 if (IS_ERR(wiz->p_enable[i])) {
595 dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
596 return PTR_ERR(wiz->p_enable[i]);
597 }
598
599 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
600 p_align[i]);
601 if (IS_ERR(wiz->p_align[i])) {
602 dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
603 return PTR_ERR(wiz->p_align[i]);
604 }
605
606 wiz->p_raw_auto_start[i] =
607 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
608 if (IS_ERR(wiz->p_raw_auto_start[i])) {
609 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
610 i);
611 return PTR_ERR(wiz->p_raw_auto_start[i]);
612 }
613
614 wiz->p_standard_mode[i] =
615 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
616 if (IS_ERR(wiz->p_standard_mode[i])) {
617 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
618 i);
619 return PTR_ERR(wiz->p_standard_mode[i]);
620 }
621
622 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
623 if (IS_ERR(wiz->p0_fullrt_div[i])) {
624 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
625 return PTR_ERR(wiz->p0_fullrt_div[i]);
626 }
627
628 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]);
629 if (IS_ERR(wiz->p0_mac_src_sel[i])) {
630 dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i);
631 return PTR_ERR(wiz->p0_mac_src_sel[i]);
632 }
633
634 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]);
635 if (IS_ERR(wiz->p0_rxfclk_sel[i])) {
636 dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i);
637 return PTR_ERR(wiz->p0_rxfclk_sel[i]);
638 }
639
640 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]);
641 if (IS_ERR(wiz->p0_refclk_sel[i])) {
642 dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i);
643 return PTR_ERR(wiz->p0_refclk_sel[i]);
644 }
645
646 wiz->p_mac_div_sel0[i] =
647 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
648 if (IS_ERR(wiz->p_mac_div_sel0[i])) {
649 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
650 i);
651 return PTR_ERR(wiz->p_mac_div_sel0[i]);
652 }
653
654 wiz->p_mac_div_sel1[i] =
655 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]);
656 if (IS_ERR(wiz->p_mac_div_sel1[i])) {
657 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
658 i);
659 return PTR_ERR(wiz->p_mac_div_sel1[i]);
660 }
661 }
662
663 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
664 typec_ln10_swap);
665 if (IS_ERR(wiz->typec_ln10_swap)) {
666 dev_err(dev, "LN10_SWAP reg field init failed\n");
667 return PTR_ERR(wiz->typec_ln10_swap);
668 }
669
670 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
671 if (IS_ERR(wiz->phy_en_refclk)) {
672 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
673 return PTR_ERR(wiz->phy_en_refclk);
674 }
675
676 return 0;
677 }
678
wiz_phy_en_refclk_enable(struct clk_hw * hw)679 static int wiz_phy_en_refclk_enable(struct clk_hw *hw)
680 {
681 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
682 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
683
684 regmap_field_write(phy_en_refclk, 1);
685
686 return 0;
687 }
688
wiz_phy_en_refclk_disable(struct clk_hw * hw)689 static void wiz_phy_en_refclk_disable(struct clk_hw *hw)
690 {
691 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
692 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
693
694 regmap_field_write(phy_en_refclk, 0);
695 }
696
wiz_phy_en_refclk_is_enabled(struct clk_hw * hw)697 static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw)
698 {
699 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
700 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
701 int val;
702
703 regmap_field_read(phy_en_refclk, &val);
704
705 return !!val;
706 }
707
708 static const struct clk_ops wiz_phy_en_refclk_ops = {
709 .enable = wiz_phy_en_refclk_enable,
710 .disable = wiz_phy_en_refclk_disable,
711 .is_enabled = wiz_phy_en_refclk_is_enabled,
712 };
713
wiz_phy_en_refclk_register(struct wiz * wiz)714 static int wiz_phy_en_refclk_register(struct wiz *wiz)
715 {
716 struct wiz_phy_en_refclk *wiz_phy_en_refclk;
717 struct device *dev = wiz->dev;
718 struct clk_init_data *init;
719 struct clk *clk;
720 char *clk_name;
721 unsigned int sz;
722
723 wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL);
724 if (!wiz_phy_en_refclk)
725 return -ENOMEM;
726
727 init = &wiz_phy_en_refclk->clk_data;
728
729 init->ops = &wiz_phy_en_refclk_ops;
730 init->flags = 0;
731
732 sz = strlen(dev_name(dev)) + strlen(output_clk_names[TI_WIZ_PHY_EN_REFCLK]) + 2;
733
734 clk_name = kzalloc(sz, GFP_KERNEL);
735 if (!clk_name)
736 return -ENOMEM;
737
738 snprintf(clk_name, sz, "%s_%s", dev_name(dev), output_clk_names[TI_WIZ_PHY_EN_REFCLK]);
739 init->name = clk_name;
740
741 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk;
742 wiz_phy_en_refclk->hw.init = init;
743
744 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw);
745
746 kfree(clk_name);
747
748 if (IS_ERR(clk))
749 return PTR_ERR(clk);
750
751 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk;
752
753 return 0;
754 }
755
wiz_clk_mux_get_parent(struct clk_hw * hw)756 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw)
757 {
758 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
759 struct regmap_field *field = mux->field;
760 unsigned int val;
761
762 regmap_field_read(field, &val);
763 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val);
764 }
765
wiz_clk_mux_set_parent(struct clk_hw * hw,u8 index)766 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index)
767 {
768 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
769 struct regmap_field *field = mux->field;
770 int val;
771
772 val = mux->table[index];
773 return regmap_field_write(field, val);
774 }
775
776 static const struct clk_ops wiz_clk_mux_ops = {
777 .set_parent = wiz_clk_mux_set_parent,
778 .get_parent = wiz_clk_mux_get_parent,
779 };
780
wiz_mux_clk_register(struct wiz * wiz,struct regmap_field * field,const struct wiz_clk_mux_sel * mux_sel,int clk_index)781 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,
782 const struct wiz_clk_mux_sel *mux_sel, int clk_index)
783 {
784 struct device *dev = wiz->dev;
785 struct clk_init_data *init;
786 const char **parent_names;
787 unsigned int num_parents;
788 struct wiz_clk_mux *mux;
789 char clk_name[100];
790 struct clk *clk;
791 int ret = 0, i;
792
793 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
794 if (!mux)
795 return -ENOMEM;
796
797 num_parents = mux_sel->num_parents;
798
799 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
800 if (!parent_names)
801 return -ENOMEM;
802
803 for (i = 0; i < num_parents; i++) {
804 clk = wiz->input_clks[mux_sel->parents[i]];
805 if (IS_ERR_OR_NULL(clk)) {
806 dev_err(dev, "Failed to get parent clk for %s\n",
807 output_clk_names[clk_index]);
808 ret = -EINVAL;
809 goto err;
810 }
811 parent_names[i] = __clk_get_name(clk);
812 }
813
814 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]);
815
816 init = &mux->clk_data;
817
818 init->ops = &wiz_clk_mux_ops;
819 init->flags = CLK_SET_RATE_NO_REPARENT;
820 init->parent_names = parent_names;
821 init->num_parents = num_parents;
822 init->name = clk_name;
823
824 mux->field = field;
825 mux->table = mux_sel->table;
826 mux->hw.init = init;
827
828 clk = devm_clk_register(dev, &mux->hw);
829 if (IS_ERR(clk)) {
830 ret = PTR_ERR(clk);
831 goto err;
832 }
833
834 wiz->output_clks[clk_index] = clk;
835
836 err:
837 kfree(parent_names);
838
839 return ret;
840 }
841
wiz_mux_of_clk_register(struct wiz * wiz,struct device_node * node,struct regmap_field * field,const u32 * table)842 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node,
843 struct regmap_field *field, const u32 *table)
844 {
845 struct device *dev = wiz->dev;
846 struct clk_init_data *init;
847 const char **parent_names;
848 unsigned int num_parents;
849 struct wiz_clk_mux *mux;
850 char clk_name[100];
851 struct clk *clk;
852 int ret;
853
854 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
855 if (!mux)
856 return -ENOMEM;
857
858 num_parents = of_clk_get_parent_count(node);
859 if (num_parents < 2) {
860 dev_err(dev, "SERDES clock must have parents\n");
861 return -EINVAL;
862 }
863
864 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
865 GFP_KERNEL);
866 if (!parent_names)
867 return -ENOMEM;
868
869 of_clk_parent_fill(node, parent_names, num_parents);
870
871 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
872 node->name);
873
874 init = &mux->clk_data;
875
876 init->ops = &wiz_clk_mux_ops;
877 init->flags = CLK_SET_RATE_NO_REPARENT;
878 init->parent_names = parent_names;
879 init->num_parents = num_parents;
880 init->name = clk_name;
881
882 mux->field = field;
883 mux->table = table;
884 mux->hw.init = init;
885
886 clk = devm_clk_register(dev, &mux->hw);
887 if (IS_ERR(clk))
888 return PTR_ERR(clk);
889
890 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
891 if (ret)
892 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
893
894 return ret;
895 }
896
wiz_clk_div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)897 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
898 unsigned long parent_rate)
899 {
900 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
901 struct regmap_field *field = div->field;
902 int val;
903
904 regmap_field_read(field, &val);
905
906 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
907 }
908
wiz_clk_div_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)909 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
910 unsigned long *prate)
911 {
912 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
913
914 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
915 }
916
wiz_clk_div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)917 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
918 unsigned long parent_rate)
919 {
920 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
921 struct regmap_field *field = div->field;
922 int val;
923
924 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0);
925 if (val < 0)
926 return val;
927
928 return regmap_field_write(field, val);
929 }
930
931 static const struct clk_ops wiz_clk_div_ops = {
932 .recalc_rate = wiz_clk_div_recalc_rate,
933 .round_rate = wiz_clk_div_round_rate,
934 .set_rate = wiz_clk_div_set_rate,
935 };
936
wiz_div_clk_register(struct wiz * wiz,struct device_node * node,struct regmap_field * field,const struct clk_div_table * table)937 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
938 struct regmap_field *field,
939 const struct clk_div_table *table)
940 {
941 struct device *dev = wiz->dev;
942 struct wiz_clk_divider *div;
943 struct clk_init_data *init;
944 const char **parent_names;
945 char clk_name[100];
946 struct clk *clk;
947 int ret;
948
949 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
950 if (!div)
951 return -ENOMEM;
952
953 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
954 node->name);
955
956 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
957 if (!parent_names)
958 return -ENOMEM;
959
960 of_clk_parent_fill(node, parent_names, 1);
961
962 init = &div->clk_data;
963
964 init->ops = &wiz_clk_div_ops;
965 init->flags = 0;
966 init->parent_names = parent_names;
967 init->num_parents = 1;
968 init->name = clk_name;
969
970 div->field = field;
971 div->table = table;
972 div->hw.init = init;
973
974 clk = devm_clk_register(dev, &div->hw);
975 if (IS_ERR(clk))
976 return PTR_ERR(clk);
977
978 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
979 if (ret)
980 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
981
982 return ret;
983 }
984
wiz_clock_cleanup(struct wiz * wiz,struct device_node * node)985 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
986 {
987 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
988 struct device *dev = wiz->dev;
989 struct device_node *clk_node;
990 int i;
991
992 switch (wiz->type) {
993 case AM64_WIZ_10G:
994 case J7200_WIZ_10G:
995 of_clk_del_provider(dev->of_node);
996 return;
997 default:
998 break;
999 }
1000
1001 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
1002 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
1003 of_clk_del_provider(clk_node);
1004 of_node_put(clk_node);
1005 }
1006
1007 for (i = 0; i < wiz->clk_div_sel_num; i++) {
1008 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name);
1009 of_clk_del_provider(clk_node);
1010 of_node_put(clk_node);
1011 }
1012
1013 of_clk_del_provider(wiz->dev->of_node);
1014 }
1015
wiz_clock_register(struct wiz * wiz)1016 static int wiz_clock_register(struct wiz *wiz)
1017 {
1018 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1019 struct device *dev = wiz->dev;
1020 struct device_node *node = dev->of_node;
1021 int clk_index;
1022 int ret;
1023 int i;
1024
1025 clk_index = TI_WIZ_PLL0_REFCLK;
1026 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) {
1027 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
1028 if (ret) {
1029 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]);
1030 return ret;
1031 }
1032 }
1033
1034 ret = wiz_phy_en_refclk_register(wiz);
1035 if (ret) {
1036 dev_err(dev, "Failed to add phy-en-refclk\n");
1037 return ret;
1038 }
1039
1040 wiz->clk_data.clks = wiz->output_clks;
1041 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;
1042 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);
1043 if (ret)
1044 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
1045
1046 return ret;
1047 }
1048
wiz_clock_init(struct wiz * wiz,struct device_node * node)1049 static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
1050 {
1051 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1052 struct device *dev = wiz->dev;
1053 struct device_node *clk_node;
1054 const char *node_name;
1055 unsigned long rate;
1056 struct clk *clk;
1057 int ret;
1058 int i;
1059
1060 clk = devm_clk_get(dev, "core_ref_clk");
1061 if (IS_ERR(clk)) {
1062 dev_err(dev, "core_ref_clk clock not found\n");
1063 ret = PTR_ERR(clk);
1064 return ret;
1065 }
1066 wiz->input_clks[WIZ_CORE_REFCLK] = clk;
1067
1068 rate = clk_get_rate(clk);
1069 if (rate >= 100000000)
1070 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
1071 else
1072 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
1073
1074 switch (wiz->type) {
1075 case AM64_WIZ_10G:
1076 case J7200_WIZ_10G:
1077 switch (rate) {
1078 case REF_CLK_100MHZ:
1079 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);
1080 break;
1081 case REF_CLK_156_25MHZ:
1082 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);
1083 break;
1084 default:
1085 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);
1086 break;
1087 }
1088 break;
1089 default:
1090 break;
1091 }
1092
1093 if (wiz->data->pma_cmn_refclk1_int_mode) {
1094 clk = devm_clk_get(dev, "core_ref1_clk");
1095 if (IS_ERR(clk)) {
1096 dev_err(dev, "core_ref1_clk clock not found\n");
1097 ret = PTR_ERR(clk);
1098 return ret;
1099 }
1100 wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
1101
1102 rate = clk_get_rate(clk);
1103 if (rate >= 100000000)
1104 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
1105 else
1106 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
1107 }
1108
1109 clk = devm_clk_get(dev, "ext_ref_clk");
1110 if (IS_ERR(clk)) {
1111 dev_err(dev, "ext_ref_clk clock not found\n");
1112 ret = PTR_ERR(clk);
1113 return ret;
1114 }
1115 wiz->input_clks[WIZ_EXT_REFCLK] = clk;
1116
1117 rate = clk_get_rate(clk);
1118 if (rate >= 100000000)
1119 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
1120 else
1121 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
1122
1123 switch (wiz->type) {
1124 case AM64_WIZ_10G:
1125 case J7200_WIZ_10G:
1126 ret = wiz_clock_register(wiz);
1127 if (ret)
1128 dev_err(dev, "Failed to register wiz clocks\n");
1129 return ret;
1130 default:
1131 break;
1132 }
1133
1134 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
1135 node_name = clk_mux_sel[i].node_name;
1136 clk_node = of_get_child_by_name(node, node_name);
1137 if (!clk_node) {
1138 dev_err(dev, "Unable to get %s node\n", node_name);
1139 ret = -EINVAL;
1140 goto err;
1141 }
1142
1143 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i],
1144 clk_mux_sel[i].table);
1145 if (ret) {
1146 dev_err(dev, "Failed to register %s clock\n",
1147 node_name);
1148 of_node_put(clk_node);
1149 goto err;
1150 }
1151
1152 of_node_put(clk_node);
1153 }
1154
1155 for (i = 0; i < wiz->clk_div_sel_num; i++) {
1156 node_name = clk_div_sel[i].node_name;
1157 clk_node = of_get_child_by_name(node, node_name);
1158 if (!clk_node) {
1159 dev_err(dev, "Unable to get %s node\n", node_name);
1160 ret = -EINVAL;
1161 goto err;
1162 }
1163
1164 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i],
1165 clk_div_sel[i].table);
1166 if (ret) {
1167 dev_err(dev, "Failed to register %s clock\n",
1168 node_name);
1169 of_node_put(clk_node);
1170 goto err;
1171 }
1172
1173 of_node_put(clk_node);
1174 }
1175
1176 return 0;
1177 err:
1178 wiz_clock_cleanup(wiz, node);
1179
1180 return ret;
1181 }
1182
wiz_phy_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)1183 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
1184 unsigned long id)
1185 {
1186 struct device *dev = rcdev->dev;
1187 struct wiz *wiz = dev_get_drvdata(dev);
1188 int ret = 0;
1189
1190 if (id == 0) {
1191 ret = regmap_field_write(wiz->phy_reset_n, false);
1192 return ret;
1193 }
1194
1195 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
1196 return ret;
1197 }
1198
wiz_phy_fullrt_div(struct wiz * wiz,int lane)1199 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
1200 {
1201 switch (wiz->type) {
1202 case AM64_WIZ_10G:
1203 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
1204 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
1205 break;
1206 case J721E_WIZ_10G:
1207 case J7200_WIZ_10G:
1208 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
1209 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
1210 break;
1211 default:
1212 return 0;
1213 }
1214 return 0;
1215 }
1216
wiz_phy_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)1217 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
1218 unsigned long id)
1219 {
1220 struct device *dev = rcdev->dev;
1221 struct wiz *wiz = dev_get_drvdata(dev);
1222 int ret;
1223
1224 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
1225 if (id == 0 && wiz->gpio_typec_dir) {
1226 if (wiz->typec_dir_delay)
1227 msleep_interruptible(wiz->typec_dir_delay);
1228
1229 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1230 regmap_field_write(wiz->typec_ln10_swap, 1);
1231 else
1232 regmap_field_write(wiz->typec_ln10_swap, 0);
1233 }
1234
1235 if (id == 0) {
1236 ret = regmap_field_write(wiz->phy_reset_n, true);
1237 return ret;
1238 }
1239
1240 ret = wiz_phy_fullrt_div(wiz, id - 1);
1241 if (ret)
1242 return ret;
1243
1244 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
1245 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
1246 else
1247 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
1248
1249 return ret;
1250 }
1251
1252 static const struct reset_control_ops wiz_phy_reset_ops = {
1253 .assert = wiz_phy_reset_assert,
1254 .deassert = wiz_phy_reset_deassert,
1255 };
1256
1257 static const struct regmap_config wiz_regmap_config = {
1258 .reg_bits = 32,
1259 .val_bits = 32,
1260 .reg_stride = 4,
1261 .fast_io = true,
1262 };
1263
1264 static struct wiz_data j721e_16g_data = {
1265 .type = J721E_WIZ_16G,
1266 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1267 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1268 .refclk_dig_sel = &refclk_dig_sel_16g,
1269 .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
1270 .clk_mux_sel = clk_mux_sel_16g,
1271 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
1272 };
1273
1274 static struct wiz_data j721e_10g_data = {
1275 .type = J721E_WIZ_10G,
1276 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1277 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1278 .refclk_dig_sel = &refclk_dig_sel_10g,
1279 .clk_mux_sel = clk_mux_sel_10g,
1280 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1281 };
1282
1283 static struct wiz_data am64_10g_data = {
1284 .type = AM64_WIZ_10G,
1285 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1286 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1287 .refclk_dig_sel = &refclk_dig_sel_10g,
1288 .clk_mux_sel = clk_mux_sel_10g,
1289 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1290 };
1291
1292 static struct wiz_data j7200_pg2_10g_data = {
1293 .type = J7200_WIZ_10G,
1294 .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel,
1295 .pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel,
1296 .refclk_dig_sel = &sup_refclk_dig_sel_10g,
1297 .pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode,
1298 .clk_mux_sel = clk_mux_sel_10g_2_refclk,
1299 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1300 };
1301
1302 static const struct of_device_id wiz_id_table[] = {
1303 {
1304 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
1305 },
1306 {
1307 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data,
1308 },
1309 {
1310 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
1311 },
1312 {
1313 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
1314 },
1315 {}
1316 };
1317 MODULE_DEVICE_TABLE(of, wiz_id_table);
1318
wiz_get_lane_phy_types(struct device * dev,struct wiz * wiz)1319 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
1320 {
1321 struct device_node *serdes, *subnode;
1322
1323 serdes = of_get_child_by_name(dev->of_node, "serdes");
1324 if (!serdes) {
1325 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
1326 return -EINVAL;
1327 }
1328
1329 for_each_child_of_node(serdes, subnode) {
1330 u32 reg, num_lanes = 1, phy_type = PHY_NONE;
1331 int ret, i;
1332
1333 if (!(of_node_name_eq(subnode, "phy") ||
1334 of_node_name_eq(subnode, "link")))
1335 continue;
1336
1337 ret = of_property_read_u32(subnode, "reg", ®);
1338 if (ret) {
1339 of_node_put(subnode);
1340 dev_err(dev,
1341 "%s: Reading \"reg\" from \"%s\" failed: %d\n",
1342 __func__, subnode->name, ret);
1343 return ret;
1344 }
1345 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes);
1346 of_property_read_u32(subnode, "cdns,phy-type", &phy_type);
1347
1348 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
1349 reg, reg + num_lanes - 1, phy_type);
1350
1351 for (i = reg; i < reg + num_lanes; i++)
1352 wiz->lane_phy_type[i] = phy_type;
1353 }
1354
1355 return 0;
1356 }
1357
wiz_probe(struct platform_device * pdev)1358 static int wiz_probe(struct platform_device *pdev)
1359 {
1360 struct reset_controller_dev *phy_reset_dev;
1361 struct device *dev = &pdev->dev;
1362 struct device_node *node = dev->of_node;
1363 struct platform_device *serdes_pdev;
1364 bool already_configured = false;
1365 struct device_node *child_node;
1366 struct regmap *regmap;
1367 struct resource res;
1368 void __iomem *base;
1369 struct wiz *wiz;
1370 int ret, val, i;
1371 u32 num_lanes;
1372 const struct wiz_data *data;
1373
1374 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
1375 if (!wiz)
1376 return -ENOMEM;
1377
1378 data = of_device_get_match_data(dev);
1379 if (!data) {
1380 dev_err(dev, "NULL device data\n");
1381 return -EINVAL;
1382 }
1383
1384 wiz->data = data;
1385 wiz->type = data->type;
1386
1387 child_node = of_get_child_by_name(node, "serdes");
1388 if (!child_node) {
1389 dev_err(dev, "Failed to get SERDES child DT node\n");
1390 return -ENODEV;
1391 }
1392
1393 ret = of_address_to_resource(child_node, 0, &res);
1394 if (ret) {
1395 dev_err(dev, "Failed to get memory resource\n");
1396 goto err_addr_to_resource;
1397 }
1398
1399 base = devm_ioremap(dev, res.start, resource_size(&res));
1400 if (!base) {
1401 ret = -ENOMEM;
1402 goto err_addr_to_resource;
1403 }
1404
1405 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config);
1406 if (IS_ERR(regmap)) {
1407 dev_err(dev, "Failed to initialize regmap\n");
1408 ret = PTR_ERR(regmap);
1409 goto err_addr_to_resource;
1410 }
1411
1412 wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm");
1413 if (IS_ERR(wiz->scm_regmap)) {
1414 if (wiz->type == J7200_WIZ_10G) {
1415 dev_err(dev, "Couldn't get ti,scm regmap\n");
1416 ret = -ENODEV;
1417 goto err_addr_to_resource;
1418 }
1419
1420 wiz->scm_regmap = NULL;
1421 }
1422
1423 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
1424 if (ret) {
1425 dev_err(dev, "Failed to read num-lanes property\n");
1426 goto err_addr_to_resource;
1427 }
1428
1429 if (num_lanes > WIZ_MAX_LANES) {
1430 dev_err(dev, "Cannot support %d lanes\n", num_lanes);
1431 ret = -ENODEV;
1432 goto err_addr_to_resource;
1433 }
1434
1435 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
1436 GPIOD_IN);
1437 if (IS_ERR(wiz->gpio_typec_dir)) {
1438 ret = PTR_ERR(wiz->gpio_typec_dir);
1439 if (ret != -EPROBE_DEFER)
1440 dev_err(dev, "Failed to request typec-dir gpio: %d\n",
1441 ret);
1442 goto err_addr_to_resource;
1443 }
1444
1445 if (wiz->gpio_typec_dir) {
1446 ret = of_property_read_u32(node, "typec-dir-debounce-ms",
1447 &wiz->typec_dir_delay);
1448 if (ret && ret != -EINVAL) {
1449 dev_err(dev, "Invalid typec-dir-debounce property\n");
1450 goto err_addr_to_resource;
1451 }
1452
1453 /* use min. debounce from Type-C spec if not provided in DT */
1454 if (ret == -EINVAL)
1455 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
1456
1457 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
1458 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
1459 ret = -EINVAL;
1460 dev_err(dev, "Invalid typec-dir-debounce property\n");
1461 goto err_addr_to_resource;
1462 }
1463 }
1464
1465 ret = wiz_get_lane_phy_types(dev, wiz);
1466 if (ret)
1467 goto err_addr_to_resource;
1468
1469 wiz->dev = dev;
1470 wiz->regmap = regmap;
1471 wiz->num_lanes = num_lanes;
1472 wiz->clk_mux_sel = data->clk_mux_sel;
1473 wiz->clk_div_sel = clk_div_sel;
1474 wiz->clk_div_sel_num = data->clk_div_sel_num;
1475
1476 platform_set_drvdata(pdev, wiz);
1477
1478 ret = wiz_regfield_init(wiz);
1479 if (ret) {
1480 dev_err(dev, "Failed to initialize regfields\n");
1481 goto err_addr_to_resource;
1482 }
1483
1484 /* Enable supplemental Control override if available */
1485 if (wiz->scm_regmap)
1486 regmap_field_write(wiz->sup_legacy_clk_override, 1);
1487
1488 phy_reset_dev = &wiz->wiz_phy_reset_dev;
1489 phy_reset_dev->dev = dev;
1490 phy_reset_dev->ops = &wiz_phy_reset_ops,
1491 phy_reset_dev->owner = THIS_MODULE,
1492 phy_reset_dev->of_node = node;
1493 /* Reset for each of the lane and one for the entire SERDES */
1494 phy_reset_dev->nr_resets = num_lanes + 1;
1495
1496 ret = devm_reset_controller_register(dev, phy_reset_dev);
1497 if (ret < 0) {
1498 dev_warn(dev, "Failed to register reset controller\n");
1499 goto err_addr_to_resource;
1500 }
1501
1502 pm_runtime_enable(dev);
1503 ret = pm_runtime_get_sync(dev);
1504 if (ret < 0) {
1505 dev_err(dev, "pm_runtime_get_sync failed\n");
1506 goto err_get_sync;
1507 }
1508
1509 ret = wiz_clock_init(wiz, node);
1510 if (ret < 0) {
1511 dev_warn(dev, "Failed to initialize clocks\n");
1512 goto err_get_sync;
1513 }
1514
1515 for (i = 0; i < wiz->num_lanes; i++) {
1516 regmap_field_read(wiz->p_enable[i], &val);
1517 if (val & (P_ENABLE | P_ENABLE_FORCE)) {
1518 already_configured = true;
1519 break;
1520 }
1521 }
1522
1523 if (!already_configured) {
1524 ret = wiz_init(wiz);
1525 if (ret) {
1526 dev_err(dev, "WIZ initialization failed\n");
1527 goto err_wiz_init;
1528 }
1529 }
1530
1531 serdes_pdev = of_platform_device_create(child_node, NULL, dev);
1532 if (!serdes_pdev) {
1533 dev_WARN(dev, "Unable to create SERDES platform device\n");
1534 ret = -ENOMEM;
1535 goto err_wiz_init;
1536 }
1537 wiz->serdes_pdev = serdes_pdev;
1538
1539 of_node_put(child_node);
1540 return 0;
1541
1542 err_wiz_init:
1543 wiz_clock_cleanup(wiz, node);
1544
1545 err_get_sync:
1546 pm_runtime_put(dev);
1547 pm_runtime_disable(dev);
1548
1549 err_addr_to_resource:
1550 of_node_put(child_node);
1551
1552 return ret;
1553 }
1554
wiz_remove(struct platform_device * pdev)1555 static int wiz_remove(struct platform_device *pdev)
1556 {
1557 struct device *dev = &pdev->dev;
1558 struct device_node *node = dev->of_node;
1559 struct platform_device *serdes_pdev;
1560 struct wiz *wiz;
1561
1562 wiz = dev_get_drvdata(dev);
1563 serdes_pdev = wiz->serdes_pdev;
1564
1565 of_platform_device_destroy(&serdes_pdev->dev, NULL);
1566 wiz_clock_cleanup(wiz, node);
1567 pm_runtime_put(dev);
1568 pm_runtime_disable(dev);
1569
1570 return 0;
1571 }
1572
1573 static struct platform_driver wiz_driver = {
1574 .probe = wiz_probe,
1575 .remove = wiz_remove,
1576 .driver = {
1577 .name = "wiz",
1578 .of_match_table = wiz_id_table,
1579 },
1580 };
1581 module_platform_driver(wiz_driver);
1582
1583 MODULE_AUTHOR("Texas Instruments Inc.");
1584 MODULE_DESCRIPTION("TI J721E WIZ driver");
1585 MODULE_LICENSE("GPL v2");
1586