1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments CPSW Port's PHY Interface Mode selection Driver
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
6 *
7 * Based on cpsw-phy-sel.c driver created by Mugunthan V N <mugunthanvnm@ti.com>
8 */
9
10 #include <linux/platform_device.h>
11 #include <linux/module.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/of_net.h>
16 #include <linux/phy.h>
17 #include <linux/phy/phy.h>
18 #include <linux/regmap.h>
19
20 /* AM33xx SoC specific definitions for the CONTROL port */
21 #define AM33XX_GMII_SEL_MODE_MII 0
22 #define AM33XX_GMII_SEL_MODE_RMII 1
23 #define AM33XX_GMII_SEL_MODE_RGMII 2
24
25 /* J72xx SoC specific definitions for the CONTROL port */
26 #define J72XX_GMII_SEL_MODE_QSGMII 4
27 #define J72XX_GMII_SEL_MODE_QSGMII_SUB 6
28
29 #define PHY_GMII_PORT(n) BIT((n) - 1)
30
31 enum {
32 PHY_GMII_SEL_PORT_MODE = 0,
33 PHY_GMII_SEL_RGMII_ID_MODE,
34 PHY_GMII_SEL_RMII_IO_CLK_EN,
35 PHY_GMII_SEL_LAST,
36 };
37
38 struct phy_gmii_sel_phy_priv {
39 struct phy_gmii_sel_priv *priv;
40 u32 id;
41 struct phy *if_phy;
42 int rmii_clock_external;
43 int phy_if_mode;
44 struct regmap_field *fields[PHY_GMII_SEL_LAST];
45 };
46
47 struct phy_gmii_sel_soc_data {
48 u32 num_ports;
49 u32 features;
50 const struct reg_field (*regfields)[PHY_GMII_SEL_LAST];
51 bool use_of_data;
52 u64 extra_modes;
53 };
54
55 struct phy_gmii_sel_priv {
56 struct device *dev;
57 const struct phy_gmii_sel_soc_data *soc_data;
58 struct regmap *regmap;
59 struct phy_provider *phy_provider;
60 struct phy_gmii_sel_phy_priv *if_phys;
61 u32 num_ports;
62 u32 reg_offset;
63 u32 qsgmii_main_ports;
64 };
65
phy_gmii_sel_mode(struct phy * phy,enum phy_mode mode,int submode)66 static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
67 {
68 struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy);
69 const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data;
70 struct device *dev = if_phy->priv->dev;
71 struct regmap_field *regfield;
72 int ret, rgmii_id = 0;
73 u32 gmii_sel_mode = 0;
74
75 if (mode != PHY_MODE_ETHERNET)
76 return -EINVAL;
77
78 switch (submode) {
79 case PHY_INTERFACE_MODE_RMII:
80 gmii_sel_mode = AM33XX_GMII_SEL_MODE_RMII;
81 break;
82
83 case PHY_INTERFACE_MODE_RGMII:
84 case PHY_INTERFACE_MODE_RGMII_RXID:
85 gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
86 break;
87
88 case PHY_INTERFACE_MODE_RGMII_ID:
89 case PHY_INTERFACE_MODE_RGMII_TXID:
90 gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
91 rgmii_id = 1;
92 break;
93
94 case PHY_INTERFACE_MODE_MII:
95 case PHY_INTERFACE_MODE_GMII:
96 gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII;
97 break;
98
99 case PHY_INTERFACE_MODE_QSGMII:
100 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_QSGMII)))
101 goto unsupported;
102 if (if_phy->priv->qsgmii_main_ports & BIT(if_phy->id - 1))
103 gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII;
104 else
105 gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII_SUB;
106 break;
107
108 default:
109 goto unsupported;
110 }
111
112 if_phy->phy_if_mode = submode;
113
114 dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n",
115 __func__, if_phy->id, submode, rgmii_id,
116 if_phy->rmii_clock_external);
117
118 regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE];
119 ret = regmap_field_write(regfield, gmii_sel_mode);
120 if (ret) {
121 dev_err(dev, "port%u: set mode fail %d", if_phy->id, ret);
122 return ret;
123 }
124
125 if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE) &&
126 if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]) {
127 regfield = if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE];
128 ret = regmap_field_write(regfield, rgmii_id);
129 if (ret)
130 return ret;
131 }
132
133 if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) &&
134 if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]) {
135 regfield = if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN];
136 ret = regmap_field_write(regfield,
137 if_phy->rmii_clock_external);
138 }
139
140 return 0;
141
142 unsupported:
143 dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
144 if_phy->id, phy_modes(submode));
145 return -EINVAL;
146 }
147
148 static const
149 struct reg_field phy_gmii_sel_fields_am33xx[][PHY_GMII_SEL_LAST] = {
150 {
151 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1),
152 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4),
153 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6),
154 },
155 {
156 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3),
157 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5),
158 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 7, 7),
159 },
160 };
161
162 static const
163 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am33xx = {
164 .num_ports = 2,
165 .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
166 BIT(PHY_GMII_SEL_RMII_IO_CLK_EN),
167 .regfields = phy_gmii_sel_fields_am33xx,
168 };
169
170 static const
171 struct reg_field phy_gmii_sel_fields_dra7[][PHY_GMII_SEL_LAST] = {
172 {
173 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 0, 1),
174 },
175 {
176 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 4, 5),
177 },
178 };
179
180 static const
181 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dra7 = {
182 .num_ports = 2,
183 .regfields = phy_gmii_sel_fields_dra7,
184 };
185
186 static const
187 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = {
188 .num_ports = 2,
189 .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
190 .regfields = phy_gmii_sel_fields_am33xx,
191 };
192
193 static const
194 struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = {
195 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), },
196 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), },
197 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), },
198 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), },
199 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), },
200 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), },
201 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), },
202 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), },
203 };
204
205 static const
206 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
207 .use_of_data = true,
208 .regfields = phy_gmii_sel_fields_am654,
209 };
210
211 static const
212 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
213 .use_of_data = true,
214 .regfields = phy_gmii_sel_fields_am654,
215 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
216 };
217
218 static const struct of_device_id phy_gmii_sel_id_table[] = {
219 {
220 .compatible = "ti,am3352-phy-gmii-sel",
221 .data = &phy_gmii_sel_soc_am33xx,
222 },
223 {
224 .compatible = "ti,dra7xx-phy-gmii-sel",
225 .data = &phy_gmii_sel_soc_dra7,
226 },
227 {
228 .compatible = "ti,am43xx-phy-gmii-sel",
229 .data = &phy_gmii_sel_soc_am33xx,
230 },
231 {
232 .compatible = "ti,dm814-phy-gmii-sel",
233 .data = &phy_gmii_sel_soc_dm814,
234 },
235 {
236 .compatible = "ti,am654-phy-gmii-sel",
237 .data = &phy_gmii_sel_soc_am654,
238 },
239 {
240 .compatible = "ti,j7200-cpsw5g-phy-gmii-sel",
241 .data = &phy_gmii_sel_cpsw5g_soc_j7200,
242 },
243 {}
244 };
245 MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table);
246
247 static const struct phy_ops phy_gmii_sel_ops = {
248 .set_mode = phy_gmii_sel_mode,
249 .owner = THIS_MODULE,
250 };
251
phy_gmii_sel_of_xlate(struct device * dev,struct of_phandle_args * args)252 static struct phy *phy_gmii_sel_of_xlate(struct device *dev,
253 struct of_phandle_args *args)
254 {
255 struct phy_gmii_sel_priv *priv = dev_get_drvdata(dev);
256 int phy_id = args->args[0];
257
258 if (args->args_count < 1)
259 return ERR_PTR(-EINVAL);
260 if (!priv || !priv->if_phys)
261 return ERR_PTR(-ENODEV);
262 if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) &&
263 args->args_count < 2)
264 return ERR_PTR(-EINVAL);
265 if (phy_id > priv->num_ports)
266 return ERR_PTR(-EINVAL);
267 if (phy_id != priv->if_phys[phy_id - 1].id)
268 return ERR_PTR(-EINVAL);
269
270 phy_id--;
271 if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN))
272 priv->if_phys[phy_id].rmii_clock_external = args->args[1];
273 dev_dbg(dev, "%s id:%u ext:%d\n", __func__,
274 priv->if_phys[phy_id].id, args->args[1]);
275
276 return priv->if_phys[phy_id].if_phy;
277 }
278
phy_gmii_init_phy(struct phy_gmii_sel_priv * priv,int port,struct phy_gmii_sel_phy_priv * if_phy)279 static int phy_gmii_init_phy(struct phy_gmii_sel_priv *priv, int port,
280 struct phy_gmii_sel_phy_priv *if_phy)
281 {
282 const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data;
283 struct device *dev = priv->dev;
284 const struct reg_field *fields;
285 struct regmap_field *regfield;
286 struct reg_field field;
287 int ret;
288
289 if_phy->id = port;
290 if_phy->priv = priv;
291
292 fields = soc_data->regfields[port - 1];
293 field = *fields++;
294 field.reg += priv->reg_offset;
295 dev_dbg(dev, "%s field %x %d %d\n", __func__,
296 field.reg, field.msb, field.lsb);
297
298 regfield = devm_regmap_field_alloc(dev, priv->regmap, field);
299 if (IS_ERR(regfield))
300 return PTR_ERR(regfield);
301 if_phy->fields[PHY_GMII_SEL_PORT_MODE] = regfield;
302
303 field = *fields++;
304 field.reg += priv->reg_offset;
305 if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE)) {
306 regfield = devm_regmap_field_alloc(dev,
307 priv->regmap,
308 field);
309 if (IS_ERR(regfield))
310 return PTR_ERR(regfield);
311 if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE] = regfield;
312 dev_dbg(dev, "%s field %x %d %d\n", __func__,
313 field.reg, field.msb, field.lsb);
314 }
315
316 field = *fields;
317 field.reg += priv->reg_offset;
318 if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN)) {
319 regfield = devm_regmap_field_alloc(dev,
320 priv->regmap,
321 field);
322 if (IS_ERR(regfield))
323 return PTR_ERR(regfield);
324 if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN] = regfield;
325 dev_dbg(dev, "%s field %x %d %d\n", __func__,
326 field.reg, field.msb, field.lsb);
327 }
328
329 if_phy->if_phy = devm_phy_create(dev,
330 priv->dev->of_node,
331 &phy_gmii_sel_ops);
332 if (IS_ERR(if_phy->if_phy)) {
333 ret = PTR_ERR(if_phy->if_phy);
334 dev_err(dev, "Failed to create phy%d %d\n", port, ret);
335 return ret;
336 }
337 phy_set_drvdata(if_phy->if_phy, if_phy);
338
339 return 0;
340 }
341
phy_gmii_sel_init_ports(struct phy_gmii_sel_priv * priv)342 static int phy_gmii_sel_init_ports(struct phy_gmii_sel_priv *priv)
343 {
344 const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data;
345 struct phy_gmii_sel_phy_priv *if_phys;
346 struct device *dev = priv->dev;
347 int i, ret;
348
349 if (soc_data->use_of_data) {
350 const __be32 *offset;
351 u64 size;
352
353 offset = of_get_address(dev->of_node, 0, &size, NULL);
354 if (!offset)
355 return -EINVAL;
356 priv->num_ports = size / sizeof(u32);
357 if (!priv->num_ports)
358 return -EINVAL;
359 priv->reg_offset = __be32_to_cpu(*offset);
360 }
361
362 if_phys = devm_kcalloc(dev, priv->num_ports,
363 sizeof(*if_phys), GFP_KERNEL);
364 if (!if_phys)
365 return -ENOMEM;
366 dev_dbg(dev, "%s %d\n", __func__, priv->num_ports);
367
368 for (i = 0; i < priv->num_ports; i++) {
369 ret = phy_gmii_init_phy(priv, i + 1, &if_phys[i]);
370 if (ret)
371 return ret;
372 }
373
374 priv->if_phys = if_phys;
375 return 0;
376 }
377
phy_gmii_sel_probe(struct platform_device * pdev)378 static int phy_gmii_sel_probe(struct platform_device *pdev)
379 {
380 struct device *dev = &pdev->dev;
381 struct device_node *node = dev->of_node;
382 const struct of_device_id *of_id;
383 struct phy_gmii_sel_priv *priv;
384 u32 main_ports = 1;
385 int ret;
386
387 of_id = of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node);
388 if (!of_id)
389 return -EINVAL;
390
391 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
392 if (!priv)
393 return -ENOMEM;
394
395 priv->dev = &pdev->dev;
396 priv->soc_data = of_id->data;
397 priv->num_ports = priv->soc_data->num_ports;
398 of_property_read_u32(node, "ti,qsgmii-main-ports", &main_ports);
399 /*
400 * Ensure that main_ports is within bounds. If the property
401 * ti,qsgmii-main-ports is not mentioned, or the value mentioned
402 * is out of bounds, default to 1.
403 */
404 if (main_ports < 1 || main_ports > 4)
405 main_ports = 1;
406 priv->qsgmii_main_ports = PHY_GMII_PORT(main_ports);
407
408 priv->regmap = syscon_node_to_regmap(node->parent);
409 if (IS_ERR(priv->regmap)) {
410 ret = PTR_ERR(priv->regmap);
411 dev_err(dev, "Failed to get syscon %d\n", ret);
412 return ret;
413 }
414
415 ret = phy_gmii_sel_init_ports(priv);
416 if (ret)
417 return ret;
418
419 dev_set_drvdata(&pdev->dev, priv);
420
421 priv->phy_provider =
422 devm_of_phy_provider_register(dev,
423 phy_gmii_sel_of_xlate);
424 if (IS_ERR(priv->phy_provider)) {
425 ret = PTR_ERR(priv->phy_provider);
426 dev_err(dev, "Failed to create phy provider %d\n", ret);
427 return ret;
428 }
429
430 return 0;
431 }
432
433 static struct platform_driver phy_gmii_sel_driver = {
434 .probe = phy_gmii_sel_probe,
435 .driver = {
436 .name = "phy-gmii-sel",
437 .of_match_table = phy_gmii_sel_id_table,
438 },
439 };
440 module_platform_driver(phy_gmii_sel_driver);
441
442 MODULE_LICENSE("GPL v2");
443 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
444 MODULE_DESCRIPTION("TI CPSW Port's PHY Interface Mode selection Driver");
445