1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Purpose:	PCI Express Port Bus Driver's Internal Data Structures
4  *
5  * Copyright (C) 2004 Intel
6  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7  */
8 
9 #ifndef _PORTDRV_H_
10 #define _PORTDRV_H_
11 
12 #include <linux/compiler.h>
13 
14 /* Service Type */
15 #define PCIE_PORT_SERVICE_PME_SHIFT	0	/* Power Management Event */
16 #define PCIE_PORT_SERVICE_PME		(1 << PCIE_PORT_SERVICE_PME_SHIFT)
17 #define PCIE_PORT_SERVICE_AER_SHIFT	1	/* Advanced Error Reporting */
18 #define PCIE_PORT_SERVICE_AER		(1 << PCIE_PORT_SERVICE_AER_SHIFT)
19 #define PCIE_PORT_SERVICE_HP_SHIFT	2	/* Native Hotplug */
20 #define PCIE_PORT_SERVICE_HP		(1 << PCIE_PORT_SERVICE_HP_SHIFT)
21 #define PCIE_PORT_SERVICE_DPC_SHIFT	3	/* Downstream Port Containment */
22 #define PCIE_PORT_SERVICE_DPC		(1 << PCIE_PORT_SERVICE_DPC_SHIFT)
23 #define PCIE_PORT_SERVICE_BWNOTIF_SHIFT	4	/* Bandwidth notification */
24 #define PCIE_PORT_SERVICE_BWNOTIF	(1 << PCIE_PORT_SERVICE_BWNOTIF_SHIFT)
25 
26 #define PCIE_PORT_DEVICE_MAXSERVICES   5
27 
28 extern bool pcie_ports_dpc_native;
29 
30 #ifdef CONFIG_PCIEAER
31 int pcie_aer_init(void);
32 int pcie_aer_is_native(struct pci_dev *dev);
33 #else
pcie_aer_init(void)34 static inline int pcie_aer_init(void) { return 0; }
pcie_aer_is_native(struct pci_dev * dev)35 static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
36 #endif
37 
38 #ifdef CONFIG_HOTPLUG_PCI_PCIE
39 int pcie_hp_init(void);
40 #else
pcie_hp_init(void)41 static inline int pcie_hp_init(void) { return 0; }
42 #endif
43 
44 #ifdef CONFIG_PCIE_PME
45 int pcie_pme_init(void);
46 #else
pcie_pme_init(void)47 static inline int pcie_pme_init(void) { return 0; }
48 #endif
49 
50 #ifdef CONFIG_PCIE_DPC
51 int pcie_dpc_init(void);
52 #else
pcie_dpc_init(void)53 static inline int pcie_dpc_init(void) { return 0; }
54 #endif
55 
56 /* Port Type */
57 #define PCIE_ANY_PORT			(~0)
58 
59 struct pcie_device {
60 	int		irq;	    /* Service IRQ/MSI/MSI-X Vector */
61 	struct pci_dev *port;	    /* Root/Upstream/Downstream Port */
62 	u32		service;    /* Port service this device represents */
63 	void		*priv_data; /* Service Private Data */
64 	struct device	device;     /* Generic Device Interface */
65 };
66 #define to_pcie_device(d) container_of(d, struct pcie_device, device)
67 
set_service_data(struct pcie_device * dev,void * data)68 static inline void set_service_data(struct pcie_device *dev, void *data)
69 {
70 	dev->priv_data = data;
71 }
72 
get_service_data(struct pcie_device * dev)73 static inline void *get_service_data(struct pcie_device *dev)
74 {
75 	return dev->priv_data;
76 }
77 
78 struct pcie_port_service_driver {
79 	const char *name;
80 	int (*probe)(struct pcie_device *dev);
81 	void (*remove)(struct pcie_device *dev);
82 	int (*suspend)(struct pcie_device *dev);
83 	int (*resume_noirq)(struct pcie_device *dev);
84 	int (*resume)(struct pcie_device *dev);
85 	int (*runtime_suspend)(struct pcie_device *dev);
86 	int (*runtime_resume)(struct pcie_device *dev);
87 
88 	int (*slot_reset)(struct pcie_device *dev);
89 
90 	int port_type;  /* Type of the port this driver can handle */
91 	u32 service;    /* Port service this device represents */
92 
93 	struct device_driver driver;
94 };
95 #define to_service_driver(d) \
96 	container_of(d, struct pcie_port_service_driver, driver)
97 
98 int pcie_port_service_register(struct pcie_port_service_driver *new);
99 void pcie_port_service_unregister(struct pcie_port_service_driver *new);
100 
101 /*
102  * The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
103  * be one of the first 32 MSI-X entries.  Per PCI r3.0, sec 6.8.3.1, MSI
104  * supports a maximum of 32 vectors per function.
105  */
106 #define PCIE_PORT_MAX_MSI_ENTRIES	32
107 
108 #define get_descriptor_id(type, service) (((type - 4) << 8) | service)
109 
110 extern struct bus_type pcie_port_bus_type;
111 int pcie_port_device_register(struct pci_dev *dev);
112 int pcie_port_device_iter(struct device *dev, void *data);
113 #ifdef CONFIG_PM
114 int pcie_port_device_suspend(struct device *dev);
115 int pcie_port_device_resume_noirq(struct device *dev);
116 int pcie_port_device_resume(struct device *dev);
117 int pcie_port_device_runtime_suspend(struct device *dev);
118 int pcie_port_device_runtime_resume(struct device *dev);
119 #endif
120 void pcie_port_device_remove(struct pci_dev *dev);
121 
122 struct pci_dev;
123 
124 #ifdef CONFIG_PCIE_PME
125 extern bool pcie_pme_msi_disabled;
126 
pcie_pme_disable_msi(void)127 static inline void pcie_pme_disable_msi(void)
128 {
129 	pcie_pme_msi_disabled = true;
130 }
131 
pcie_pme_no_msi(void)132 static inline bool pcie_pme_no_msi(void)
133 {
134 	return pcie_pme_msi_disabled;
135 }
136 
137 void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable);
138 #else /* !CONFIG_PCIE_PME */
pcie_pme_disable_msi(void)139 static inline void pcie_pme_disable_msi(void) {}
pcie_pme_no_msi(void)140 static inline bool pcie_pme_no_msi(void) { return false; }
pcie_pme_interrupt_enable(struct pci_dev * dev,bool en)141 static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
142 #endif /* !CONFIG_PCIE_PME */
143 
144 struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
145 #endif /* _PORTDRV_H_ */
146