1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 Baylibre, SAS.
3 * Author: Jerome Brunet <jbrunet@baylibre.com>
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/delay.h>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/device.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/mdio-mux.h>
14 #include <linux/module.h>
15 #include <linux/phy.h>
16 #include <linux/platform_device.h>
17
18 #define ETH_PLL_STS 0x40
19 #define ETH_PLL_CTL0 0x44
20 #define PLL_CTL0_LOCK_DIG BIT(30)
21 #define PLL_CTL0_RST BIT(29)
22 #define PLL_CTL0_EN BIT(28)
23 #define PLL_CTL0_SEL BIT(23)
24 #define PLL_CTL0_N GENMASK(14, 10)
25 #define PLL_CTL0_M GENMASK(8, 0)
26 #define PLL_LOCK_TIMEOUT 1000000
27 #define PLL_MUX_NUM_PARENT 2
28 #define ETH_PLL_CTL1 0x48
29 #define ETH_PLL_CTL2 0x4c
30 #define ETH_PLL_CTL3 0x50
31 #define ETH_PLL_CTL4 0x54
32 #define ETH_PLL_CTL5 0x58
33 #define ETH_PLL_CTL6 0x5c
34 #define ETH_PLL_CTL7 0x60
35
36 #define ETH_PHY_CNTL0 0x80
37 #define EPHY_G12A_ID 0x33010180
38 #define ETH_PHY_CNTL1 0x84
39 #define PHY_CNTL1_ST_MODE GENMASK(2, 0)
40 #define PHY_CNTL1_ST_PHYADD GENMASK(7, 3)
41 #define EPHY_DFLT_ADD 8
42 #define PHY_CNTL1_MII_MODE GENMASK(15, 14)
43 #define EPHY_MODE_RMII 0x1
44 #define PHY_CNTL1_CLK_EN BIT(16)
45 #define PHY_CNTL1_CLKFREQ BIT(17)
46 #define PHY_CNTL1_PHY_ENB BIT(18)
47 #define ETH_PHY_CNTL2 0x88
48 #define PHY_CNTL2_USE_INTERNAL BIT(5)
49 #define PHY_CNTL2_SMI_SRC_MAC BIT(6)
50 #define PHY_CNTL2_RX_CLK_EPHY BIT(9)
51
52 #define MESON_G12A_MDIO_EXTERNAL_ID 0
53 #define MESON_G12A_MDIO_INTERNAL_ID 1
54
55 struct g12a_mdio_mux {
56 bool pll_is_enabled;
57 void __iomem *regs;
58 void *mux_handle;
59 struct clk *pclk;
60 struct clk *pll;
61 };
62
63 struct g12a_ephy_pll {
64 void __iomem *base;
65 struct clk_hw hw;
66 };
67
68 #define g12a_ephy_pll_to_dev(_hw) \
69 container_of(_hw, struct g12a_ephy_pll, hw)
70
g12a_ephy_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)71 static unsigned long g12a_ephy_pll_recalc_rate(struct clk_hw *hw,
72 unsigned long parent_rate)
73 {
74 struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
75 u32 val, m, n;
76
77 val = readl(pll->base + ETH_PLL_CTL0);
78 m = FIELD_GET(PLL_CTL0_M, val);
79 n = FIELD_GET(PLL_CTL0_N, val);
80
81 return parent_rate * m / n;
82 }
83
g12a_ephy_pll_enable(struct clk_hw * hw)84 static int g12a_ephy_pll_enable(struct clk_hw *hw)
85 {
86 struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
87 u32 val = readl(pll->base + ETH_PLL_CTL0);
88
89 /* Apply both enable an reset */
90 val |= PLL_CTL0_RST | PLL_CTL0_EN;
91 writel(val, pll->base + ETH_PLL_CTL0);
92
93 /* Clear the reset to let PLL lock */
94 val &= ~PLL_CTL0_RST;
95 writel(val, pll->base + ETH_PLL_CTL0);
96
97 /* Poll on the digital lock instead of the usual analog lock
98 * This is done because bit 31 is unreliable on some SoC. Bit
99 * 31 may indicate that the PLL is not lock even though the clock
100 * is actually running
101 */
102 return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val,
103 val & PLL_CTL0_LOCK_DIG, 0, PLL_LOCK_TIMEOUT);
104 }
105
g12a_ephy_pll_disable(struct clk_hw * hw)106 static void g12a_ephy_pll_disable(struct clk_hw *hw)
107 {
108 struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
109 u32 val;
110
111 val = readl(pll->base + ETH_PLL_CTL0);
112 val &= ~PLL_CTL0_EN;
113 val |= PLL_CTL0_RST;
114 writel(val, pll->base + ETH_PLL_CTL0);
115 }
116
g12a_ephy_pll_is_enabled(struct clk_hw * hw)117 static int g12a_ephy_pll_is_enabled(struct clk_hw *hw)
118 {
119 struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
120 unsigned int val;
121
122 val = readl(pll->base + ETH_PLL_CTL0);
123
124 return (val & PLL_CTL0_LOCK_DIG) ? 1 : 0;
125 }
126
g12a_ephy_pll_init(struct clk_hw * hw)127 static int g12a_ephy_pll_init(struct clk_hw *hw)
128 {
129 struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
130
131 /* Apply PLL HW settings */
132 writel(0x29c0040a, pll->base + ETH_PLL_CTL0);
133 writel(0x927e0000, pll->base + ETH_PLL_CTL1);
134 writel(0xac5f49e5, pll->base + ETH_PLL_CTL2);
135 writel(0x00000000, pll->base + ETH_PLL_CTL3);
136 writel(0x00000000, pll->base + ETH_PLL_CTL4);
137 writel(0x20200000, pll->base + ETH_PLL_CTL5);
138 writel(0x0000c002, pll->base + ETH_PLL_CTL6);
139 writel(0x00000023, pll->base + ETH_PLL_CTL7);
140
141 return 0;
142 }
143
144 static const struct clk_ops g12a_ephy_pll_ops = {
145 .recalc_rate = g12a_ephy_pll_recalc_rate,
146 .is_enabled = g12a_ephy_pll_is_enabled,
147 .enable = g12a_ephy_pll_enable,
148 .disable = g12a_ephy_pll_disable,
149 .init = g12a_ephy_pll_init,
150 };
151
g12a_enable_internal_mdio(struct g12a_mdio_mux * priv)152 static int g12a_enable_internal_mdio(struct g12a_mdio_mux *priv)
153 {
154 u32 value;
155 int ret;
156
157 /* Enable the phy clock */
158 if (!priv->pll_is_enabled) {
159 ret = clk_prepare_enable(priv->pll);
160 if (ret)
161 return ret;
162 }
163
164 priv->pll_is_enabled = true;
165
166 /* Initialize ephy control */
167 writel(EPHY_G12A_ID, priv->regs + ETH_PHY_CNTL0);
168
169 /* Make sure we get a 0 -> 1 transition on the enable bit */
170 value = FIELD_PREP(PHY_CNTL1_ST_MODE, 3) |
171 FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) |
172 FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) |
173 PHY_CNTL1_CLK_EN |
174 PHY_CNTL1_CLKFREQ;
175 writel(value, priv->regs + ETH_PHY_CNTL1);
176 writel(PHY_CNTL2_USE_INTERNAL |
177 PHY_CNTL2_SMI_SRC_MAC |
178 PHY_CNTL2_RX_CLK_EPHY,
179 priv->regs + ETH_PHY_CNTL2);
180
181 value |= PHY_CNTL1_PHY_ENB;
182 writel(value, priv->regs + ETH_PHY_CNTL1);
183
184 /* The phy needs a bit of time to power up */
185 mdelay(10);
186
187 return 0;
188 }
189
g12a_enable_external_mdio(struct g12a_mdio_mux * priv)190 static int g12a_enable_external_mdio(struct g12a_mdio_mux *priv)
191 {
192 /* Reset the mdio bus mux */
193 writel_relaxed(0x0, priv->regs + ETH_PHY_CNTL2);
194
195 /* Disable the phy clock if enabled */
196 if (priv->pll_is_enabled) {
197 clk_disable_unprepare(priv->pll);
198 priv->pll_is_enabled = false;
199 }
200
201 return 0;
202 }
203
g12a_mdio_switch_fn(int current_child,int desired_child,void * data)204 static int g12a_mdio_switch_fn(int current_child, int desired_child,
205 void *data)
206 {
207 struct g12a_mdio_mux *priv = dev_get_drvdata(data);
208
209 if (current_child == desired_child)
210 return 0;
211
212 switch (desired_child) {
213 case MESON_G12A_MDIO_EXTERNAL_ID:
214 return g12a_enable_external_mdio(priv);
215 case MESON_G12A_MDIO_INTERNAL_ID:
216 return g12a_enable_internal_mdio(priv);
217 default:
218 return -EINVAL;
219 }
220 }
221
222 static const struct of_device_id g12a_mdio_mux_match[] = {
223 { .compatible = "amlogic,g12a-mdio-mux", },
224 {},
225 };
226 MODULE_DEVICE_TABLE(of, g12a_mdio_mux_match);
227
g12a_ephy_glue_clk_register(struct device * dev)228 static int g12a_ephy_glue_clk_register(struct device *dev)
229 {
230 struct g12a_mdio_mux *priv = dev_get_drvdata(dev);
231 const char *parent_names[PLL_MUX_NUM_PARENT];
232 struct clk_init_data init;
233 struct g12a_ephy_pll *pll;
234 struct clk_mux *mux;
235 struct clk *clk;
236 char *name;
237 int i;
238
239 /* get the mux parents */
240 for (i = 0; i < PLL_MUX_NUM_PARENT; i++) {
241 char in_name[8];
242
243 snprintf(in_name, sizeof(in_name), "clkin%d", i);
244 clk = devm_clk_get(dev, in_name);
245 if (IS_ERR(clk))
246 return dev_err_probe(dev, PTR_ERR(clk),
247 "Missing clock %s\n", in_name);
248
249 parent_names[i] = __clk_get_name(clk);
250 }
251
252 /* create the input mux */
253 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
254 if (!mux)
255 return -ENOMEM;
256
257 name = kasprintf(GFP_KERNEL, "%s#mux", dev_name(dev));
258 if (!name)
259 return -ENOMEM;
260
261 init.name = name;
262 init.ops = &clk_mux_ro_ops;
263 init.flags = 0;
264 init.parent_names = parent_names;
265 init.num_parents = PLL_MUX_NUM_PARENT;
266
267 mux->reg = priv->regs + ETH_PLL_CTL0;
268 mux->shift = __ffs(PLL_CTL0_SEL);
269 mux->mask = PLL_CTL0_SEL >> mux->shift;
270 mux->hw.init = &init;
271
272 clk = devm_clk_register(dev, &mux->hw);
273 kfree(name);
274 if (IS_ERR(clk)) {
275 dev_err(dev, "failed to register input mux\n");
276 return PTR_ERR(clk);
277 }
278
279 /* create the pll */
280 pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
281 if (!pll)
282 return -ENOMEM;
283
284 name = kasprintf(GFP_KERNEL, "%s#pll", dev_name(dev));
285 if (!name)
286 return -ENOMEM;
287
288 init.name = name;
289 init.ops = &g12a_ephy_pll_ops;
290 init.flags = 0;
291 parent_names[0] = __clk_get_name(clk);
292 init.parent_names = parent_names;
293 init.num_parents = 1;
294
295 pll->base = priv->regs;
296 pll->hw.init = &init;
297
298 clk = devm_clk_register(dev, &pll->hw);
299 kfree(name);
300 if (IS_ERR(clk)) {
301 dev_err(dev, "failed to register input mux\n");
302 return PTR_ERR(clk);
303 }
304
305 priv->pll = clk;
306
307 return 0;
308 }
309
g12a_mdio_mux_probe(struct platform_device * pdev)310 static int g12a_mdio_mux_probe(struct platform_device *pdev)
311 {
312 struct device *dev = &pdev->dev;
313 struct g12a_mdio_mux *priv;
314 int ret;
315
316 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
317 if (!priv)
318 return -ENOMEM;
319
320 platform_set_drvdata(pdev, priv);
321
322 priv->regs = devm_platform_ioremap_resource(pdev, 0);
323 if (IS_ERR(priv->regs))
324 return PTR_ERR(priv->regs);
325
326 priv->pclk = devm_clk_get(dev, "pclk");
327 if (IS_ERR(priv->pclk))
328 return dev_err_probe(dev, PTR_ERR(priv->pclk),
329 "failed to get peripheral clock\n");
330
331 /* Make sure the device registers are clocked */
332 ret = clk_prepare_enable(priv->pclk);
333 if (ret) {
334 dev_err(dev, "failed to enable peripheral clock");
335 return ret;
336 }
337
338 /* Register PLL in CCF */
339 ret = g12a_ephy_glue_clk_register(dev);
340 if (ret)
341 goto err;
342
343 ret = mdio_mux_init(dev, dev->of_node, g12a_mdio_switch_fn,
344 &priv->mux_handle, dev, NULL);
345 if (ret) {
346 dev_err_probe(dev, ret, "mdio multiplexer init failed\n");
347 goto err;
348 }
349
350 return 0;
351
352 err:
353 clk_disable_unprepare(priv->pclk);
354 return ret;
355 }
356
g12a_mdio_mux_remove(struct platform_device * pdev)357 static int g12a_mdio_mux_remove(struct platform_device *pdev)
358 {
359 struct g12a_mdio_mux *priv = platform_get_drvdata(pdev);
360
361 mdio_mux_uninit(priv->mux_handle);
362
363 if (priv->pll_is_enabled)
364 clk_disable_unprepare(priv->pll);
365
366 clk_disable_unprepare(priv->pclk);
367
368 return 0;
369 }
370
371 static struct platform_driver g12a_mdio_mux_driver = {
372 .probe = g12a_mdio_mux_probe,
373 .remove = g12a_mdio_mux_remove,
374 .driver = {
375 .name = "g12a-mdio_mux",
376 .of_match_table = g12a_mdio_mux_match,
377 },
378 };
379 module_platform_driver(g12a_mdio_mux_driver);
380
381 MODULE_DESCRIPTION("Amlogic G12a MDIO multiplexer driver");
382 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
383 MODULE_LICENSE("GPL v2");
384