1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88E6xxx Switch Port Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/if_bridge.h>
13 #include <linux/phy.h>
14 #include <linux/phylink.h>
15
16 #include "chip.h"
17 #include "global2.h"
18 #include "port.h"
19 #include "serdes.h"
20
mv88e6xxx_port_read(struct mv88e6xxx_chip * chip,int port,int reg,u16 * val)21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
22 u16 *val)
23 {
24 int addr = chip->info->port_base_addr + port;
25
26 return mv88e6xxx_read(chip, addr, reg, val);
27 }
28
mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip * chip,int port,int reg,int bit,int val)29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
30 int bit, int val)
31 {
32 int addr = chip->info->port_base_addr + port;
33
34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val);
35 }
36
mv88e6xxx_port_write(struct mv88e6xxx_chip * chip,int port,int reg,u16 val)37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
38 u16 val)
39 {
40 int addr = chip->info->port_base_addr + port;
41
42 return mv88e6xxx_write(chip, addr, reg, val);
43 }
44
45 /* Offset 0x00: MAC (or PCS or Physical) Status Register
46 *
47 * For most devices, this is read only. However the 6185 has the MyPause
48 * bit read/write.
49 */
mv88e6185_port_set_pause(struct mv88e6xxx_chip * chip,int port,int pause)50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
51 int pause)
52 {
53 u16 reg;
54 int err;
55
56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
57 if (err)
58 return err;
59
60 if (pause)
61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
62 else
63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
64
65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
66 }
67
68 /* Offset 0x01: MAC (or PCS or Physical) Control Register
69 *
70 * Link, Duplex and Flow Control have one force bit, one value bit.
71 *
72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
73 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
74 * Newer chips need a ForcedSpd bit 13 set to consider the value.
75 */
76
mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip * chip,int port,phy_interface_t mode)77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
78 phy_interface_t mode)
79 {
80 u16 reg;
81 int err;
82
83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
84 if (err)
85 return err;
86
87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
88 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
89
90 switch (mode) {
91 case PHY_INTERFACE_MODE_RGMII_RXID:
92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
93 break;
94 case PHY_INTERFACE_MODE_RGMII_TXID:
95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
96 break;
97 case PHY_INTERFACE_MODE_RGMII_ID:
98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
99 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
100 break;
101 case PHY_INTERFACE_MODE_RGMII:
102 break;
103 default:
104 return 0;
105 }
106
107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
108 if (err)
109 return err;
110
111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
114
115 return 0;
116 }
117
mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip * chip,int port,phy_interface_t mode)118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
119 phy_interface_t mode)
120 {
121 if (port < 5)
122 return -EOPNOTSUPP;
123
124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
125 }
126
mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip * chip,int port,phy_interface_t mode)127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
128 phy_interface_t mode)
129 {
130 if (port != 0)
131 return -EOPNOTSUPP;
132
133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
134 }
135
mv88e6xxx_port_set_link(struct mv88e6xxx_chip * chip,int port,int link)136 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
137 {
138 u16 reg;
139 int err;
140
141 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
142 if (err)
143 return err;
144
145 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
146 MV88E6XXX_PORT_MAC_CTL_LINK_UP);
147
148 switch (link) {
149 case LINK_FORCED_DOWN:
150 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
151 break;
152 case LINK_FORCED_UP:
153 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
154 MV88E6XXX_PORT_MAC_CTL_LINK_UP;
155 break;
156 case LINK_UNFORCED:
157 /* normal link detection */
158 break;
159 default:
160 return -EINVAL;
161 }
162
163 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
164 if (err)
165 return err;
166
167 dev_dbg(chip->dev, "p%d: %s link %s\n", port,
168 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
169 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
170
171 return 0;
172 }
173
mv88e6xxx_port_sync_link(struct mv88e6xxx_chip * chip,int port,unsigned int mode,bool isup)174 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
175 {
176 const struct mv88e6xxx_ops *ops = chip->info->ops;
177 int err = 0;
178 int link;
179
180 if (isup)
181 link = LINK_FORCED_UP;
182 else
183 link = LINK_FORCED_DOWN;
184
185 if (ops->port_set_link)
186 err = ops->port_set_link(chip, port, link);
187
188 return err;
189 }
190
mv88e6185_port_sync_link(struct mv88e6xxx_chip * chip,int port,unsigned int mode,bool isup)191 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
192 {
193 const struct mv88e6xxx_ops *ops = chip->info->ops;
194 int err = 0;
195 int link;
196
197 if (mode == MLO_AN_INBAND)
198 link = LINK_UNFORCED;
199 else if (isup)
200 link = LINK_FORCED_UP;
201 else
202 link = LINK_FORCED_DOWN;
203
204 if (ops->port_set_link)
205 err = ops->port_set_link(chip, port, link);
206
207 return err;
208 }
209
mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip * chip,int port,int speed,bool alt_bit,bool force_bit,int duplex)210 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip,
211 int port, int speed, bool alt_bit,
212 bool force_bit, int duplex)
213 {
214 u16 reg, ctrl;
215 int err;
216
217 switch (speed) {
218 case 10:
219 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
220 break;
221 case 100:
222 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
223 break;
224 case 200:
225 if (alt_bit)
226 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
227 MV88E6390_PORT_MAC_CTL_ALTSPEED;
228 else
229 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
230 break;
231 case 1000:
232 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
233 break;
234 case 2500:
235 if (alt_bit)
236 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
237 MV88E6390_PORT_MAC_CTL_ALTSPEED;
238 else
239 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000;
240 break;
241 case 10000:
242 /* all bits set, fall through... */
243 case SPEED_UNFORCED:
244 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
245 break;
246 default:
247 return -EOPNOTSUPP;
248 }
249
250 switch (duplex) {
251 case DUPLEX_HALF:
252 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
253 break;
254 case DUPLEX_FULL:
255 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
256 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
257 break;
258 case DUPLEX_UNFORCED:
259 /* normal duplex detection */
260 break;
261 default:
262 return -EOPNOTSUPP;
263 }
264
265 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
266 if (err)
267 return err;
268
269 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
270 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
271 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
272
273 if (alt_bit)
274 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
275 if (force_bit) {
276 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
277 if (speed != SPEED_UNFORCED)
278 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
279 }
280 reg |= ctrl;
281
282 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
283 if (err)
284 return err;
285
286 if (speed != SPEED_UNFORCED)
287 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
288 else
289 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
290 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
291 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
292 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
293
294 return 0;
295 }
296
297 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip * chip,int port,int speed,int duplex)298 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
299 int speed, int duplex)
300 {
301 if (speed == 200 || speed > 1000)
302 return -EOPNOTSUPP;
303
304 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
305 duplex);
306 }
307
308 /* Support 10, 100 Mbps (e.g. 88E6250 family) */
mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip * chip,int port,int speed,int duplex)309 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
310 int speed, int duplex)
311 {
312 if (speed > 100)
313 return -EOPNOTSUPP;
314
315 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
316 duplex);
317 }
318
319 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */
mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip * chip,int port,int speed,int duplex)320 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
321 int speed, int duplex)
322 {
323 if (speed > 2500)
324 return -EOPNOTSUPP;
325
326 if (speed == 200 && port != 0)
327 return -EOPNOTSUPP;
328
329 if (speed == 2500 && port < 5)
330 return -EOPNOTSUPP;
331
332 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true,
333 duplex);
334 }
335
mv88e6341_port_max_speed_mode(int port)336 phy_interface_t mv88e6341_port_max_speed_mode(int port)
337 {
338 if (port == 5)
339 return PHY_INTERFACE_MODE_2500BASEX;
340
341 return PHY_INTERFACE_MODE_NA;
342 }
343
344 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip * chip,int port,int speed,int duplex)345 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
346 int speed, int duplex)
347 {
348 if (speed > 1000)
349 return -EOPNOTSUPP;
350
351 if (speed == 200 && port < 5)
352 return -EOPNOTSUPP;
353
354 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false,
355 duplex);
356 }
357
358 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip * chip,int port,int speed,int duplex)359 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
360 int speed, int duplex)
361 {
362 if (speed > 2500)
363 return -EOPNOTSUPP;
364
365 if (speed == 200 && port != 0)
366 return -EOPNOTSUPP;
367
368 if (speed == 2500 && port < 9)
369 return -EOPNOTSUPP;
370
371 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
372 duplex);
373 }
374
mv88e6390_port_max_speed_mode(int port)375 phy_interface_t mv88e6390_port_max_speed_mode(int port)
376 {
377 if (port == 9 || port == 10)
378 return PHY_INTERFACE_MODE_2500BASEX;
379
380 return PHY_INTERFACE_MODE_NA;
381 }
382
383 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip * chip,int port,int speed,int duplex)384 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
385 int speed, int duplex)
386 {
387 if (speed == 200 && port != 0)
388 return -EOPNOTSUPP;
389
390 if (speed >= 2500 && port < 9)
391 return -EOPNOTSUPP;
392
393 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
394 duplex);
395 }
396
mv88e6390x_port_max_speed_mode(int port)397 phy_interface_t mv88e6390x_port_max_speed_mode(int port)
398 {
399 if (port == 9 || port == 10)
400 return PHY_INTERFACE_MODE_XAUI;
401
402 return PHY_INTERFACE_MODE_NA;
403 }
404
405 /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X)
406 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register
407 * values for speeds 2500 & 5000 conflict.
408 */
mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip * chip,int port,int speed,int duplex)409 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
410 int speed, int duplex)
411 {
412 u16 reg, ctrl;
413 int err;
414
415 if (speed == 200 && port != 0)
416 return -EOPNOTSUPP;
417
418 if (speed >= 2500 && port > 0 && port < 9)
419 return -EOPNOTSUPP;
420
421 switch (speed) {
422 case 10:
423 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
424 break;
425 case 100:
426 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
427 break;
428 case 200:
429 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
430 MV88E6390_PORT_MAC_CTL_ALTSPEED;
431 break;
432 case 1000:
433 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
434 break;
435 case 2500:
436 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 |
437 MV88E6390_PORT_MAC_CTL_ALTSPEED;
438 break;
439 case 5000:
440 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
441 MV88E6390_PORT_MAC_CTL_ALTSPEED;
442 break;
443 case 10000:
444 case SPEED_UNFORCED:
445 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
446 break;
447 default:
448 return -EOPNOTSUPP;
449 }
450
451 switch (duplex) {
452 case DUPLEX_HALF:
453 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
454 break;
455 case DUPLEX_FULL:
456 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
457 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
458 break;
459 case DUPLEX_UNFORCED:
460 /* normal duplex detection */
461 break;
462 default:
463 return -EOPNOTSUPP;
464 }
465
466 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
467 if (err)
468 return err;
469
470 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
471 MV88E6390_PORT_MAC_CTL_ALTSPEED |
472 MV88E6390_PORT_MAC_CTL_FORCE_SPEED);
473
474 if (speed != SPEED_UNFORCED)
475 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
476
477 reg |= ctrl;
478
479 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
480 if (err)
481 return err;
482
483 if (speed != SPEED_UNFORCED)
484 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
485 else
486 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
487 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
488 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
489 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
490
491 return 0;
492 }
493
mv88e6393x_port_max_speed_mode(int port)494 phy_interface_t mv88e6393x_port_max_speed_mode(int port)
495 {
496 if (port == 0 || port == 9 || port == 10)
497 return PHY_INTERFACE_MODE_10GBASER;
498
499 return PHY_INTERFACE_MODE_NA;
500 }
501
mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip * chip,int port,phy_interface_t mode,bool force)502 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
503 phy_interface_t mode, bool force)
504 {
505 u16 cmode;
506 int lane;
507 u16 reg;
508 int err;
509
510 /* Default to a slow mode, so freeing up SERDES interfaces for
511 * other ports which might use them for SFPs.
512 */
513 if (mode == PHY_INTERFACE_MODE_NA)
514 mode = PHY_INTERFACE_MODE_1000BASEX;
515
516 switch (mode) {
517 case PHY_INTERFACE_MODE_RMII:
518 cmode = MV88E6XXX_PORT_STS_CMODE_RMII;
519 break;
520 case PHY_INTERFACE_MODE_RGMII:
521 case PHY_INTERFACE_MODE_RGMII_ID:
522 case PHY_INTERFACE_MODE_RGMII_RXID:
523 case PHY_INTERFACE_MODE_RGMII_TXID:
524 cmode = MV88E6XXX_PORT_STS_CMODE_RGMII;
525 break;
526 case PHY_INTERFACE_MODE_1000BASEX:
527 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX;
528 break;
529 case PHY_INTERFACE_MODE_SGMII:
530 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
531 break;
532 case PHY_INTERFACE_MODE_2500BASEX:
533 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
534 break;
535 case PHY_INTERFACE_MODE_5GBASER:
536 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER;
537 break;
538 case PHY_INTERFACE_MODE_XGMII:
539 case PHY_INTERFACE_MODE_XAUI:
540 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
541 break;
542 case PHY_INTERFACE_MODE_RXAUI:
543 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
544 break;
545 case PHY_INTERFACE_MODE_10GBASER:
546 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER;
547 break;
548 default:
549 cmode = 0;
550 }
551
552 /* cmode doesn't change, nothing to do for us unless forced */
553 if (cmode == chip->ports[port].cmode && !force)
554 return 0;
555
556 lane = mv88e6xxx_serdes_get_lane(chip, port);
557 if (lane >= 0) {
558 if (chip->ports[port].serdes_irq) {
559 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
560 if (err)
561 return err;
562 }
563
564 err = mv88e6xxx_serdes_power_down(chip, port, lane);
565 if (err)
566 return err;
567 }
568
569 chip->ports[port].cmode = 0;
570
571 if (cmode) {
572 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
573 if (err)
574 return err;
575
576 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
577 reg |= cmode;
578
579 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
580 if (err)
581 return err;
582
583 chip->ports[port].cmode = cmode;
584
585 lane = mv88e6xxx_serdes_get_lane(chip, port);
586 if (lane == -ENODEV)
587 return 0;
588 if (lane < 0)
589 return lane;
590
591 err = mv88e6xxx_serdes_power_up(chip, port, lane);
592 if (err)
593 return err;
594
595 if (chip->ports[port].serdes_irq) {
596 err = mv88e6xxx_serdes_irq_enable(chip, port, lane);
597 if (err)
598 return err;
599 }
600 }
601
602 return 0;
603 }
604
mv88e6390x_port_set_cmode(struct mv88e6xxx_chip * chip,int port,phy_interface_t mode)605 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
606 phy_interface_t mode)
607 {
608 if (port != 9 && port != 10)
609 return -EOPNOTSUPP;
610
611 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
612 }
613
mv88e6390_port_set_cmode(struct mv88e6xxx_chip * chip,int port,phy_interface_t mode)614 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
615 phy_interface_t mode)
616 {
617 if (port != 9 && port != 10)
618 return -EOPNOTSUPP;
619
620 switch (mode) {
621 case PHY_INTERFACE_MODE_NA:
622 return 0;
623 case PHY_INTERFACE_MODE_XGMII:
624 case PHY_INTERFACE_MODE_XAUI:
625 case PHY_INTERFACE_MODE_RXAUI:
626 return -EINVAL;
627 default:
628 break;
629 }
630
631 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
632 }
633
mv88e6393x_port_set_cmode(struct mv88e6xxx_chip * chip,int port,phy_interface_t mode)634 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
635 phy_interface_t mode)
636 {
637 int err;
638 u16 reg;
639
640 if (port != 0 && port != 9 && port != 10)
641 return -EOPNOTSUPP;
642
643 if (port == 9 || port == 10) {
644 switch (mode) {
645 case PHY_INTERFACE_MODE_RMII:
646 case PHY_INTERFACE_MODE_RGMII:
647 case PHY_INTERFACE_MODE_RGMII_ID:
648 case PHY_INTERFACE_MODE_RGMII_RXID:
649 case PHY_INTERFACE_MODE_RGMII_TXID:
650 return -EINVAL;
651 default:
652 break;
653 }
654 }
655
656 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */
657 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
658 if (err)
659 return err;
660
661 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE;
662 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE;
663 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
664 if (err)
665 return err;
666
667 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
668 }
669
mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip * chip,int port)670 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip,
671 int port)
672 {
673 int err, addr;
674 u16 reg, bits;
675
676 if (port != 5)
677 return -EOPNOTSUPP;
678
679 addr = chip->info->port_base_addr + port;
680
681 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®);
682 if (err)
683 return err;
684
685 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE |
686 MV88E6341_PORT_RESERVED_1A_SGMII_AN;
687
688 if ((reg & bits) == bits)
689 return 0;
690
691 reg |= bits;
692 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg);
693 }
694
mv88e6341_port_set_cmode(struct mv88e6xxx_chip * chip,int port,phy_interface_t mode)695 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
696 phy_interface_t mode)
697 {
698 int err;
699
700 if (port != 5)
701 return -EOPNOTSUPP;
702
703 switch (mode) {
704 case PHY_INTERFACE_MODE_NA:
705 return 0;
706 case PHY_INTERFACE_MODE_XGMII:
707 case PHY_INTERFACE_MODE_XAUI:
708 case PHY_INTERFACE_MODE_RXAUI:
709 return -EINVAL;
710 default:
711 break;
712 }
713
714 err = mv88e6341_port_set_cmode_writable(chip, port);
715 if (err)
716 return err;
717
718 return mv88e6xxx_port_set_cmode(chip, port, mode, true);
719 }
720
mv88e6185_port_get_cmode(struct mv88e6xxx_chip * chip,int port,u8 * cmode)721 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
722 {
723 int err;
724 u16 reg;
725
726 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
727 if (err)
728 return err;
729
730 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
731
732 return 0;
733 }
734
mv88e6352_port_get_cmode(struct mv88e6xxx_chip * chip,int port,u8 * cmode)735 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
736 {
737 int err;
738 u16 reg;
739
740 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
741 if (err)
742 return err;
743
744 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
745
746 return 0;
747 }
748
749 /* Offset 0x02: Jamming Control
750 *
751 * Do not limit the period of time that this port can be paused for by
752 * the remote end or the period of time that this port can pause the
753 * remote end.
754 */
mv88e6097_port_pause_limit(struct mv88e6xxx_chip * chip,int port,u8 in,u8 out)755 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
756 u8 out)
757 {
758 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
759 out << 8 | in);
760 }
761
mv88e6390_port_pause_limit(struct mv88e6xxx_chip * chip,int port,u8 in,u8 out)762 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
763 u8 out)
764 {
765 int err;
766
767 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
768 MV88E6390_PORT_FLOW_CTL_UPDATE |
769 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
770 if (err)
771 return err;
772
773 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
774 MV88E6390_PORT_FLOW_CTL_UPDATE |
775 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
776 }
777
778 /* Offset 0x04: Port Control Register */
779
780 static const char * const mv88e6xxx_port_state_names[] = {
781 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
782 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
783 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
784 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
785 };
786
mv88e6xxx_port_set_state(struct mv88e6xxx_chip * chip,int port,u8 state)787 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
788 {
789 u16 reg;
790 int err;
791
792 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
793 if (err)
794 return err;
795
796 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
797
798 switch (state) {
799 case BR_STATE_DISABLED:
800 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
801 break;
802 case BR_STATE_BLOCKING:
803 case BR_STATE_LISTENING:
804 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
805 break;
806 case BR_STATE_LEARNING:
807 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
808 break;
809 case BR_STATE_FORWARDING:
810 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
811 break;
812 default:
813 return -EINVAL;
814 }
815
816 reg |= state;
817
818 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
819 if (err)
820 return err;
821
822 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
823 mv88e6xxx_port_state_names[state]);
824
825 return 0;
826 }
827
mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_egress_mode mode)828 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
829 enum mv88e6xxx_egress_mode mode)
830 {
831 int err;
832 u16 reg;
833
834 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
835 if (err)
836 return err;
837
838 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
839
840 switch (mode) {
841 case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
842 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
843 break;
844 case MV88E6XXX_EGRESS_MODE_UNTAGGED:
845 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
846 break;
847 case MV88E6XXX_EGRESS_MODE_TAGGED:
848 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
849 break;
850 case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
851 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
852 break;
853 default:
854 return -EINVAL;
855 }
856
857 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
858 }
859
mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode mode)860 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
861 enum mv88e6xxx_frame_mode mode)
862 {
863 int err;
864 u16 reg;
865
866 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
867 if (err)
868 return err;
869
870 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
871
872 switch (mode) {
873 case MV88E6XXX_FRAME_MODE_NORMAL:
874 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
875 break;
876 case MV88E6XXX_FRAME_MODE_DSA:
877 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
878 break;
879 default:
880 return -EINVAL;
881 }
882
883 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
884 }
885
mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode mode)886 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
887 enum mv88e6xxx_frame_mode mode)
888 {
889 int err;
890 u16 reg;
891
892 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
893 if (err)
894 return err;
895
896 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
897
898 switch (mode) {
899 case MV88E6XXX_FRAME_MODE_NORMAL:
900 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
901 break;
902 case MV88E6XXX_FRAME_MODE_DSA:
903 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
904 break;
905 case MV88E6XXX_FRAME_MODE_PROVIDER:
906 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
907 break;
908 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
909 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
910 break;
911 default:
912 return -EINVAL;
913 }
914
915 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
916 }
917
mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip * chip,int port,bool unicast)918 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
919 int port, bool unicast)
920 {
921 int err;
922 u16 reg;
923
924 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
925 if (err)
926 return err;
927
928 if (unicast)
929 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
930 else
931 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
932
933 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
934 }
935
mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip * chip,int port,bool unicast)936 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
937 bool unicast)
938 {
939 int err;
940 u16 reg;
941
942 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
943 if (err)
944 return err;
945
946 if (unicast)
947 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
948 else
949 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
950
951 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
952 }
953
mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip * chip,int port,bool multicast)954 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
955 bool multicast)
956 {
957 int err;
958 u16 reg;
959
960 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
961 if (err)
962 return err;
963
964 if (multicast)
965 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
966 else
967 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
968
969 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
970 }
971
972 /* Offset 0x05: Port Control 1 */
973
mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip * chip,int port,bool message_port)974 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
975 bool message_port)
976 {
977 u16 val;
978 int err;
979
980 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
981 if (err)
982 return err;
983
984 if (message_port)
985 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
986 else
987 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
988
989 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
990 }
991
mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip * chip,int port,bool trunk,u8 id)992 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
993 bool trunk, u8 id)
994 {
995 u16 val;
996 int err;
997
998 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
999 if (err)
1000 return err;
1001
1002 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK;
1003
1004 if (trunk)
1005 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT |
1006 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT);
1007 else
1008 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT;
1009
1010 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
1011 }
1012
1013 /* Offset 0x06: Port Based VLAN Map */
1014
mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip * chip,int port,u16 map)1015 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
1016 {
1017 const u16 mask = mv88e6xxx_port_mask(chip);
1018 u16 reg;
1019 int err;
1020
1021 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1022 if (err)
1023 return err;
1024
1025 reg &= ~mask;
1026 reg |= map & mask;
1027
1028 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1029 if (err)
1030 return err;
1031
1032 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
1033
1034 return 0;
1035 }
1036
mv88e6xxx_port_get_fid(struct mv88e6xxx_chip * chip,int port,u16 * fid)1037 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
1038 {
1039 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1040 u16 reg;
1041 int err;
1042
1043 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1044 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1045 if (err)
1046 return err;
1047
1048 *fid = (reg & 0xf000) >> 12;
1049
1050 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1051 if (upper_mask) {
1052 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1053 ®);
1054 if (err)
1055 return err;
1056
1057 *fid |= (reg & upper_mask) << 4;
1058 }
1059
1060 return 0;
1061 }
1062
mv88e6xxx_port_set_fid(struct mv88e6xxx_chip * chip,int port,u16 fid)1063 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
1064 {
1065 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1066 u16 reg;
1067 int err;
1068
1069 if (fid >= mv88e6xxx_num_databases(chip))
1070 return -EINVAL;
1071
1072 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1073 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
1074 if (err)
1075 return err;
1076
1077 reg &= 0x0fff;
1078 reg |= (fid & 0x000f) << 12;
1079
1080 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1081 if (err)
1082 return err;
1083
1084 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1085 if (upper_mask) {
1086 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1087 ®);
1088 if (err)
1089 return err;
1090
1091 reg &= ~upper_mask;
1092 reg |= (fid >> 4) & upper_mask;
1093
1094 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
1095 reg);
1096 if (err)
1097 return err;
1098 }
1099
1100 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
1101
1102 return 0;
1103 }
1104
1105 /* Offset 0x07: Default Port VLAN ID & Priority */
1106
mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip * chip,int port,u16 * pvid)1107 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
1108 {
1109 u16 reg;
1110 int err;
1111
1112 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1113 ®);
1114 if (err)
1115 return err;
1116
1117 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1118
1119 return 0;
1120 }
1121
mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip * chip,int port,u16 pvid)1122 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
1123 {
1124 u16 reg;
1125 int err;
1126
1127 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1128 ®);
1129 if (err)
1130 return err;
1131
1132 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1133 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1134
1135 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1136 reg);
1137 if (err)
1138 return err;
1139
1140 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
1141
1142 return 0;
1143 }
1144
1145 /* Offset 0x08: Port Control 2 Register */
1146
1147 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1148 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
1149 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
1150 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
1151 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
1152 };
1153
mv88e6185_port_set_default_forward(struct mv88e6xxx_chip * chip,int port,bool multicast)1154 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
1155 int port, bool multicast)
1156 {
1157 int err;
1158 u16 reg;
1159
1160 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1161 if (err)
1162 return err;
1163
1164 if (multicast)
1165 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1166 else
1167 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1168
1169 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1170 }
1171
mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip * chip,int port,int upstream_port)1172 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1173 int upstream_port)
1174 {
1175 int err;
1176 u16 reg;
1177
1178 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1179 if (err)
1180 return err;
1181
1182 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
1183 reg |= upstream_port;
1184
1185 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1186 }
1187
mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_egress_direction direction,bool mirror)1188 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
1189 enum mv88e6xxx_egress_direction direction,
1190 bool mirror)
1191 {
1192 bool *mirror_port;
1193 u16 reg;
1194 u16 bit;
1195 int err;
1196
1197 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1198 if (err)
1199 return err;
1200
1201 switch (direction) {
1202 case MV88E6XXX_EGRESS_DIR_INGRESS:
1203 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR;
1204 mirror_port = &chip->ports[port].mirror_ingress;
1205 break;
1206 case MV88E6XXX_EGRESS_DIR_EGRESS:
1207 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR;
1208 mirror_port = &chip->ports[port].mirror_egress;
1209 break;
1210 default:
1211 return -EINVAL;
1212 }
1213
1214 reg &= ~bit;
1215 if (mirror)
1216 reg |= bit;
1217
1218 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1219 if (!err)
1220 *mirror_port = mirror;
1221
1222 return err;
1223 }
1224
mv88e6xxx_port_set_lock(struct mv88e6xxx_chip * chip,int port,bool locked)1225 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,
1226 bool locked)
1227 {
1228 u16 reg;
1229 int err;
1230
1231 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
1232 if (err)
1233 return err;
1234
1235 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK;
1236 if (locked)
1237 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK;
1238
1239 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1240 if (err)
1241 return err;
1242
1243 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®);
1244 if (err)
1245 return err;
1246
1247 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1248 if (locked)
1249 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1250
1251 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg);
1252 }
1253
mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip * chip,int port,u16 mode)1254 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
1255 u16 mode)
1256 {
1257 u16 reg;
1258 int err;
1259
1260 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1261 if (err)
1262 return err;
1263
1264 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1265 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1266
1267 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1268 if (err)
1269 return err;
1270
1271 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1272 mv88e6xxx_port_8021q_mode_names[mode]);
1273
1274 return 0;
1275 }
1276
mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip * chip,int port,bool drop_untagged)1277 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
1278 bool drop_untagged)
1279 {
1280 u16 old, new;
1281 int err;
1282
1283 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old);
1284 if (err)
1285 return err;
1286
1287 if (drop_untagged)
1288 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;
1289 else
1290 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;
1291
1292 if (new == old)
1293 return 0;
1294
1295 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new);
1296 }
1297
mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip * chip,int port,bool map)1298 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map)
1299 {
1300 u16 reg;
1301 int err;
1302
1303 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1304 if (err)
1305 return err;
1306
1307 if (map)
1308 reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
1309 else
1310 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA;
1311
1312 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1313 }
1314
mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip * chip,int port,size_t size)1315 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1316 size_t size)
1317 {
1318 u16 reg;
1319 int err;
1320
1321 size += VLAN_ETH_HLEN + ETH_FCS_LEN;
1322
1323 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1324 if (err)
1325 return err;
1326
1327 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
1328
1329 if (size <= 1522)
1330 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
1331 else if (size <= 2048)
1332 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
1333 else if (size <= 10240)
1334 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
1335 else
1336 return -ERANGE;
1337
1338 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1339 }
1340
1341 /* Offset 0x09: Port Rate Control */
1342
mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip * chip,int port)1343 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1344 {
1345 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1346 0x0000);
1347 }
1348
mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip * chip,int port)1349 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1350 {
1351 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1352 0x0001);
1353 }
1354
1355 /* Offset 0x0B: Port Association Vector */
1356
mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip * chip,int port,u16 pav)1357 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
1358 u16 pav)
1359 {
1360 u16 reg, mask;
1361 int err;
1362
1363 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1364 ®);
1365 if (err)
1366 return err;
1367
1368 mask = mv88e6xxx_port_mask(chip);
1369 reg &= ~mask;
1370 reg |= pav & mask;
1371
1372 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1373 reg);
1374 }
1375
1376 /* Offset 0x0C: Port ATU Control */
1377
mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip * chip,int port)1378 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1379 {
1380 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1381 }
1382
1383 /* Offset 0x0D: (Priority) Override Register */
1384
mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip * chip,int port)1385 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1386 {
1387 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1388 }
1389
1390 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */
1391
mv88e6393x_port_policy_read(struct mv88e6xxx_chip * chip,int port,u16 pointer,u8 * data)1392 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port,
1393 u16 pointer, u8 *data)
1394 {
1395 u16 reg;
1396 int err;
1397
1398 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1399 pointer);
1400 if (err)
1401 return err;
1402
1403 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1404 ®);
1405 if (err)
1406 return err;
1407
1408 *data = reg;
1409
1410 return 0;
1411 }
1412
mv88e6393x_port_policy_write(struct mv88e6xxx_chip * chip,int port,u16 pointer,u8 data)1413 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port,
1414 u16 pointer, u8 data)
1415 {
1416 u16 reg;
1417
1418 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data;
1419
1420 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1421 reg);
1422 }
1423
mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip * chip,u16 pointer,u8 data)1424 static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip,
1425 u16 pointer, u8 data)
1426 {
1427 int err, port;
1428
1429 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1430 if (dsa_is_unused_port(chip->ds, port))
1431 continue;
1432
1433 err = mv88e6393x_port_policy_write(chip, port, pointer, data);
1434 if (err)
1435 return err;
1436 }
1437
1438 return 0;
1439 }
1440
mv88e6393x_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)1441 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip,
1442 enum mv88e6xxx_egress_direction direction,
1443 int port)
1444 {
1445 u16 ptr;
1446 int err;
1447
1448 switch (direction) {
1449 case MV88E6XXX_EGRESS_DIR_INGRESS:
1450 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST;
1451 err = mv88e6393x_port_policy_write_all(chip, ptr, port);
1452 if (err)
1453 return err;
1454 break;
1455 case MV88E6XXX_EGRESS_DIR_EGRESS:
1456 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST;
1457 err = mv88e6xxx_g2_write(chip, ptr, port);
1458 if (err)
1459 return err;
1460 break;
1461 }
1462
1463 return 0;
1464 }
1465
mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip * chip,int port,int upstream_port)1466 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1467 int upstream_port)
1468 {
1469 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST;
1470 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI |
1471 upstream_port;
1472
1473 return mv88e6393x_port_policy_write(chip, port, ptr, data);
1474 }
1475
mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip * chip)1476 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
1477 {
1478 u16 ptr;
1479 int err;
1480
1481 /* Consider the frames with reserved multicast destination
1482 * addresses matching 01:80:c2:00:00:00 and
1483 * 01:80:c2:00:00:02 as MGMT.
1484 */
1485 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO;
1486 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1487 if (err)
1488 return err;
1489
1490 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI;
1491 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1492 if (err)
1493 return err;
1494
1495 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO;
1496 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1497 if (err)
1498 return err;
1499
1500 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI;
1501 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1502 if (err)
1503 return err;
1504
1505 return 0;
1506 }
1507
1508 /* Offset 0x10 & 0x11: EPC */
1509
mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip * chip,int port)1510 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port)
1511 {
1512 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY);
1513
1514 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0);
1515 }
1516
1517 /* Port Ether type for 6393X family */
1518
mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip * chip,int port,u16 etype)1519 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1520 u16 etype)
1521 {
1522 u16 val;
1523 int err;
1524
1525 err = mv88e6393x_port_epc_wait_ready(chip, port);
1526 if (err)
1527 return err;
1528
1529 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype);
1530 if (err)
1531 return err;
1532
1533 val = MV88E6393X_PORT_EPC_CMD_BUSY |
1534 MV88E6393X_PORT_EPC_CMD_WRITE |
1535 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE;
1536
1537 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val);
1538 }
1539
1540 /* Offset 0x0f: Port Ether type */
1541
mv88e6351_port_set_ether_type(struct mv88e6xxx_chip * chip,int port,u16 etype)1542 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1543 u16 etype)
1544 {
1545 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1546 }
1547
1548 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1549 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1550 */
1551
mv88e6095_port_tag_remap(struct mv88e6xxx_chip * chip,int port)1552 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1553 {
1554 int err;
1555
1556 /* Use a direct priority mapping for all IEEE tagged frames */
1557 err = mv88e6xxx_port_write(chip, port,
1558 MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
1559 0x3210);
1560 if (err)
1561 return err;
1562
1563 return mv88e6xxx_port_write(chip, port,
1564 MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
1565 0x7654);
1566 }
1567
mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip * chip,int port,u16 table,u8 ptr,u16 data)1568 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
1569 int port, u16 table, u8 ptr, u16 data)
1570 {
1571 u16 reg;
1572
1573 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
1574 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
1575 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
1576
1577 return mv88e6xxx_port_write(chip, port,
1578 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
1579 }
1580
mv88e6390_port_tag_remap(struct mv88e6xxx_chip * chip,int port)1581 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1582 {
1583 int err, i;
1584 u16 table;
1585
1586 for (i = 0; i <= 7; i++) {
1587 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
1588 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1589 (i | i << 4));
1590 if (err)
1591 return err;
1592
1593 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
1594 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1595 if (err)
1596 return err;
1597
1598 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
1599 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1600 if (err)
1601 return err;
1602
1603 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
1604 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1605 if (err)
1606 return err;
1607 }
1608
1609 return 0;
1610 }
1611
1612 /* Offset 0x0E: Policy Control Register */
1613
1614 static int
mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping,enum mv88e6xxx_policy_action action,u16 * mask,u16 * val,int * shift)1615 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping,
1616 enum mv88e6xxx_policy_action action,
1617 u16 *mask, u16 *val, int *shift)
1618 {
1619 switch (mapping) {
1620 case MV88E6XXX_POLICY_MAPPING_DA:
1621 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK);
1622 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK;
1623 break;
1624 case MV88E6XXX_POLICY_MAPPING_SA:
1625 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK);
1626 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK;
1627 break;
1628 case MV88E6XXX_POLICY_MAPPING_VTU:
1629 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK);
1630 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK;
1631 break;
1632 case MV88E6XXX_POLICY_MAPPING_ETYPE:
1633 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK);
1634 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK;
1635 break;
1636 case MV88E6XXX_POLICY_MAPPING_PPPOE:
1637 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK);
1638 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK;
1639 break;
1640 case MV88E6XXX_POLICY_MAPPING_VBAS:
1641 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK);
1642 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK;
1643 break;
1644 case MV88E6XXX_POLICY_MAPPING_OPT82:
1645 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK);
1646 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK;
1647 break;
1648 case MV88E6XXX_POLICY_MAPPING_UDP:
1649 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK);
1650 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK;
1651 break;
1652 default:
1653 return -EOPNOTSUPP;
1654 }
1655
1656 switch (action) {
1657 case MV88E6XXX_POLICY_ACTION_NORMAL:
1658 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL;
1659 break;
1660 case MV88E6XXX_POLICY_ACTION_MIRROR:
1661 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR;
1662 break;
1663 case MV88E6XXX_POLICY_ACTION_TRAP:
1664 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP;
1665 break;
1666 case MV88E6XXX_POLICY_ACTION_DISCARD:
1667 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD;
1668 break;
1669 default:
1670 return -EOPNOTSUPP;
1671 }
1672
1673 return 0;
1674 }
1675
mv88e6352_port_set_policy(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_policy_mapping mapping,enum mv88e6xxx_policy_action action)1676 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1677 enum mv88e6xxx_policy_mapping mapping,
1678 enum mv88e6xxx_policy_action action)
1679 {
1680 u16 reg, mask, val;
1681 int shift;
1682 int err;
1683
1684 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
1685 &val, &shift);
1686 if (err)
1687 return err;
1688
1689 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®);
1690 if (err)
1691 return err;
1692
1693 reg &= ~mask;
1694 reg |= (val << shift) & mask;
1695
1696 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);
1697 }
1698
mv88e6393x_port_set_policy(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_policy_mapping mapping,enum mv88e6xxx_policy_action action)1699 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1700 enum mv88e6xxx_policy_mapping mapping,
1701 enum mv88e6xxx_policy_action action)
1702 {
1703 u16 mask, val;
1704 int shift;
1705 int err;
1706 u16 ptr;
1707 u8 reg;
1708
1709 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
1710 &val, &shift);
1711 if (err)
1712 return err;
1713
1714 /* The 16-bit Port Policy CTL register from older chips is on 6393x
1715 * changed to Port Policy MGMT CTL, which can access more data, but
1716 * indirectly. The original 16-bit value is divided into two 8-bit
1717 * registers.
1718 */
1719 ptr = shift / 8;
1720 shift %= 8;
1721 mask >>= ptr * 8;
1722
1723 err = mv88e6393x_port_policy_read(chip, port, ptr, ®);
1724 if (err)
1725 return err;
1726
1727 reg &= ~mask;
1728 reg |= (val << shift) & mask;
1729
1730 return mv88e6393x_port_policy_write(chip, port, ptr, reg);
1731 }
1732