1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 */
6 #include <linux/etherdevice.h>
7 #include <linux/if_bridge.h>
8 #include <linux/iopoll.h>
9 #include <linux/mdio.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/module.h>
12 #include <linux/netdevice.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_mdio.h>
15 #include <linux/of_net.h>
16 #include <linux/of_platform.h>
17 #include <linux/phylink.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/reset.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/gpio/driver.h>
23 #include <net/dsa.h>
24
25 #include "mt7530.h"
26
pcs_to_mt753x_pcs(struct phylink_pcs * pcs)27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
28 {
29 return container_of(pcs, struct mt753x_pcs, pcs);
30 }
31
32 /* String, offset, and register size in bytes if different from 4 bytes */
33 static const struct mt7530_mib_desc mt7530_mib[] = {
34 MIB_DESC(1, 0x00, "TxDrop"),
35 MIB_DESC(1, 0x04, "TxCrcErr"),
36 MIB_DESC(1, 0x08, "TxUnicast"),
37 MIB_DESC(1, 0x0c, "TxMulticast"),
38 MIB_DESC(1, 0x10, "TxBroadcast"),
39 MIB_DESC(1, 0x14, "TxCollision"),
40 MIB_DESC(1, 0x18, "TxSingleCollision"),
41 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
42 MIB_DESC(1, 0x20, "TxDeferred"),
43 MIB_DESC(1, 0x24, "TxLateCollision"),
44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
45 MIB_DESC(1, 0x2c, "TxPause"),
46 MIB_DESC(1, 0x30, "TxPktSz64"),
47 MIB_DESC(1, 0x34, "TxPktSz65To127"),
48 MIB_DESC(1, 0x38, "TxPktSz128To255"),
49 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
50 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
51 MIB_DESC(1, 0x44, "Tx1024ToMax"),
52 MIB_DESC(2, 0x48, "TxBytes"),
53 MIB_DESC(1, 0x60, "RxDrop"),
54 MIB_DESC(1, 0x64, "RxFiltering"),
55 MIB_DESC(1, 0x68, "RxUnicast"),
56 MIB_DESC(1, 0x6c, "RxMulticast"),
57 MIB_DESC(1, 0x70, "RxBroadcast"),
58 MIB_DESC(1, 0x74, "RxAlignErr"),
59 MIB_DESC(1, 0x78, "RxCrcErr"),
60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
61 MIB_DESC(1, 0x80, "RxFragErr"),
62 MIB_DESC(1, 0x84, "RxOverSzErr"),
63 MIB_DESC(1, 0x88, "RxJabberErr"),
64 MIB_DESC(1, 0x8c, "RxPause"),
65 MIB_DESC(1, 0x90, "RxPktSz64"),
66 MIB_DESC(1, 0x94, "RxPktSz65To127"),
67 MIB_DESC(1, 0x98, "RxPktSz128To255"),
68 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
71 MIB_DESC(2, 0xa8, "RxBytes"),
72 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
73 MIB_DESC(1, 0xb4, "RxIngressDrop"),
74 MIB_DESC(1, 0xb8, "RxArlDrop"),
75 };
76
77 /* Since phy_device has not yet been created and
78 * phy_{read,write}_mmd_indirect is not available, we provide our own
79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
80 * to complete this function.
81 */
82 static int
core_read_mmd_indirect(struct mt7530_priv * priv,int prtad,int devad)83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
84 {
85 struct mii_bus *bus = priv->bus;
86 int value, ret;
87
88 /* Write the desired MMD Devad */
89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
90 if (ret < 0)
91 goto err;
92
93 /* Write the desired MMD register address */
94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
95 if (ret < 0)
96 goto err;
97
98 /* Select the Function : DATA with no post increment */
99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
100 if (ret < 0)
101 goto err;
102
103 /* Read the content of the MMD's selected register */
104 value = bus->read(bus, 0, MII_MMD_DATA);
105
106 return value;
107 err:
108 dev_err(&bus->dev, "failed to read mmd register\n");
109
110 return ret;
111 }
112
113 static int
core_write_mmd_indirect(struct mt7530_priv * priv,int prtad,int devad,u32 data)114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
115 int devad, u32 data)
116 {
117 struct mii_bus *bus = priv->bus;
118 int ret;
119
120 /* Write the desired MMD Devad */
121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
122 if (ret < 0)
123 goto err;
124
125 /* Write the desired MMD register address */
126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
127 if (ret < 0)
128 goto err;
129
130 /* Select the Function : DATA with no post increment */
131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
132 if (ret < 0)
133 goto err;
134
135 /* Write the data into MMD's selected register */
136 ret = bus->write(bus, 0, MII_MMD_DATA, data);
137 err:
138 if (ret < 0)
139 dev_err(&bus->dev,
140 "failed to write mmd register\n");
141 return ret;
142 }
143
144 static void
core_write(struct mt7530_priv * priv,u32 reg,u32 val)145 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
146 {
147 struct mii_bus *bus = priv->bus;
148
149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
150
151 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
152
153 mutex_unlock(&bus->mdio_lock);
154 }
155
156 static void
core_rmw(struct mt7530_priv * priv,u32 reg,u32 mask,u32 set)157 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
158 {
159 struct mii_bus *bus = priv->bus;
160 u32 val;
161
162 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
163
164 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
165 val &= ~mask;
166 val |= set;
167 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
168
169 mutex_unlock(&bus->mdio_lock);
170 }
171
172 static void
core_set(struct mt7530_priv * priv,u32 reg,u32 val)173 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
174 {
175 core_rmw(priv, reg, 0, val);
176 }
177
178 static void
core_clear(struct mt7530_priv * priv,u32 reg,u32 val)179 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
180 {
181 core_rmw(priv, reg, val, 0);
182 }
183
184 static int
mt7530_mii_write(struct mt7530_priv * priv,u32 reg,u32 val)185 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
186 {
187 struct mii_bus *bus = priv->bus;
188 u16 page, r, lo, hi;
189 int ret;
190
191 page = (reg >> 6) & 0x3ff;
192 r = (reg >> 2) & 0xf;
193 lo = val & 0xffff;
194 hi = val >> 16;
195
196 /* MT7530 uses 31 as the pseudo port */
197 ret = bus->write(bus, 0x1f, 0x1f, page);
198 if (ret < 0)
199 goto err;
200
201 ret = bus->write(bus, 0x1f, r, lo);
202 if (ret < 0)
203 goto err;
204
205 ret = bus->write(bus, 0x1f, 0x10, hi);
206 err:
207 if (ret < 0)
208 dev_err(&bus->dev,
209 "failed to write mt7530 register\n");
210 return ret;
211 }
212
213 static u32
mt7530_mii_read(struct mt7530_priv * priv,u32 reg)214 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
215 {
216 struct mii_bus *bus = priv->bus;
217 u16 page, r, lo, hi;
218 int ret;
219
220 page = (reg >> 6) & 0x3ff;
221 r = (reg >> 2) & 0xf;
222
223 /* MT7530 uses 31 as the pseudo port */
224 ret = bus->write(bus, 0x1f, 0x1f, page);
225 if (ret < 0) {
226 dev_err(&bus->dev,
227 "failed to read mt7530 register\n");
228 return ret;
229 }
230
231 lo = bus->read(bus, 0x1f, r);
232 hi = bus->read(bus, 0x1f, 0x10);
233
234 return (hi << 16) | (lo & 0xffff);
235 }
236
237 static void
mt7530_write(struct mt7530_priv * priv,u32 reg,u32 val)238 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
239 {
240 struct mii_bus *bus = priv->bus;
241
242 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
243
244 mt7530_mii_write(priv, reg, val);
245
246 mutex_unlock(&bus->mdio_lock);
247 }
248
249 static u32
_mt7530_unlocked_read(struct mt7530_dummy_poll * p)250 _mt7530_unlocked_read(struct mt7530_dummy_poll *p)
251 {
252 return mt7530_mii_read(p->priv, p->reg);
253 }
254
255 static u32
_mt7530_read(struct mt7530_dummy_poll * p)256 _mt7530_read(struct mt7530_dummy_poll *p)
257 {
258 struct mii_bus *bus = p->priv->bus;
259 u32 val;
260
261 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
262
263 val = mt7530_mii_read(p->priv, p->reg);
264
265 mutex_unlock(&bus->mdio_lock);
266
267 return val;
268 }
269
270 static u32
mt7530_read(struct mt7530_priv * priv,u32 reg)271 mt7530_read(struct mt7530_priv *priv, u32 reg)
272 {
273 struct mt7530_dummy_poll p;
274
275 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
276 return _mt7530_read(&p);
277 }
278
279 static void
mt7530_rmw(struct mt7530_priv * priv,u32 reg,u32 mask,u32 set)280 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
281 u32 mask, u32 set)
282 {
283 struct mii_bus *bus = priv->bus;
284 u32 val;
285
286 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
287
288 val = mt7530_mii_read(priv, reg);
289 val &= ~mask;
290 val |= set;
291 mt7530_mii_write(priv, reg, val);
292
293 mutex_unlock(&bus->mdio_lock);
294 }
295
296 static void
mt7530_set(struct mt7530_priv * priv,u32 reg,u32 val)297 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
298 {
299 mt7530_rmw(priv, reg, 0, val);
300 }
301
302 static void
mt7530_clear(struct mt7530_priv * priv,u32 reg,u32 val)303 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
304 {
305 mt7530_rmw(priv, reg, val, 0);
306 }
307
308 static int
mt7530_fdb_cmd(struct mt7530_priv * priv,enum mt7530_fdb_cmd cmd,u32 * rsp)309 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
310 {
311 u32 val;
312 int ret;
313 struct mt7530_dummy_poll p;
314
315 /* Set the command operating upon the MAC address entries */
316 val = ATC_BUSY | ATC_MAT(0) | cmd;
317 mt7530_write(priv, MT7530_ATC, val);
318
319 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
320 ret = readx_poll_timeout(_mt7530_read, &p, val,
321 !(val & ATC_BUSY), 20, 20000);
322 if (ret < 0) {
323 dev_err(priv->dev, "reset timeout\n");
324 return ret;
325 }
326
327 /* Additional sanity for read command if the specified
328 * entry is invalid
329 */
330 val = mt7530_read(priv, MT7530_ATC);
331 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
332 return -EINVAL;
333
334 if (rsp)
335 *rsp = val;
336
337 return 0;
338 }
339
340 static void
mt7530_fdb_read(struct mt7530_priv * priv,struct mt7530_fdb * fdb)341 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
342 {
343 u32 reg[3];
344 int i;
345
346 /* Read from ARL table into an array */
347 for (i = 0; i < 3; i++) {
348 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
349
350 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
351 __func__, __LINE__, i, reg[i]);
352 }
353
354 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
355 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
356 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
357 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
358 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
359 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
360 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
361 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
362 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
363 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
364 }
365
366 static void
mt7530_fdb_write(struct mt7530_priv * priv,u16 vid,u8 port_mask,const u8 * mac,u8 aging,u8 type)367 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
368 u8 port_mask, const u8 *mac,
369 u8 aging, u8 type)
370 {
371 u32 reg[3] = { 0 };
372 int i;
373
374 reg[1] |= vid & CVID_MASK;
375 reg[1] |= ATA2_IVL;
376 reg[1] |= ATA2_FID(FID_BRIDGED);
377 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
378 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
379 /* STATIC_ENT indicate that entry is static wouldn't
380 * be aged out and STATIC_EMP specified as erasing an
381 * entry
382 */
383 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
384 reg[1] |= mac[5] << MAC_BYTE_5;
385 reg[1] |= mac[4] << MAC_BYTE_4;
386 reg[0] |= mac[3] << MAC_BYTE_3;
387 reg[0] |= mac[2] << MAC_BYTE_2;
388 reg[0] |= mac[1] << MAC_BYTE_1;
389 reg[0] |= mac[0] << MAC_BYTE_0;
390
391 /* Write array into the ARL table */
392 for (i = 0; i < 3; i++)
393 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
394 }
395
396 /* Setup TX circuit including relevant PAD and driving */
397 static int
mt7530_pad_clk_setup(struct dsa_switch * ds,phy_interface_t interface)398 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
399 {
400 struct mt7530_priv *priv = ds->priv;
401 u32 ncpo1, ssc_delta, trgint, i, xtal;
402
403 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
404
405 if (xtal == HWTRAP_XTAL_20MHZ) {
406 dev_err(priv->dev,
407 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
408 __func__);
409 return -EINVAL;
410 }
411
412 switch (interface) {
413 case PHY_INTERFACE_MODE_RGMII:
414 trgint = 0;
415 /* PLL frequency: 125MHz */
416 ncpo1 = 0x0c80;
417 break;
418 case PHY_INTERFACE_MODE_TRGMII:
419 trgint = 1;
420 if (priv->id == ID_MT7621) {
421 /* PLL frequency: 150MHz: 1.2GBit */
422 if (xtal == HWTRAP_XTAL_40MHZ)
423 ncpo1 = 0x0780;
424 if (xtal == HWTRAP_XTAL_25MHZ)
425 ncpo1 = 0x0a00;
426 } else { /* PLL frequency: 250MHz: 2.0Gbit */
427 if (xtal == HWTRAP_XTAL_40MHZ)
428 ncpo1 = 0x0c80;
429 if (xtal == HWTRAP_XTAL_25MHZ)
430 ncpo1 = 0x1400;
431 }
432 break;
433 default:
434 dev_err(priv->dev, "xMII interface %d not supported\n",
435 interface);
436 return -EINVAL;
437 }
438
439 if (xtal == HWTRAP_XTAL_25MHZ)
440 ssc_delta = 0x57;
441 else
442 ssc_delta = 0x87;
443
444 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
445 P6_INTF_MODE(trgint));
446
447 /* Lower Tx Driving for TRGMII path */
448 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
449 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
450 TD_DM_DRVP(8) | TD_DM_DRVN(8));
451
452 /* Disable MT7530 core and TRGMII Tx clocks */
453 core_clear(priv, CORE_TRGMII_GSW_CLK_CG,
454 REG_GSWCK_EN | REG_TRGMIICK_EN);
455
456 /* Setup core clock for MT7530 */
457 /* Disable PLL */
458 core_write(priv, CORE_GSWPLL_GRP1, 0);
459
460 /* Set core clock into 500Mhz */
461 core_write(priv, CORE_GSWPLL_GRP2,
462 RG_GSWPLL_POSDIV_500M(1) |
463 RG_GSWPLL_FBKDIV_500M(25));
464
465 /* Enable PLL */
466 core_write(priv, CORE_GSWPLL_GRP1,
467 RG_GSWPLL_EN_PRE |
468 RG_GSWPLL_POSDIV_200M(2) |
469 RG_GSWPLL_FBKDIV_200M(32));
470
471 /* Setup the MT7530 TRGMII Tx Clock */
472 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
473 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
474 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
475 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
476 core_write(priv, CORE_PLL_GROUP4,
477 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
478 RG_SYSPLL_BIAS_LPF_EN);
479 core_write(priv, CORE_PLL_GROUP2,
480 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
481 RG_SYSPLL_POSDIV(1));
482 core_write(priv, CORE_PLL_GROUP7,
483 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
484 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
485
486 /* Enable MT7530 core and TRGMII Tx clocks */
487 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
488 REG_GSWCK_EN | REG_TRGMIICK_EN);
489
490 if (!trgint)
491 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
492 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
493 RD_TAP_MASK, RD_TAP(16));
494 return 0;
495 }
496
mt7531_dual_sgmii_supported(struct mt7530_priv * priv)497 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
498 {
499 u32 val;
500
501 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
502
503 return (val & PAD_DUAL_SGMII_EN) != 0;
504 }
505
506 static int
mt7531_pad_setup(struct dsa_switch * ds,phy_interface_t interface)507 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
508 {
509 return 0;
510 }
511
512 static void
mt7531_pll_setup(struct mt7530_priv * priv)513 mt7531_pll_setup(struct mt7530_priv *priv)
514 {
515 u32 top_sig;
516 u32 hwstrap;
517 u32 xtal;
518 u32 val;
519
520 if (mt7531_dual_sgmii_supported(priv))
521 return;
522
523 val = mt7530_read(priv, MT7531_CREV);
524 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
525 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
526 if ((val & CHIP_REV_M) > 0)
527 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
528 HWTRAP_XTAL_FSEL_25MHZ;
529 else
530 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
531
532 /* Step 1 : Disable MT7531 COREPLL */
533 val = mt7530_read(priv, MT7531_PLLGP_EN);
534 val &= ~EN_COREPLL;
535 mt7530_write(priv, MT7531_PLLGP_EN, val);
536
537 /* Step 2: switch to XTAL output */
538 val = mt7530_read(priv, MT7531_PLLGP_EN);
539 val |= SW_CLKSW;
540 mt7530_write(priv, MT7531_PLLGP_EN, val);
541
542 val = mt7530_read(priv, MT7531_PLLGP_CR0);
543 val &= ~RG_COREPLL_EN;
544 mt7530_write(priv, MT7531_PLLGP_CR0, val);
545
546 /* Step 3: disable PLLGP and enable program PLLGP */
547 val = mt7530_read(priv, MT7531_PLLGP_EN);
548 val |= SW_PLLGP;
549 mt7530_write(priv, MT7531_PLLGP_EN, val);
550
551 /* Step 4: program COREPLL output frequency to 500MHz */
552 val = mt7530_read(priv, MT7531_PLLGP_CR0);
553 val &= ~RG_COREPLL_POSDIV_M;
554 val |= 2 << RG_COREPLL_POSDIV_S;
555 mt7530_write(priv, MT7531_PLLGP_CR0, val);
556 usleep_range(25, 35);
557
558 switch (xtal) {
559 case HWTRAP_XTAL_FSEL_25MHZ:
560 val = mt7530_read(priv, MT7531_PLLGP_CR0);
561 val &= ~RG_COREPLL_SDM_PCW_M;
562 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
563 mt7530_write(priv, MT7531_PLLGP_CR0, val);
564 break;
565 case HWTRAP_XTAL_FSEL_40MHZ:
566 val = mt7530_read(priv, MT7531_PLLGP_CR0);
567 val &= ~RG_COREPLL_SDM_PCW_M;
568 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
569 mt7530_write(priv, MT7531_PLLGP_CR0, val);
570 break;
571 }
572
573 /* Set feedback divide ratio update signal to high */
574 val = mt7530_read(priv, MT7531_PLLGP_CR0);
575 val |= RG_COREPLL_SDM_PCW_CHG;
576 mt7530_write(priv, MT7531_PLLGP_CR0, val);
577 /* Wait for at least 16 XTAL clocks */
578 usleep_range(10, 20);
579
580 /* Step 5: set feedback divide ratio update signal to low */
581 val = mt7530_read(priv, MT7531_PLLGP_CR0);
582 val &= ~RG_COREPLL_SDM_PCW_CHG;
583 mt7530_write(priv, MT7531_PLLGP_CR0, val);
584
585 /* Enable 325M clock for SGMII */
586 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
587
588 /* Enable 250SSC clock for RGMII */
589 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
590
591 /* Step 6: Enable MT7531 PLL */
592 val = mt7530_read(priv, MT7531_PLLGP_CR0);
593 val |= RG_COREPLL_EN;
594 mt7530_write(priv, MT7531_PLLGP_CR0, val);
595
596 val = mt7530_read(priv, MT7531_PLLGP_EN);
597 val |= EN_COREPLL;
598 mt7530_write(priv, MT7531_PLLGP_EN, val);
599 usleep_range(25, 35);
600 }
601
602 static void
mt7530_mib_reset(struct dsa_switch * ds)603 mt7530_mib_reset(struct dsa_switch *ds)
604 {
605 struct mt7530_priv *priv = ds->priv;
606
607 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
608 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
609 }
610
mt7530_phy_read(struct mt7530_priv * priv,int port,int regnum)611 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum)
612 {
613 return mdiobus_read_nested(priv->bus, port, regnum);
614 }
615
mt7530_phy_write(struct mt7530_priv * priv,int port,int regnum,u16 val)616 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum,
617 u16 val)
618 {
619 return mdiobus_write_nested(priv->bus, port, regnum, val);
620 }
621
622 static int
mt7531_ind_c45_phy_read(struct mt7530_priv * priv,int port,int devad,int regnum)623 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
624 int regnum)
625 {
626 struct mii_bus *bus = priv->bus;
627 struct mt7530_dummy_poll p;
628 u32 reg, val;
629 int ret;
630
631 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
632
633 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
634
635 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
636 !(val & MT7531_PHY_ACS_ST), 20, 100000);
637 if (ret < 0) {
638 dev_err(priv->dev, "poll timeout\n");
639 goto out;
640 }
641
642 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
643 MT7531_MDIO_DEV_ADDR(devad) | regnum;
644 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
645
646 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
647 !(val & MT7531_PHY_ACS_ST), 20, 100000);
648 if (ret < 0) {
649 dev_err(priv->dev, "poll timeout\n");
650 goto out;
651 }
652
653 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
654 MT7531_MDIO_DEV_ADDR(devad);
655 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
656
657 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
658 !(val & MT7531_PHY_ACS_ST), 20, 100000);
659 if (ret < 0) {
660 dev_err(priv->dev, "poll timeout\n");
661 goto out;
662 }
663
664 ret = val & MT7531_MDIO_RW_DATA_MASK;
665 out:
666 mutex_unlock(&bus->mdio_lock);
667
668 return ret;
669 }
670
671 static int
mt7531_ind_c45_phy_write(struct mt7530_priv * priv,int port,int devad,int regnum,u32 data)672 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
673 int regnum, u32 data)
674 {
675 struct mii_bus *bus = priv->bus;
676 struct mt7530_dummy_poll p;
677 u32 val, reg;
678 int ret;
679
680 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
681
682 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
683
684 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
685 !(val & MT7531_PHY_ACS_ST), 20, 100000);
686 if (ret < 0) {
687 dev_err(priv->dev, "poll timeout\n");
688 goto out;
689 }
690
691 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
692 MT7531_MDIO_DEV_ADDR(devad) | regnum;
693 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
694
695 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
696 !(val & MT7531_PHY_ACS_ST), 20, 100000);
697 if (ret < 0) {
698 dev_err(priv->dev, "poll timeout\n");
699 goto out;
700 }
701
702 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
703 MT7531_MDIO_DEV_ADDR(devad) | data;
704 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
705
706 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
707 !(val & MT7531_PHY_ACS_ST), 20, 100000);
708 if (ret < 0) {
709 dev_err(priv->dev, "poll timeout\n");
710 goto out;
711 }
712
713 out:
714 mutex_unlock(&bus->mdio_lock);
715
716 return ret;
717 }
718
719 static int
mt7531_ind_c22_phy_read(struct mt7530_priv * priv,int port,int regnum)720 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
721 {
722 struct mii_bus *bus = priv->bus;
723 struct mt7530_dummy_poll p;
724 int ret;
725 u32 val;
726
727 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
728
729 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
730
731 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
732 !(val & MT7531_PHY_ACS_ST), 20, 100000);
733 if (ret < 0) {
734 dev_err(priv->dev, "poll timeout\n");
735 goto out;
736 }
737
738 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
739 MT7531_MDIO_REG_ADDR(regnum);
740
741 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
742
743 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
744 !(val & MT7531_PHY_ACS_ST), 20, 100000);
745 if (ret < 0) {
746 dev_err(priv->dev, "poll timeout\n");
747 goto out;
748 }
749
750 ret = val & MT7531_MDIO_RW_DATA_MASK;
751 out:
752 mutex_unlock(&bus->mdio_lock);
753
754 return ret;
755 }
756
757 static int
mt7531_ind_c22_phy_write(struct mt7530_priv * priv,int port,int regnum,u16 data)758 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
759 u16 data)
760 {
761 struct mii_bus *bus = priv->bus;
762 struct mt7530_dummy_poll p;
763 int ret;
764 u32 reg;
765
766 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
767
768 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
769
770 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
771 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
772 if (ret < 0) {
773 dev_err(priv->dev, "poll timeout\n");
774 goto out;
775 }
776
777 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
778 MT7531_MDIO_REG_ADDR(regnum) | data;
779
780 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
781
782 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
783 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
784 if (ret < 0) {
785 dev_err(priv->dev, "poll timeout\n");
786 goto out;
787 }
788
789 out:
790 mutex_unlock(&bus->mdio_lock);
791
792 return ret;
793 }
794
795 static int
mt7531_ind_phy_read(struct mt7530_priv * priv,int port,int regnum)796 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum)
797 {
798 int devad;
799 int ret;
800
801 if (regnum & MII_ADDR_C45) {
802 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
803 ret = mt7531_ind_c45_phy_read(priv, port, devad,
804 regnum & MII_REGADDR_C45_MASK);
805 } else {
806 ret = mt7531_ind_c22_phy_read(priv, port, regnum);
807 }
808
809 return ret;
810 }
811
812 static int
mt7531_ind_phy_write(struct mt7530_priv * priv,int port,int regnum,u16 data)813 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum,
814 u16 data)
815 {
816 int devad;
817 int ret;
818
819 if (regnum & MII_ADDR_C45) {
820 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
821 ret = mt7531_ind_c45_phy_write(priv, port, devad,
822 regnum & MII_REGADDR_C45_MASK,
823 data);
824 } else {
825 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
826 }
827
828 return ret;
829 }
830
831 static int
mt753x_phy_read(struct mii_bus * bus,int port,int regnum)832 mt753x_phy_read(struct mii_bus *bus, int port, int regnum)
833 {
834 struct mt7530_priv *priv = bus->priv;
835
836 return priv->info->phy_read(priv, port, regnum);
837 }
838
839 static int
mt753x_phy_write(struct mii_bus * bus,int port,int regnum,u16 val)840 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val)
841 {
842 struct mt7530_priv *priv = bus->priv;
843
844 return priv->info->phy_write(priv, port, regnum, val);
845 }
846
847 static void
mt7530_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)848 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
849 uint8_t *data)
850 {
851 int i;
852
853 if (stringset != ETH_SS_STATS)
854 return;
855
856 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
857 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
858 ETH_GSTRING_LEN);
859 }
860
861 static void
mt7530_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)862 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
863 uint64_t *data)
864 {
865 struct mt7530_priv *priv = ds->priv;
866 const struct mt7530_mib_desc *mib;
867 u32 reg, i;
868 u64 hi;
869
870 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
871 mib = &mt7530_mib[i];
872 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
873
874 data[i] = mt7530_read(priv, reg);
875 if (mib->size == 2) {
876 hi = mt7530_read(priv, reg + 4);
877 data[i] |= hi << 32;
878 }
879 }
880 }
881
882 static int
mt7530_get_sset_count(struct dsa_switch * ds,int port,int sset)883 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
884 {
885 if (sset != ETH_SS_STATS)
886 return 0;
887
888 return ARRAY_SIZE(mt7530_mib);
889 }
890
891 static int
mt7530_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)892 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
893 {
894 struct mt7530_priv *priv = ds->priv;
895 unsigned int secs = msecs / 1000;
896 unsigned int tmp_age_count;
897 unsigned int error = -1;
898 unsigned int age_count;
899 unsigned int age_unit;
900
901 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
902 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
903 return -ERANGE;
904
905 /* iterate through all possible age_count to find the closest pair */
906 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
907 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
908
909 if (tmp_age_unit <= AGE_UNIT_MAX) {
910 unsigned int tmp_error = secs -
911 (tmp_age_count + 1) * (tmp_age_unit + 1);
912
913 /* found a closer pair */
914 if (error > tmp_error) {
915 error = tmp_error;
916 age_count = tmp_age_count;
917 age_unit = tmp_age_unit;
918 }
919
920 /* found the exact match, so break the loop */
921 if (!error)
922 break;
923 }
924 }
925
926 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
927
928 return 0;
929 }
930
mt7530_setup_port5(struct dsa_switch * ds,phy_interface_t interface)931 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
932 {
933 struct mt7530_priv *priv = ds->priv;
934 u8 tx_delay = 0;
935 int val;
936
937 mutex_lock(&priv->reg_mutex);
938
939 val = mt7530_read(priv, MT7530_MHWTRAP);
940
941 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
942 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
943
944 switch (priv->p5_intf_sel) {
945 case P5_INTF_SEL_PHY_P0:
946 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
947 val |= MHWTRAP_PHY0_SEL;
948 fallthrough;
949 case P5_INTF_SEL_PHY_P4:
950 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
951 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
952
953 /* Setup the MAC by default for the cpu port */
954 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
955 break;
956 case P5_INTF_SEL_GMAC5:
957 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
958 val &= ~MHWTRAP_P5_DIS;
959 break;
960 case P5_DISABLED:
961 interface = PHY_INTERFACE_MODE_NA;
962 break;
963 default:
964 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
965 priv->p5_intf_sel);
966 goto unlock_exit;
967 }
968
969 /* Setup RGMII settings */
970 if (phy_interface_mode_is_rgmii(interface)) {
971 val |= MHWTRAP_P5_RGMII_MODE;
972
973 /* P5 RGMII RX Clock Control: delay setting for 1000M */
974 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
975
976 /* Don't set delay in DSA mode */
977 if (!dsa_is_dsa_port(priv->ds, 5) &&
978 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
979 interface == PHY_INTERFACE_MODE_RGMII_ID))
980 tx_delay = 4; /* n * 0.5 ns */
981
982 /* P5 RGMII TX Clock Control: delay x */
983 mt7530_write(priv, MT7530_P5RGMIITXCR,
984 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
985
986 /* reduce P5 RGMII Tx driving, 8mA */
987 mt7530_write(priv, MT7530_IO_DRV_CR,
988 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
989 }
990
991 mt7530_write(priv, MT7530_MHWTRAP, val);
992
993 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
994 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
995
996 priv->p5_interface = interface;
997
998 unlock_exit:
999 mutex_unlock(&priv->reg_mutex);
1000 }
1001
1002 static int
mt753x_cpu_port_enable(struct dsa_switch * ds,int port)1003 mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
1004 {
1005 struct mt7530_priv *priv = ds->priv;
1006 int ret;
1007
1008 /* Setup max capability of CPU port at first */
1009 if (priv->info->cpu_port_config) {
1010 ret = priv->info->cpu_port_config(ds, port);
1011 if (ret)
1012 return ret;
1013 }
1014
1015 /* Enable Mediatek header mode on the cpu port */
1016 mt7530_write(priv, MT7530_PVC_P(port),
1017 PORT_SPEC_TAG);
1018
1019 /* Disable flooding by default */
1020 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK,
1021 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port)));
1022
1023 /* Set CPU port number */
1024 if (priv->id == ID_MT7621)
1025 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1026
1027 /* CPU port gets connected to all user ports of
1028 * the switch.
1029 */
1030 mt7530_write(priv, MT7530_PCR_P(port),
1031 PCR_MATRIX(dsa_user_ports(priv->ds)));
1032
1033 /* Set to fallback mode for independent VLAN learning */
1034 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1035 MT7530_PORT_FALLBACK_MODE);
1036
1037 return 0;
1038 }
1039
1040 static int
mt7530_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)1041 mt7530_port_enable(struct dsa_switch *ds, int port,
1042 struct phy_device *phy)
1043 {
1044 struct dsa_port *dp = dsa_to_port(ds, port);
1045 struct mt7530_priv *priv = ds->priv;
1046
1047 mutex_lock(&priv->reg_mutex);
1048
1049 /* Allow the user port gets connected to the cpu port and also
1050 * restore the port matrix if the port is the member of a certain
1051 * bridge.
1052 */
1053 if (dsa_port_is_user(dp)) {
1054 struct dsa_port *cpu_dp = dp->cpu_dp;
1055
1056 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index));
1057 }
1058 priv->ports[port].enable = true;
1059 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1060 priv->ports[port].pm);
1061 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1062
1063 mutex_unlock(&priv->reg_mutex);
1064
1065 return 0;
1066 }
1067
1068 static void
mt7530_port_disable(struct dsa_switch * ds,int port)1069 mt7530_port_disable(struct dsa_switch *ds, int port)
1070 {
1071 struct mt7530_priv *priv = ds->priv;
1072
1073 mutex_lock(&priv->reg_mutex);
1074
1075 /* Clear up all port matrix which could be restored in the next
1076 * enablement for the port.
1077 */
1078 priv->ports[port].enable = false;
1079 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1080 PCR_MATRIX_CLR);
1081 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1082
1083 mutex_unlock(&priv->reg_mutex);
1084 }
1085
1086 static int
mt7530_port_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1087 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1088 {
1089 struct mt7530_priv *priv = ds->priv;
1090 struct mii_bus *bus = priv->bus;
1091 int length;
1092 u32 val;
1093
1094 /* When a new MTU is set, DSA always set the CPU port's MTU to the
1095 * largest MTU of the slave ports. Because the switch only has a global
1096 * RX length register, only allowing CPU port here is enough.
1097 */
1098 if (!dsa_is_cpu_port(ds, port))
1099 return 0;
1100
1101 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1102
1103 val = mt7530_mii_read(priv, MT7530_GMACCR);
1104 val &= ~MAX_RX_PKT_LEN_MASK;
1105
1106 /* RX length also includes Ethernet header, MTK tag, and FCS length */
1107 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1108 if (length <= 1522) {
1109 val |= MAX_RX_PKT_LEN_1522;
1110 } else if (length <= 1536) {
1111 val |= MAX_RX_PKT_LEN_1536;
1112 } else if (length <= 1552) {
1113 val |= MAX_RX_PKT_LEN_1552;
1114 } else {
1115 val &= ~MAX_RX_JUMBO_MASK;
1116 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1117 val |= MAX_RX_PKT_LEN_JUMBO;
1118 }
1119
1120 mt7530_mii_write(priv, MT7530_GMACCR, val);
1121
1122 mutex_unlock(&bus->mdio_lock);
1123
1124 return 0;
1125 }
1126
1127 static int
mt7530_port_max_mtu(struct dsa_switch * ds,int port)1128 mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1129 {
1130 return MT7530_MAX_MTU;
1131 }
1132
1133 static void
mt7530_stp_state_set(struct dsa_switch * ds,int port,u8 state)1134 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1135 {
1136 struct mt7530_priv *priv = ds->priv;
1137 u32 stp_state;
1138
1139 switch (state) {
1140 case BR_STATE_DISABLED:
1141 stp_state = MT7530_STP_DISABLED;
1142 break;
1143 case BR_STATE_BLOCKING:
1144 stp_state = MT7530_STP_BLOCKING;
1145 break;
1146 case BR_STATE_LISTENING:
1147 stp_state = MT7530_STP_LISTENING;
1148 break;
1149 case BR_STATE_LEARNING:
1150 stp_state = MT7530_STP_LEARNING;
1151 break;
1152 case BR_STATE_FORWARDING:
1153 default:
1154 stp_state = MT7530_STP_FORWARDING;
1155 break;
1156 }
1157
1158 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED),
1159 FID_PST(FID_BRIDGED, stp_state));
1160 }
1161
1162 static int
mt7530_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1163 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1164 struct switchdev_brport_flags flags,
1165 struct netlink_ext_ack *extack)
1166 {
1167 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1168 BR_BCAST_FLOOD))
1169 return -EINVAL;
1170
1171 return 0;
1172 }
1173
1174 static int
mt7530_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1175 mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
1176 struct switchdev_brport_flags flags,
1177 struct netlink_ext_ack *extack)
1178 {
1179 struct mt7530_priv *priv = ds->priv;
1180
1181 if (flags.mask & BR_LEARNING)
1182 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
1183 flags.val & BR_LEARNING ? 0 : SA_DIS);
1184
1185 if (flags.mask & BR_FLOOD)
1186 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
1187 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1188
1189 if (flags.mask & BR_MCAST_FLOOD)
1190 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1191 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1192
1193 if (flags.mask & BR_BCAST_FLOOD)
1194 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
1195 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1196
1197 return 0;
1198 }
1199
1200 static int
mt7530_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1201 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1202 struct dsa_bridge bridge, bool *tx_fwd_offload,
1203 struct netlink_ext_ack *extack)
1204 {
1205 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1206 struct dsa_port *cpu_dp = dp->cpu_dp;
1207 u32 port_bitmap = BIT(cpu_dp->index);
1208 struct mt7530_priv *priv = ds->priv;
1209
1210 mutex_lock(&priv->reg_mutex);
1211
1212 dsa_switch_for_each_user_port(other_dp, ds) {
1213 int other_port = other_dp->index;
1214
1215 if (dp == other_dp)
1216 continue;
1217
1218 /* Add this port to the port matrix of the other ports in the
1219 * same bridge. If the port is disabled, port matrix is kept
1220 * and not being setup until the port becomes enabled.
1221 */
1222 if (!dsa_port_offloads_bridge(other_dp, &bridge))
1223 continue;
1224
1225 if (priv->ports[other_port].enable)
1226 mt7530_set(priv, MT7530_PCR_P(other_port),
1227 PCR_MATRIX(BIT(port)));
1228 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port));
1229
1230 port_bitmap |= BIT(other_port);
1231 }
1232
1233 /* Add the all other ports to this port matrix. */
1234 if (priv->ports[port].enable)
1235 mt7530_rmw(priv, MT7530_PCR_P(port),
1236 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1237 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1238
1239 /* Set to fallback mode for independent VLAN learning */
1240 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1241 MT7530_PORT_FALLBACK_MODE);
1242
1243 mutex_unlock(&priv->reg_mutex);
1244
1245 return 0;
1246 }
1247
1248 static void
mt7530_port_set_vlan_unaware(struct dsa_switch * ds,int port)1249 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1250 {
1251 struct mt7530_priv *priv = ds->priv;
1252 bool all_user_ports_removed = true;
1253 int i;
1254
1255 /* This is called after .port_bridge_leave when leaving a VLAN-aware
1256 * bridge. Don't set standalone ports to fallback mode.
1257 */
1258 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
1259 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1260 MT7530_PORT_FALLBACK_MODE);
1261
1262 mt7530_rmw(priv, MT7530_PVC_P(port),
1263 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
1264 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
1265 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
1266 MT7530_VLAN_ACC_ALL);
1267
1268 /* Set PVID to 0 */
1269 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1270 G0_PORT_VID_DEF);
1271
1272 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1273 if (dsa_is_user_port(ds, i) &&
1274 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
1275 all_user_ports_removed = false;
1276 break;
1277 }
1278 }
1279
1280 /* CPU port also does the same thing until all user ports belonging to
1281 * the CPU port get out of VLAN filtering mode.
1282 */
1283 if (all_user_ports_removed) {
1284 struct dsa_port *dp = dsa_to_port(ds, port);
1285 struct dsa_port *cpu_dp = dp->cpu_dp;
1286
1287 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index),
1288 PCR_MATRIX(dsa_user_ports(priv->ds)));
1289 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG
1290 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1291 }
1292 }
1293
1294 static void
mt7530_port_set_vlan_aware(struct dsa_switch * ds,int port)1295 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1296 {
1297 struct mt7530_priv *priv = ds->priv;
1298
1299 /* Trapped into security mode allows packet forwarding through VLAN
1300 * table lookup.
1301 */
1302 if (dsa_is_user_port(ds, port)) {
1303 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1304 MT7530_PORT_SECURITY_MODE);
1305 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1306 G0_PORT_VID(priv->ports[port].pvid));
1307
1308 /* Only accept tagged frames if PVID is not set */
1309 if (!priv->ports[port].pvid)
1310 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1311 MT7530_VLAN_ACC_TAGGED);
1312 }
1313
1314 /* Set the port as a user port which is to be able to recognize VID
1315 * from incoming packets before fetching entry within the VLAN table.
1316 */
1317 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1318 VLAN_ATTR(MT7530_VLAN_USER) |
1319 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
1320 }
1321
1322 static void
mt7530_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1323 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1324 struct dsa_bridge bridge)
1325 {
1326 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1327 struct dsa_port *cpu_dp = dp->cpu_dp;
1328 struct mt7530_priv *priv = ds->priv;
1329
1330 mutex_lock(&priv->reg_mutex);
1331
1332 dsa_switch_for_each_user_port(other_dp, ds) {
1333 int other_port = other_dp->index;
1334
1335 if (dp == other_dp)
1336 continue;
1337
1338 /* Remove this port from the port matrix of the other ports
1339 * in the same bridge. If the port is disabled, port matrix
1340 * is kept and not being setup until the port becomes enabled.
1341 */
1342 if (!dsa_port_offloads_bridge(other_dp, &bridge))
1343 continue;
1344
1345 if (priv->ports[other_port].enable)
1346 mt7530_clear(priv, MT7530_PCR_P(other_port),
1347 PCR_MATRIX(BIT(port)));
1348 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port));
1349 }
1350
1351 /* Set the cpu port to be the only one in the port matrix of
1352 * this port.
1353 */
1354 if (priv->ports[port].enable)
1355 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1356 PCR_MATRIX(BIT(cpu_dp->index)));
1357 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index));
1358
1359 /* When a port is removed from the bridge, the port would be set up
1360 * back to the default as is at initial boot which is a VLAN-unaware
1361 * port.
1362 */
1363 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1364 MT7530_PORT_MATRIX_MODE);
1365
1366 mutex_unlock(&priv->reg_mutex);
1367 }
1368
1369 static int
mt7530_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1370 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
1371 const unsigned char *addr, u16 vid,
1372 struct dsa_db db)
1373 {
1374 struct mt7530_priv *priv = ds->priv;
1375 int ret;
1376 u8 port_mask = BIT(port);
1377
1378 mutex_lock(&priv->reg_mutex);
1379 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1380 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1381 mutex_unlock(&priv->reg_mutex);
1382
1383 return ret;
1384 }
1385
1386 static int
mt7530_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1387 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
1388 const unsigned char *addr, u16 vid,
1389 struct dsa_db db)
1390 {
1391 struct mt7530_priv *priv = ds->priv;
1392 int ret;
1393 u8 port_mask = BIT(port);
1394
1395 mutex_lock(&priv->reg_mutex);
1396 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
1397 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1398 mutex_unlock(&priv->reg_mutex);
1399
1400 return ret;
1401 }
1402
1403 static int
mt7530_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1404 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
1405 dsa_fdb_dump_cb_t *cb, void *data)
1406 {
1407 struct mt7530_priv *priv = ds->priv;
1408 struct mt7530_fdb _fdb = { 0 };
1409 int cnt = MT7530_NUM_FDB_RECORDS;
1410 int ret = 0;
1411 u32 rsp = 0;
1412
1413 mutex_lock(&priv->reg_mutex);
1414
1415 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1416 if (ret < 0)
1417 goto err;
1418
1419 do {
1420 if (rsp & ATC_SRCH_HIT) {
1421 mt7530_fdb_read(priv, &_fdb);
1422 if (_fdb.port_mask & BIT(port)) {
1423 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1424 data);
1425 if (ret < 0)
1426 break;
1427 }
1428 }
1429 } while (--cnt &&
1430 !(rsp & ATC_SRCH_END) &&
1431 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1432 err:
1433 mutex_unlock(&priv->reg_mutex);
1434
1435 return 0;
1436 }
1437
1438 static int
mt7530_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1439 mt7530_port_mdb_add(struct dsa_switch *ds, int port,
1440 const struct switchdev_obj_port_mdb *mdb,
1441 struct dsa_db db)
1442 {
1443 struct mt7530_priv *priv = ds->priv;
1444 const u8 *addr = mdb->addr;
1445 u16 vid = mdb->vid;
1446 u8 port_mask = 0;
1447 int ret;
1448
1449 mutex_lock(&priv->reg_mutex);
1450
1451 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1452 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1453 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1454 & PORT_MAP_MASK;
1455
1456 port_mask |= BIT(port);
1457 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1458 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1459
1460 mutex_unlock(&priv->reg_mutex);
1461
1462 return ret;
1463 }
1464
1465 static int
mt7530_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1466 mt7530_port_mdb_del(struct dsa_switch *ds, int port,
1467 const struct switchdev_obj_port_mdb *mdb,
1468 struct dsa_db db)
1469 {
1470 struct mt7530_priv *priv = ds->priv;
1471 const u8 *addr = mdb->addr;
1472 u16 vid = mdb->vid;
1473 u8 port_mask = 0;
1474 int ret;
1475
1476 mutex_lock(&priv->reg_mutex);
1477
1478 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1479 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1480 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1481 & PORT_MAP_MASK;
1482
1483 port_mask &= ~BIT(port);
1484 mt7530_fdb_write(priv, vid, port_mask, addr, -1,
1485 port_mask ? STATIC_ENT : STATIC_EMP);
1486 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1487
1488 mutex_unlock(&priv->reg_mutex);
1489
1490 return ret;
1491 }
1492
1493 static int
mt7530_vlan_cmd(struct mt7530_priv * priv,enum mt7530_vlan_cmd cmd,u16 vid)1494 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1495 {
1496 struct mt7530_dummy_poll p;
1497 u32 val;
1498 int ret;
1499
1500 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1501 mt7530_write(priv, MT7530_VTCR, val);
1502
1503 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1504 ret = readx_poll_timeout(_mt7530_read, &p, val,
1505 !(val & VTCR_BUSY), 20, 20000);
1506 if (ret < 0) {
1507 dev_err(priv->dev, "poll timeout\n");
1508 return ret;
1509 }
1510
1511 val = mt7530_read(priv, MT7530_VTCR);
1512 if (val & VTCR_INVALID) {
1513 dev_err(priv->dev, "read VTCR invalid\n");
1514 return -EINVAL;
1515 }
1516
1517 return 0;
1518 }
1519
1520 static int
mt7530_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1521 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1522 struct netlink_ext_ack *extack)
1523 {
1524 struct dsa_port *dp = dsa_to_port(ds, port);
1525 struct dsa_port *cpu_dp = dp->cpu_dp;
1526
1527 if (vlan_filtering) {
1528 /* The port is being kept as VLAN-unaware port when bridge is
1529 * set up with vlan_filtering not being set, Otherwise, the
1530 * port and the corresponding CPU port is required the setup
1531 * for becoming a VLAN-aware port.
1532 */
1533 mt7530_port_set_vlan_aware(ds, port);
1534 mt7530_port_set_vlan_aware(ds, cpu_dp->index);
1535 } else {
1536 mt7530_port_set_vlan_unaware(ds, port);
1537 }
1538
1539 return 0;
1540 }
1541
1542 static void
mt7530_hw_vlan_add(struct mt7530_priv * priv,struct mt7530_hw_vlan_entry * entry)1543 mt7530_hw_vlan_add(struct mt7530_priv *priv,
1544 struct mt7530_hw_vlan_entry *entry)
1545 {
1546 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
1547 u8 new_members;
1548 u32 val;
1549
1550 new_members = entry->old_members | BIT(entry->port);
1551
1552 /* Validate the entry with independent learning, create egress tag per
1553 * VLAN and joining the port as one of the port members.
1554 */
1555 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
1556 VLAN_VALID;
1557 mt7530_write(priv, MT7530_VAWD1, val);
1558
1559 /* Decide whether adding tag or not for those outgoing packets from the
1560 * port inside the VLAN.
1561 * CPU port is always taken as a tagged port for serving more than one
1562 * VLANs across and also being applied with egress type stack mode for
1563 * that VLAN tags would be appended after hardware special tag used as
1564 * DSA tag.
1565 */
1566 if (dsa_port_is_cpu(dp))
1567 val = MT7530_VLAN_EGRESS_STACK;
1568 else if (entry->untagged)
1569 val = MT7530_VLAN_EGRESS_UNTAG;
1570 else
1571 val = MT7530_VLAN_EGRESS_TAG;
1572 mt7530_rmw(priv, MT7530_VAWD2,
1573 ETAG_CTRL_P_MASK(entry->port),
1574 ETAG_CTRL_P(entry->port, val));
1575 }
1576
1577 static void
mt7530_hw_vlan_del(struct mt7530_priv * priv,struct mt7530_hw_vlan_entry * entry)1578 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1579 struct mt7530_hw_vlan_entry *entry)
1580 {
1581 u8 new_members;
1582 u32 val;
1583
1584 new_members = entry->old_members & ~BIT(entry->port);
1585
1586 val = mt7530_read(priv, MT7530_VAWD1);
1587 if (!(val & VLAN_VALID)) {
1588 dev_err(priv->dev,
1589 "Cannot be deleted due to invalid entry\n");
1590 return;
1591 }
1592
1593 if (new_members) {
1594 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1595 VLAN_VALID;
1596 mt7530_write(priv, MT7530_VAWD1, val);
1597 } else {
1598 mt7530_write(priv, MT7530_VAWD1, 0);
1599 mt7530_write(priv, MT7530_VAWD2, 0);
1600 }
1601 }
1602
1603 static void
mt7530_hw_vlan_update(struct mt7530_priv * priv,u16 vid,struct mt7530_hw_vlan_entry * entry,mt7530_vlan_op vlan_op)1604 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1605 struct mt7530_hw_vlan_entry *entry,
1606 mt7530_vlan_op vlan_op)
1607 {
1608 u32 val;
1609
1610 /* Fetch entry */
1611 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1612
1613 val = mt7530_read(priv, MT7530_VAWD1);
1614
1615 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1616
1617 /* Manipulate entry */
1618 vlan_op(priv, entry);
1619
1620 /* Flush result to hardware */
1621 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1622 }
1623
1624 static int
mt7530_setup_vlan0(struct mt7530_priv * priv)1625 mt7530_setup_vlan0(struct mt7530_priv *priv)
1626 {
1627 u32 val;
1628
1629 /* Validate the entry with independent learning, keep the original
1630 * ingress tag attribute.
1631 */
1632 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
1633 VLAN_VALID;
1634 mt7530_write(priv, MT7530_VAWD1, val);
1635
1636 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
1637 }
1638
1639 static int
mt7530_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1640 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1641 const struct switchdev_obj_port_vlan *vlan,
1642 struct netlink_ext_ack *extack)
1643 {
1644 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1645 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1646 struct mt7530_hw_vlan_entry new_entry;
1647 struct mt7530_priv *priv = ds->priv;
1648
1649 mutex_lock(&priv->reg_mutex);
1650
1651 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1652 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
1653
1654 if (pvid) {
1655 priv->ports[port].pvid = vlan->vid;
1656
1657 /* Accept all frames if PVID is set */
1658 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1659 MT7530_VLAN_ACC_ALL);
1660
1661 /* Only configure PVID if VLAN filtering is enabled */
1662 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1663 mt7530_rmw(priv, MT7530_PPBV1_P(port),
1664 G0_PORT_VID_MASK,
1665 G0_PORT_VID(vlan->vid));
1666 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
1667 /* This VLAN is overwritten without PVID, so unset it */
1668 priv->ports[port].pvid = G0_PORT_VID_DEF;
1669
1670 /* Only accept tagged frames if the port is VLAN-aware */
1671 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1672 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1673 MT7530_VLAN_ACC_TAGGED);
1674
1675 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1676 G0_PORT_VID_DEF);
1677 }
1678
1679 mutex_unlock(&priv->reg_mutex);
1680
1681 return 0;
1682 }
1683
1684 static int
mt7530_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1685 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1686 const struct switchdev_obj_port_vlan *vlan)
1687 {
1688 struct mt7530_hw_vlan_entry target_entry;
1689 struct mt7530_priv *priv = ds->priv;
1690
1691 mutex_lock(&priv->reg_mutex);
1692
1693 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1694 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1695 mt7530_hw_vlan_del);
1696
1697 /* PVID is being restored to the default whenever the PVID port
1698 * is being removed from the VLAN.
1699 */
1700 if (priv->ports[port].pvid == vlan->vid) {
1701 priv->ports[port].pvid = G0_PORT_VID_DEF;
1702
1703 /* Only accept tagged frames if the port is VLAN-aware */
1704 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1705 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1706 MT7530_VLAN_ACC_TAGGED);
1707
1708 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1709 G0_PORT_VID_DEF);
1710 }
1711
1712
1713 mutex_unlock(&priv->reg_mutex);
1714
1715 return 0;
1716 }
1717
mt753x_mirror_port_get(unsigned int id,u32 val)1718 static int mt753x_mirror_port_get(unsigned int id, u32 val)
1719 {
1720 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1721 MIRROR_PORT(val);
1722 }
1723
mt753x_mirror_port_set(unsigned int id,u32 val)1724 static int mt753x_mirror_port_set(unsigned int id, u32 val)
1725 {
1726 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1727 MIRROR_PORT(val);
1728 }
1729
mt753x_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)1730 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
1731 struct dsa_mall_mirror_tc_entry *mirror,
1732 bool ingress, struct netlink_ext_ack *extack)
1733 {
1734 struct mt7530_priv *priv = ds->priv;
1735 int monitor_port;
1736 u32 val;
1737
1738 /* Check for existent entry */
1739 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1740 return -EEXIST;
1741
1742 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1743
1744 /* MT7530 only supports one monitor port */
1745 monitor_port = mt753x_mirror_port_get(priv->id, val);
1746 if (val & MT753X_MIRROR_EN(priv->id) &&
1747 monitor_port != mirror->to_local_port)
1748 return -EEXIST;
1749
1750 val |= MT753X_MIRROR_EN(priv->id);
1751 val &= ~MT753X_MIRROR_MASK(priv->id);
1752 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1753 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1754
1755 val = mt7530_read(priv, MT7530_PCR_P(port));
1756 if (ingress) {
1757 val |= PORT_RX_MIR;
1758 priv->mirror_rx |= BIT(port);
1759 } else {
1760 val |= PORT_TX_MIR;
1761 priv->mirror_tx |= BIT(port);
1762 }
1763 mt7530_write(priv, MT7530_PCR_P(port), val);
1764
1765 return 0;
1766 }
1767
mt753x_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)1768 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
1769 struct dsa_mall_mirror_tc_entry *mirror)
1770 {
1771 struct mt7530_priv *priv = ds->priv;
1772 u32 val;
1773
1774 val = mt7530_read(priv, MT7530_PCR_P(port));
1775 if (mirror->ingress) {
1776 val &= ~PORT_RX_MIR;
1777 priv->mirror_rx &= ~BIT(port);
1778 } else {
1779 val &= ~PORT_TX_MIR;
1780 priv->mirror_tx &= ~BIT(port);
1781 }
1782 mt7530_write(priv, MT7530_PCR_P(port), val);
1783
1784 if (!priv->mirror_rx && !priv->mirror_tx) {
1785 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1786 val &= ~MT753X_MIRROR_EN(priv->id);
1787 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1788 }
1789 }
1790
1791 static enum dsa_tag_protocol
mtk_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)1792 mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1793 enum dsa_tag_protocol mp)
1794 {
1795 return DSA_TAG_PROTO_MTK;
1796 }
1797
1798 #ifdef CONFIG_GPIOLIB
1799 static inline u32
mt7530_gpio_to_bit(unsigned int offset)1800 mt7530_gpio_to_bit(unsigned int offset)
1801 {
1802 /* Map GPIO offset to register bit
1803 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2
1804 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5
1805 * [10: 8] port 2 LED 0..2 as GPIO 6..8
1806 * [14:12] port 3 LED 0..2 as GPIO 9..11
1807 * [18:16] port 4 LED 0..2 as GPIO 12..14
1808 */
1809 return BIT(offset + offset / 3);
1810 }
1811
1812 static int
mt7530_gpio_get(struct gpio_chip * gc,unsigned int offset)1813 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1814 {
1815 struct mt7530_priv *priv = gpiochip_get_data(gc);
1816 u32 bit = mt7530_gpio_to_bit(offset);
1817
1818 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1819 }
1820
1821 static void
mt7530_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)1822 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1823 {
1824 struct mt7530_priv *priv = gpiochip_get_data(gc);
1825 u32 bit = mt7530_gpio_to_bit(offset);
1826
1827 if (value)
1828 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1829 else
1830 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1831 }
1832
1833 static int
mt7530_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)1834 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1835 {
1836 struct mt7530_priv *priv = gpiochip_get_data(gc);
1837 u32 bit = mt7530_gpio_to_bit(offset);
1838
1839 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1840 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1841 }
1842
1843 static int
mt7530_gpio_direction_input(struct gpio_chip * gc,unsigned int offset)1844 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1845 {
1846 struct mt7530_priv *priv = gpiochip_get_data(gc);
1847 u32 bit = mt7530_gpio_to_bit(offset);
1848
1849 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1850 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1851
1852 return 0;
1853 }
1854
1855 static int
mt7530_gpio_direction_output(struct gpio_chip * gc,unsigned int offset,int value)1856 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1857 {
1858 struct mt7530_priv *priv = gpiochip_get_data(gc);
1859 u32 bit = mt7530_gpio_to_bit(offset);
1860
1861 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1862
1863 if (value)
1864 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1865 else
1866 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1867
1868 mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1869
1870 return 0;
1871 }
1872
1873 static int
mt7530_setup_gpio(struct mt7530_priv * priv)1874 mt7530_setup_gpio(struct mt7530_priv *priv)
1875 {
1876 struct device *dev = priv->dev;
1877 struct gpio_chip *gc;
1878
1879 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1880 if (!gc)
1881 return -ENOMEM;
1882
1883 mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1884 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1885 mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1886
1887 gc->label = "mt7530";
1888 gc->parent = dev;
1889 gc->owner = THIS_MODULE;
1890 gc->get_direction = mt7530_gpio_get_direction;
1891 gc->direction_input = mt7530_gpio_direction_input;
1892 gc->direction_output = mt7530_gpio_direction_output;
1893 gc->get = mt7530_gpio_get;
1894 gc->set = mt7530_gpio_set;
1895 gc->base = -1;
1896 gc->ngpio = 15;
1897 gc->can_sleep = true;
1898
1899 return devm_gpiochip_add_data(dev, gc, priv);
1900 }
1901 #endif /* CONFIG_GPIOLIB */
1902
1903 static irqreturn_t
mt7530_irq_thread_fn(int irq,void * dev_id)1904 mt7530_irq_thread_fn(int irq, void *dev_id)
1905 {
1906 struct mt7530_priv *priv = dev_id;
1907 bool handled = false;
1908 u32 val;
1909 int p;
1910
1911 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1912 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
1913 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
1914 mutex_unlock(&priv->bus->mdio_lock);
1915
1916 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1917 if (BIT(p) & val) {
1918 unsigned int irq;
1919
1920 irq = irq_find_mapping(priv->irq_domain, p);
1921 handle_nested_irq(irq);
1922 handled = true;
1923 }
1924 }
1925
1926 return IRQ_RETVAL(handled);
1927 }
1928
1929 static void
mt7530_irq_mask(struct irq_data * d)1930 mt7530_irq_mask(struct irq_data *d)
1931 {
1932 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1933
1934 priv->irq_enable &= ~BIT(d->hwirq);
1935 }
1936
1937 static void
mt7530_irq_unmask(struct irq_data * d)1938 mt7530_irq_unmask(struct irq_data *d)
1939 {
1940 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1941
1942 priv->irq_enable |= BIT(d->hwirq);
1943 }
1944
1945 static void
mt7530_irq_bus_lock(struct irq_data * d)1946 mt7530_irq_bus_lock(struct irq_data *d)
1947 {
1948 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1949
1950 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1951 }
1952
1953 static void
mt7530_irq_bus_sync_unlock(struct irq_data * d)1954 mt7530_irq_bus_sync_unlock(struct irq_data *d)
1955 {
1956 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1957
1958 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1959 mutex_unlock(&priv->bus->mdio_lock);
1960 }
1961
1962 static struct irq_chip mt7530_irq_chip = {
1963 .name = KBUILD_MODNAME,
1964 .irq_mask = mt7530_irq_mask,
1965 .irq_unmask = mt7530_irq_unmask,
1966 .irq_bus_lock = mt7530_irq_bus_lock,
1967 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock,
1968 };
1969
1970 static int
mt7530_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)1971 mt7530_irq_map(struct irq_domain *domain, unsigned int irq,
1972 irq_hw_number_t hwirq)
1973 {
1974 irq_set_chip_data(irq, domain->host_data);
1975 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq);
1976 irq_set_nested_thread(irq, true);
1977 irq_set_noprobe(irq);
1978
1979 return 0;
1980 }
1981
1982 static const struct irq_domain_ops mt7530_irq_domain_ops = {
1983 .map = mt7530_irq_map,
1984 .xlate = irq_domain_xlate_onecell,
1985 };
1986
1987 static void
mt7530_setup_mdio_irq(struct mt7530_priv * priv)1988 mt7530_setup_mdio_irq(struct mt7530_priv *priv)
1989 {
1990 struct dsa_switch *ds = priv->ds;
1991 int p;
1992
1993 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1994 if (BIT(p) & ds->phys_mii_mask) {
1995 unsigned int irq;
1996
1997 irq = irq_create_mapping(priv->irq_domain, p);
1998 ds->slave_mii_bus->irq[p] = irq;
1999 }
2000 }
2001 }
2002
2003 static int
mt7530_setup_irq(struct mt7530_priv * priv)2004 mt7530_setup_irq(struct mt7530_priv *priv)
2005 {
2006 struct device *dev = priv->dev;
2007 struct device_node *np = dev->of_node;
2008 int ret;
2009
2010 if (!of_property_read_bool(np, "interrupt-controller")) {
2011 dev_info(dev, "no interrupt support\n");
2012 return 0;
2013 }
2014
2015 priv->irq = of_irq_get(np, 0);
2016 if (priv->irq <= 0) {
2017 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq);
2018 return priv->irq ? : -EINVAL;
2019 }
2020
2021 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
2022 &mt7530_irq_domain_ops, priv);
2023 if (!priv->irq_domain) {
2024 dev_err(dev, "failed to create IRQ domain\n");
2025 return -ENOMEM;
2026 }
2027
2028 /* This register must be set for MT7530 to properly fire interrupts */
2029 if (priv->id != ID_MT7531)
2030 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
2031
2032 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
2033 IRQF_ONESHOT, KBUILD_MODNAME, priv);
2034 if (ret) {
2035 irq_domain_remove(priv->irq_domain);
2036 dev_err(dev, "failed to request IRQ: %d\n", ret);
2037 return ret;
2038 }
2039
2040 return 0;
2041 }
2042
2043 static void
mt7530_free_mdio_irq(struct mt7530_priv * priv)2044 mt7530_free_mdio_irq(struct mt7530_priv *priv)
2045 {
2046 int p;
2047
2048 for (p = 0; p < MT7530_NUM_PHYS; p++) {
2049 if (BIT(p) & priv->ds->phys_mii_mask) {
2050 unsigned int irq;
2051
2052 irq = irq_find_mapping(priv->irq_domain, p);
2053 irq_dispose_mapping(irq);
2054 }
2055 }
2056 }
2057
2058 static void
mt7530_free_irq_common(struct mt7530_priv * priv)2059 mt7530_free_irq_common(struct mt7530_priv *priv)
2060 {
2061 free_irq(priv->irq, priv);
2062 irq_domain_remove(priv->irq_domain);
2063 }
2064
2065 static void
mt7530_free_irq(struct mt7530_priv * priv)2066 mt7530_free_irq(struct mt7530_priv *priv)
2067 {
2068 mt7530_free_mdio_irq(priv);
2069 mt7530_free_irq_common(priv);
2070 }
2071
2072 static int
mt7530_setup_mdio(struct mt7530_priv * priv)2073 mt7530_setup_mdio(struct mt7530_priv *priv)
2074 {
2075 struct dsa_switch *ds = priv->ds;
2076 struct device *dev = priv->dev;
2077 struct mii_bus *bus;
2078 static int idx;
2079 int ret;
2080
2081 bus = devm_mdiobus_alloc(dev);
2082 if (!bus)
2083 return -ENOMEM;
2084
2085 ds->slave_mii_bus = bus;
2086 bus->priv = priv;
2087 bus->name = KBUILD_MODNAME "-mii";
2088 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
2089 bus->read = mt753x_phy_read;
2090 bus->write = mt753x_phy_write;
2091 bus->parent = dev;
2092 bus->phy_mask = ~ds->phys_mii_mask;
2093
2094 if (priv->irq)
2095 mt7530_setup_mdio_irq(priv);
2096
2097 ret = devm_mdiobus_register(dev, bus);
2098 if (ret) {
2099 dev_err(dev, "failed to register MDIO bus: %d\n", ret);
2100 if (priv->irq)
2101 mt7530_free_mdio_irq(priv);
2102 }
2103
2104 return ret;
2105 }
2106
2107 static int
mt7530_setup(struct dsa_switch * ds)2108 mt7530_setup(struct dsa_switch *ds)
2109 {
2110 struct mt7530_priv *priv = ds->priv;
2111 struct device_node *dn = NULL;
2112 struct device_node *phy_node;
2113 struct device_node *mac_np;
2114 struct mt7530_dummy_poll p;
2115 phy_interface_t interface;
2116 struct dsa_port *cpu_dp;
2117 u32 id, val;
2118 int ret, i;
2119
2120 /* The parent node of master netdev which holds the common system
2121 * controller also is the container for two GMACs nodes representing
2122 * as two netdev instances.
2123 */
2124 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
2125 dn = cpu_dp->master->dev.of_node->parent;
2126 /* It doesn't matter which CPU port is found first,
2127 * their masters should share the same parent OF node
2128 */
2129 break;
2130 }
2131
2132 if (!dn) {
2133 dev_err(ds->dev, "parent OF node of DSA master not found");
2134 return -EINVAL;
2135 }
2136
2137 ds->assisted_learning_on_cpu_port = true;
2138 ds->mtu_enforcement_ingress = true;
2139
2140 if (priv->id == ID_MT7530) {
2141 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
2142 ret = regulator_enable(priv->core_pwr);
2143 if (ret < 0) {
2144 dev_err(priv->dev,
2145 "Failed to enable core power: %d\n", ret);
2146 return ret;
2147 }
2148
2149 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
2150 ret = regulator_enable(priv->io_pwr);
2151 if (ret < 0) {
2152 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
2153 ret);
2154 return ret;
2155 }
2156 }
2157
2158 /* Reset whole chip through gpio pin or memory-mapped registers for
2159 * different type of hardware
2160 */
2161 if (priv->mcm) {
2162 reset_control_assert(priv->rstc);
2163 usleep_range(1000, 1100);
2164 reset_control_deassert(priv->rstc);
2165 } else {
2166 gpiod_set_value_cansleep(priv->reset, 0);
2167 usleep_range(1000, 1100);
2168 gpiod_set_value_cansleep(priv->reset, 1);
2169 }
2170
2171 /* Waiting for MT7530 got to stable */
2172 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2173 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2174 20, 1000000);
2175 if (ret < 0) {
2176 dev_err(priv->dev, "reset timeout\n");
2177 return ret;
2178 }
2179
2180 id = mt7530_read(priv, MT7530_CREV);
2181 id >>= CHIP_NAME_SHIFT;
2182 if (id != MT7530_ID) {
2183 dev_err(priv->dev, "chip %x can't be supported\n", id);
2184 return -ENODEV;
2185 }
2186
2187 /* Reset the switch through internal reset */
2188 mt7530_write(priv, MT7530_SYS_CTRL,
2189 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2190 SYS_CTRL_REG_RST);
2191
2192 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
2193 val = mt7530_read(priv, MT7530_MHWTRAP);
2194 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
2195 val |= MHWTRAP_MANUAL;
2196 mt7530_write(priv, MT7530_MHWTRAP, val);
2197
2198 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2199
2200 /* Enable and reset MIB counters */
2201 mt7530_mib_reset(ds);
2202
2203 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2204 /* Disable forwarding by default on all ports */
2205 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2206 PCR_MATRIX_CLR);
2207
2208 /* Disable learning by default on all ports */
2209 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2210
2211 if (dsa_is_cpu_port(ds, i)) {
2212 ret = mt753x_cpu_port_enable(ds, i);
2213 if (ret)
2214 return ret;
2215 } else {
2216 mt7530_port_disable(ds, i);
2217
2218 /* Set default PVID to 0 on all user ports */
2219 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2220 G0_PORT_VID_DEF);
2221 }
2222 /* Enable consistent egress tag */
2223 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2224 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2225 }
2226
2227 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2228 ret = mt7530_setup_vlan0(priv);
2229 if (ret)
2230 return ret;
2231
2232 /* Setup port 5 */
2233 priv->p5_intf_sel = P5_DISABLED;
2234 interface = PHY_INTERFACE_MODE_NA;
2235
2236 if (!dsa_is_unused_port(ds, 5)) {
2237 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2238 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
2239 if (ret && ret != -ENODEV)
2240 return ret;
2241 } else {
2242 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
2243 for_each_child_of_node(dn, mac_np) {
2244 if (!of_device_is_compatible(mac_np,
2245 "mediatek,eth-mac"))
2246 continue;
2247
2248 ret = of_property_read_u32(mac_np, "reg", &id);
2249 if (ret < 0 || id != 1)
2250 continue;
2251
2252 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
2253 if (!phy_node)
2254 continue;
2255
2256 if (phy_node->parent == priv->dev->of_node->parent) {
2257 ret = of_get_phy_mode(mac_np, &interface);
2258 if (ret && ret != -ENODEV) {
2259 of_node_put(mac_np);
2260 of_node_put(phy_node);
2261 return ret;
2262 }
2263 id = of_mdio_parse_addr(ds->dev, phy_node);
2264 if (id == 0)
2265 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
2266 if (id == 4)
2267 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
2268 }
2269 of_node_put(mac_np);
2270 of_node_put(phy_node);
2271 break;
2272 }
2273 }
2274
2275 #ifdef CONFIG_GPIOLIB
2276 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
2277 ret = mt7530_setup_gpio(priv);
2278 if (ret)
2279 return ret;
2280 }
2281 #endif /* CONFIG_GPIOLIB */
2282
2283 mt7530_setup_port5(ds, interface);
2284
2285 /* Flush the FDB table */
2286 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2287 if (ret < 0)
2288 return ret;
2289
2290 return 0;
2291 }
2292
2293 static int
mt7531_setup(struct dsa_switch * ds)2294 mt7531_setup(struct dsa_switch *ds)
2295 {
2296 struct mt7530_priv *priv = ds->priv;
2297 struct mt7530_dummy_poll p;
2298 struct dsa_port *cpu_dp;
2299 u32 val, id;
2300 int ret, i;
2301
2302 /* Reset whole chip through gpio pin or memory-mapped registers for
2303 * different type of hardware
2304 */
2305 if (priv->mcm) {
2306 reset_control_assert(priv->rstc);
2307 usleep_range(1000, 1100);
2308 reset_control_deassert(priv->rstc);
2309 } else {
2310 gpiod_set_value_cansleep(priv->reset, 0);
2311 usleep_range(1000, 1100);
2312 gpiod_set_value_cansleep(priv->reset, 1);
2313 }
2314
2315 /* Waiting for MT7530 got to stable */
2316 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2317 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2318 20, 1000000);
2319 if (ret < 0) {
2320 dev_err(priv->dev, "reset timeout\n");
2321 return ret;
2322 }
2323
2324 id = mt7530_read(priv, MT7531_CREV);
2325 id >>= CHIP_NAME_SHIFT;
2326
2327 if (id != MT7531_ID) {
2328 dev_err(priv->dev, "chip %x can't be supported\n", id);
2329 return -ENODEV;
2330 }
2331
2332 /* all MACs must be forced link-down before sw reset */
2333 for (i = 0; i < MT7530_NUM_PORTS; i++)
2334 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
2335
2336 /* Reset the switch through internal reset */
2337 mt7530_write(priv, MT7530_SYS_CTRL,
2338 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2339 SYS_CTRL_REG_RST);
2340
2341 mt7531_pll_setup(priv);
2342
2343 if (mt7531_dual_sgmii_supported(priv)) {
2344 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
2345
2346 /* Let ds->slave_mii_bus be able to access external phy. */
2347 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
2348 MT7531_EXT_P_MDC_11);
2349 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
2350 MT7531_EXT_P_MDIO_12);
2351 } else {
2352 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2353 }
2354 dev_dbg(ds->dev, "P5 support %s interface\n",
2355 p5_intf_modes(priv->p5_intf_sel));
2356
2357 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
2358 MT7531_GPIO0_INTERRUPT);
2359
2360 /* Let phylink decide the interface later. */
2361 priv->p5_interface = PHY_INTERFACE_MODE_NA;
2362 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2363
2364 /* Enable PHY core PLL, since phy_device has not yet been created
2365 * provided for phy_[read,write]_mmd_indirect is called, we provide
2366 * our own mt7531_ind_mmd_phy_[read,write] to complete this
2367 * function.
2368 */
2369 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
2370 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2371 val |= MT7531_PHY_PLL_BYPASS_MODE;
2372 val &= ~MT7531_PHY_PLL_OFF;
2373 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
2374 CORE_PLL_GROUP4, val);
2375
2376 /* BPDU to CPU port */
2377 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
2378 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
2379 BIT(cpu_dp->index));
2380 break;
2381 }
2382 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
2383 MT753X_BPDU_CPU_ONLY);
2384
2385 /* Enable and reset MIB counters */
2386 mt7530_mib_reset(ds);
2387
2388 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2389 /* Disable forwarding by default on all ports */
2390 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2391 PCR_MATRIX_CLR);
2392
2393 /* Disable learning by default on all ports */
2394 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2395
2396 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
2397
2398 if (dsa_is_cpu_port(ds, i)) {
2399 ret = mt753x_cpu_port_enable(ds, i);
2400 if (ret)
2401 return ret;
2402 } else {
2403 mt7530_port_disable(ds, i);
2404
2405 /* Set default PVID to 0 on all user ports */
2406 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2407 G0_PORT_VID_DEF);
2408 }
2409
2410 /* Enable consistent egress tag */
2411 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2412 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2413 }
2414
2415 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2416 ret = mt7530_setup_vlan0(priv);
2417 if (ret)
2418 return ret;
2419
2420 ds->assisted_learning_on_cpu_port = true;
2421 ds->mtu_enforcement_ingress = true;
2422
2423 /* Flush the FDB table */
2424 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2425 if (ret < 0)
2426 return ret;
2427
2428 return 0;
2429 }
2430
mt7530_mac_port_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)2431 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
2432 struct phylink_config *config)
2433 {
2434 switch (port) {
2435 case 0 ... 4: /* Internal phy */
2436 __set_bit(PHY_INTERFACE_MODE_GMII,
2437 config->supported_interfaces);
2438 break;
2439
2440 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2441 phy_interface_set_rgmii(config->supported_interfaces);
2442 __set_bit(PHY_INTERFACE_MODE_MII,
2443 config->supported_interfaces);
2444 __set_bit(PHY_INTERFACE_MODE_GMII,
2445 config->supported_interfaces);
2446 break;
2447
2448 case 6: /* 1st cpu port */
2449 __set_bit(PHY_INTERFACE_MODE_RGMII,
2450 config->supported_interfaces);
2451 __set_bit(PHY_INTERFACE_MODE_TRGMII,
2452 config->supported_interfaces);
2453 break;
2454 }
2455 }
2456
mt7531_is_rgmii_port(struct mt7530_priv * priv,u32 port)2457 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
2458 {
2459 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
2460 }
2461
mt7531_mac_port_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)2462 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
2463 struct phylink_config *config)
2464 {
2465 struct mt7530_priv *priv = ds->priv;
2466
2467 switch (port) {
2468 case 0 ... 4: /* Internal phy */
2469 __set_bit(PHY_INTERFACE_MODE_GMII,
2470 config->supported_interfaces);
2471 break;
2472
2473 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
2474 if (mt7531_is_rgmii_port(priv, port)) {
2475 phy_interface_set_rgmii(config->supported_interfaces);
2476 break;
2477 }
2478 fallthrough;
2479
2480 case 6: /* 1st cpu port supports sgmii/8023z only */
2481 __set_bit(PHY_INTERFACE_MODE_SGMII,
2482 config->supported_interfaces);
2483 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
2484 config->supported_interfaces);
2485 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
2486 config->supported_interfaces);
2487
2488 config->mac_capabilities |= MAC_2500FD;
2489 break;
2490 }
2491 }
2492
2493 static int
mt753x_pad_setup(struct dsa_switch * ds,const struct phylink_link_state * state)2494 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2495 {
2496 struct mt7530_priv *priv = ds->priv;
2497
2498 return priv->info->pad_setup(ds, state->interface);
2499 }
2500
2501 static int
mt7530_mac_config(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2502 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2503 phy_interface_t interface)
2504 {
2505 struct mt7530_priv *priv = ds->priv;
2506
2507 /* Only need to setup port5. */
2508 if (port != 5)
2509 return 0;
2510
2511 mt7530_setup_port5(priv->ds, interface);
2512
2513 return 0;
2514 }
2515
mt7531_rgmii_setup(struct mt7530_priv * priv,u32 port,phy_interface_t interface,struct phy_device * phydev)2516 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2517 phy_interface_t interface,
2518 struct phy_device *phydev)
2519 {
2520 u32 val;
2521
2522 if (!mt7531_is_rgmii_port(priv, port)) {
2523 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2524 port);
2525 return -EINVAL;
2526 }
2527
2528 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2529 val |= GP_CLK_EN;
2530 val &= ~GP_MODE_MASK;
2531 val |= GP_MODE(MT7531_GP_MODE_RGMII);
2532 val &= ~CLK_SKEW_IN_MASK;
2533 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2534 val &= ~CLK_SKEW_OUT_MASK;
2535 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2536 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2537
2538 /* Do not adjust rgmii delay when vendor phy driver presents. */
2539 if (!phydev || phy_driver_is_genphy(phydev)) {
2540 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2541 switch (interface) {
2542 case PHY_INTERFACE_MODE_RGMII:
2543 val |= TXCLK_NO_REVERSE;
2544 val |= RXCLK_NO_DELAY;
2545 break;
2546 case PHY_INTERFACE_MODE_RGMII_RXID:
2547 val |= TXCLK_NO_REVERSE;
2548 break;
2549 case PHY_INTERFACE_MODE_RGMII_TXID:
2550 val |= RXCLK_NO_DELAY;
2551 break;
2552 case PHY_INTERFACE_MODE_RGMII_ID:
2553 break;
2554 default:
2555 return -EINVAL;
2556 }
2557 }
2558 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2559
2560 return 0;
2561 }
2562
mt7531_pcs_link_up(struct phylink_pcs * pcs,unsigned int mode,phy_interface_t interface,int speed,int duplex)2563 static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
2564 phy_interface_t interface, int speed, int duplex)
2565 {
2566 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
2567 int port = pcs_to_mt753x_pcs(pcs)->port;
2568 unsigned int val;
2569
2570 /* For adjusting speed and duplex of SGMII force mode. */
2571 if (interface != PHY_INTERFACE_MODE_SGMII ||
2572 phylink_autoneg_inband(mode))
2573 return;
2574
2575 /* SGMII force mode setting */
2576 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
2577 val &= ~MT7531_SGMII_IF_MODE_MASK;
2578
2579 switch (speed) {
2580 case SPEED_10:
2581 val |= MT7531_SGMII_FORCE_SPEED_10;
2582 break;
2583 case SPEED_100:
2584 val |= MT7531_SGMII_FORCE_SPEED_100;
2585 break;
2586 case SPEED_1000:
2587 val |= MT7531_SGMII_FORCE_SPEED_1000;
2588 break;
2589 }
2590
2591 /* MT7531 SGMII 1G force mode can only work in full duplex mode,
2592 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2593 *
2594 * The speed check is unnecessary as the MAC capabilities apply
2595 * this restriction. --rmk
2596 */
2597 if ((speed == SPEED_10 || speed == SPEED_100) &&
2598 duplex != DUPLEX_FULL)
2599 val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2600
2601 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2602 }
2603
mt753x_is_mac_port(u32 port)2604 static bool mt753x_is_mac_port(u32 port)
2605 {
2606 return (port == 5 || port == 6);
2607 }
2608
mt7531_sgmii_setup_mode_force(struct mt7530_priv * priv,u32 port,phy_interface_t interface)2609 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2610 phy_interface_t interface)
2611 {
2612 u32 val;
2613
2614 if (!mt753x_is_mac_port(port))
2615 return -EINVAL;
2616
2617 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2618 MT7531_SGMII_PHYA_PWD);
2619
2620 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2621 val &= ~MT7531_RG_TPHY_SPEED_MASK;
2622 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2623 * encoding.
2624 */
2625 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2626 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2627 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2628
2629 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2630
2631 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2632 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2633 */
2634 mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2635 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2636 MT7531_SGMII_FORCE_SPEED_1000);
2637
2638 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2639
2640 return 0;
2641 }
2642
mt7531_sgmii_setup_mode_an(struct mt7530_priv * priv,int port,phy_interface_t interface)2643 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2644 phy_interface_t interface)
2645 {
2646 if (!mt753x_is_mac_port(port))
2647 return -EINVAL;
2648
2649 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2650 MT7531_SGMII_PHYA_PWD);
2651
2652 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2653 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2654
2655 mt7530_set(priv, MT7531_SGMII_MODE(port),
2656 MT7531_SGMII_REMOTE_FAULT_DIS |
2657 MT7531_SGMII_SPEED_DUPLEX_AN);
2658
2659 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2660 MT7531_SGMII_TX_CONFIG_MASK, 1);
2661
2662 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2663
2664 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2665
2666 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2667
2668 return 0;
2669 }
2670
mt7531_pcs_an_restart(struct phylink_pcs * pcs)2671 static void mt7531_pcs_an_restart(struct phylink_pcs *pcs)
2672 {
2673 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
2674 int port = pcs_to_mt753x_pcs(pcs)->port;
2675 u32 val;
2676
2677 /* Only restart AN when AN is enabled */
2678 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2679 if (val & MT7531_SGMII_AN_ENABLE) {
2680 val |= MT7531_SGMII_AN_RESTART;
2681 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2682 }
2683 }
2684
2685 static int
mt7531_mac_config(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2686 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2687 phy_interface_t interface)
2688 {
2689 struct mt7530_priv *priv = ds->priv;
2690 struct phy_device *phydev;
2691 struct dsa_port *dp;
2692
2693 if (!mt753x_is_mac_port(port)) {
2694 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2695 return -EINVAL;
2696 }
2697
2698 switch (interface) {
2699 case PHY_INTERFACE_MODE_RGMII:
2700 case PHY_INTERFACE_MODE_RGMII_ID:
2701 case PHY_INTERFACE_MODE_RGMII_RXID:
2702 case PHY_INTERFACE_MODE_RGMII_TXID:
2703 dp = dsa_to_port(ds, port);
2704 phydev = dp->slave->phydev;
2705 return mt7531_rgmii_setup(priv, port, interface, phydev);
2706 case PHY_INTERFACE_MODE_SGMII:
2707 return mt7531_sgmii_setup_mode_an(priv, port, interface);
2708 case PHY_INTERFACE_MODE_NA:
2709 case PHY_INTERFACE_MODE_1000BASEX:
2710 case PHY_INTERFACE_MODE_2500BASEX:
2711 return mt7531_sgmii_setup_mode_force(priv, port, interface);
2712 default:
2713 return -EINVAL;
2714 }
2715
2716 return -EINVAL;
2717 }
2718
2719 static int
mt753x_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)2720 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2721 const struct phylink_link_state *state)
2722 {
2723 struct mt7530_priv *priv = ds->priv;
2724
2725 return priv->info->mac_port_config(ds, port, mode, state->interface);
2726 }
2727
2728 static struct phylink_pcs *
mt753x_phylink_mac_select_pcs(struct dsa_switch * ds,int port,phy_interface_t interface)2729 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
2730 phy_interface_t interface)
2731 {
2732 struct mt7530_priv *priv = ds->priv;
2733
2734 switch (interface) {
2735 case PHY_INTERFACE_MODE_TRGMII:
2736 case PHY_INTERFACE_MODE_SGMII:
2737 case PHY_INTERFACE_MODE_1000BASEX:
2738 case PHY_INTERFACE_MODE_2500BASEX:
2739 return &priv->pcs[port].pcs;
2740
2741 default:
2742 return NULL;
2743 }
2744 }
2745
2746 static void
mt753x_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)2747 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2748 const struct phylink_link_state *state)
2749 {
2750 struct mt7530_priv *priv = ds->priv;
2751 u32 mcr_cur, mcr_new;
2752
2753 switch (port) {
2754 case 0 ... 4: /* Internal phy */
2755 if (state->interface != PHY_INTERFACE_MODE_GMII)
2756 goto unsupported;
2757 break;
2758 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2759 if (priv->p5_interface == state->interface)
2760 break;
2761
2762 if (mt753x_mac_config(ds, port, mode, state) < 0)
2763 goto unsupported;
2764
2765 if (priv->p5_intf_sel != P5_DISABLED)
2766 priv->p5_interface = state->interface;
2767 break;
2768 case 6: /* 1st cpu port */
2769 if (priv->p6_interface == state->interface)
2770 break;
2771
2772 mt753x_pad_setup(ds, state);
2773
2774 if (mt753x_mac_config(ds, port, mode, state) < 0)
2775 goto unsupported;
2776
2777 priv->p6_interface = state->interface;
2778 break;
2779 default:
2780 unsupported:
2781 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2782 __func__, phy_modes(state->interface), port);
2783 return;
2784 }
2785
2786 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2787 mcr_new = mcr_cur;
2788 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
2789 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
2790 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
2791
2792 /* Are we connected to external phy */
2793 if (port == 5 && dsa_is_user_port(ds, 5))
2794 mcr_new |= PMCR_EXT_PHY;
2795
2796 if (mcr_new != mcr_cur)
2797 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2798 }
2799
mt753x_phylink_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2800 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
2801 unsigned int mode,
2802 phy_interface_t interface)
2803 {
2804 struct mt7530_priv *priv = ds->priv;
2805
2806 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
2807 }
2808
mt753x_phylink_pcs_link_up(struct phylink_pcs * pcs,unsigned int mode,phy_interface_t interface,int speed,int duplex)2809 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs,
2810 unsigned int mode,
2811 phy_interface_t interface,
2812 int speed, int duplex)
2813 {
2814 if (pcs->ops->pcs_link_up)
2815 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
2816 }
2817
mt753x_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)2818 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
2819 unsigned int mode,
2820 phy_interface_t interface,
2821 struct phy_device *phydev,
2822 int speed, int duplex,
2823 bool tx_pause, bool rx_pause)
2824 {
2825 struct mt7530_priv *priv = ds->priv;
2826 u32 mcr;
2827
2828 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2829
2830 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2831 * variants.
2832 */
2833 if (interface == PHY_INTERFACE_MODE_TRGMII ||
2834 (phy_interface_mode_is_8023z(interface))) {
2835 speed = SPEED_1000;
2836 duplex = DUPLEX_FULL;
2837 }
2838
2839 switch (speed) {
2840 case SPEED_1000:
2841 mcr |= PMCR_FORCE_SPEED_1000;
2842 break;
2843 case SPEED_100:
2844 mcr |= PMCR_FORCE_SPEED_100;
2845 break;
2846 }
2847 if (duplex == DUPLEX_FULL) {
2848 mcr |= PMCR_FORCE_FDX;
2849 if (tx_pause)
2850 mcr |= PMCR_TX_FC_EN;
2851 if (rx_pause)
2852 mcr |= PMCR_RX_FC_EN;
2853 }
2854
2855 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
2856 switch (speed) {
2857 case SPEED_1000:
2858 mcr |= PMCR_FORCE_EEE1G;
2859 break;
2860 case SPEED_100:
2861 mcr |= PMCR_FORCE_EEE100;
2862 break;
2863 }
2864 }
2865
2866 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
2867 }
2868
2869 static int
mt7531_cpu_port_config(struct dsa_switch * ds,int port)2870 mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2871 {
2872 struct mt7530_priv *priv = ds->priv;
2873 phy_interface_t interface;
2874 int speed;
2875 int ret;
2876
2877 switch (port) {
2878 case 5:
2879 if (mt7531_is_rgmii_port(priv, port))
2880 interface = PHY_INTERFACE_MODE_RGMII;
2881 else
2882 interface = PHY_INTERFACE_MODE_2500BASEX;
2883
2884 priv->p5_interface = interface;
2885 break;
2886 case 6:
2887 interface = PHY_INTERFACE_MODE_2500BASEX;
2888
2889 priv->p6_interface = interface;
2890 break;
2891 default:
2892 return -EINVAL;
2893 }
2894
2895 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2896 speed = SPEED_2500;
2897 else
2898 speed = SPEED_1000;
2899
2900 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2901 if (ret)
2902 return ret;
2903 mt7530_write(priv, MT7530_PMCR_P(port),
2904 PMCR_CPU_PORT_SETTING(priv->id));
2905 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED,
2906 interface, speed, DUPLEX_FULL);
2907 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2908 speed, DUPLEX_FULL, true, true);
2909
2910 return 0;
2911 }
2912
mt753x_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)2913 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
2914 struct phylink_config *config)
2915 {
2916 struct mt7530_priv *priv = ds->priv;
2917
2918 /* This switch only supports full-duplex at 1Gbps */
2919 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
2920 MAC_10 | MAC_100 | MAC_1000FD;
2921
2922 if ((priv->id == ID_MT7531) && mt753x_is_mac_port(port))
2923 config->mac_capabilities |= MAC_2500FD;
2924
2925 /* This driver does not make use of the speed, duplex, pause or the
2926 * advertisement in its mac_config, so it is safe to mark this driver
2927 * as non-legacy.
2928 */
2929 config->legacy_pre_march2020 = false;
2930
2931 priv->info->mac_port_get_caps(ds, port, config);
2932 }
2933
mt753x_pcs_validate(struct phylink_pcs * pcs,unsigned long * supported,const struct phylink_link_state * state)2934 static int mt753x_pcs_validate(struct phylink_pcs *pcs,
2935 unsigned long *supported,
2936 const struct phylink_link_state *state)
2937 {
2938 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */
2939 if (state->interface == PHY_INTERFACE_MODE_TRGMII ||
2940 phy_interface_mode_is_8023z(state->interface))
2941 phylink_clear(supported, Autoneg);
2942
2943 return 0;
2944 }
2945
mt7530_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)2946 static void mt7530_pcs_get_state(struct phylink_pcs *pcs,
2947 struct phylink_link_state *state)
2948 {
2949 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
2950 int port = pcs_to_mt753x_pcs(pcs)->port;
2951 u32 pmsr;
2952
2953 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2954
2955 state->link = (pmsr & PMSR_LINK);
2956 state->an_complete = state->link;
2957 state->duplex = !!(pmsr & PMSR_DPX);
2958
2959 switch (pmsr & PMSR_SPEED_MASK) {
2960 case PMSR_SPEED_10:
2961 state->speed = SPEED_10;
2962 break;
2963 case PMSR_SPEED_100:
2964 state->speed = SPEED_100;
2965 break;
2966 case PMSR_SPEED_1000:
2967 state->speed = SPEED_1000;
2968 break;
2969 default:
2970 state->speed = SPEED_UNKNOWN;
2971 break;
2972 }
2973
2974 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2975 if (pmsr & PMSR_RX_FC)
2976 state->pause |= MLO_PAUSE_RX;
2977 if (pmsr & PMSR_TX_FC)
2978 state->pause |= MLO_PAUSE_TX;
2979 }
2980
2981 static int
mt7531_sgmii_pcs_get_state_an(struct mt7530_priv * priv,int port,struct phylink_link_state * state)2982 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
2983 struct phylink_link_state *state)
2984 {
2985 u32 status, val;
2986 u16 config_reg;
2987
2988 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2989 state->link = !!(status & MT7531_SGMII_LINK_STATUS);
2990 state->an_complete = !!(status & MT7531_SGMII_AN_COMPLETE);
2991 if (state->interface == PHY_INTERFACE_MODE_SGMII &&
2992 (status & MT7531_SGMII_AN_ENABLE)) {
2993 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
2994 config_reg = val >> 16;
2995
2996 switch (config_reg & LPA_SGMII_SPD_MASK) {
2997 case LPA_SGMII_1000:
2998 state->speed = SPEED_1000;
2999 break;
3000 case LPA_SGMII_100:
3001 state->speed = SPEED_100;
3002 break;
3003 case LPA_SGMII_10:
3004 state->speed = SPEED_10;
3005 break;
3006 default:
3007 dev_err(priv->dev, "invalid sgmii PHY speed\n");
3008 state->link = false;
3009 return -EINVAL;
3010 }
3011
3012 if (config_reg & LPA_SGMII_FULL_DUPLEX)
3013 state->duplex = DUPLEX_FULL;
3014 else
3015 state->duplex = DUPLEX_HALF;
3016 }
3017
3018 return 0;
3019 }
3020
3021 static void
mt7531_sgmii_pcs_get_state_inband(struct mt7530_priv * priv,int port,struct phylink_link_state * state)3022 mt7531_sgmii_pcs_get_state_inband(struct mt7530_priv *priv, int port,
3023 struct phylink_link_state *state)
3024 {
3025 unsigned int val;
3026
3027 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
3028 state->link = !!(val & MT7531_SGMII_LINK_STATUS);
3029 if (!state->link)
3030 return;
3031
3032 state->an_complete = state->link;
3033
3034 if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
3035 state->speed = SPEED_2500;
3036 else
3037 state->speed = SPEED_1000;
3038
3039 state->duplex = DUPLEX_FULL;
3040 state->pause = MLO_PAUSE_NONE;
3041 }
3042
mt7531_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)3043 static void mt7531_pcs_get_state(struct phylink_pcs *pcs,
3044 struct phylink_link_state *state)
3045 {
3046 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
3047 int port = pcs_to_mt753x_pcs(pcs)->port;
3048
3049 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
3050 mt7531_sgmii_pcs_get_state_an(priv, port, state);
3051 return;
3052 } else if ((state->interface == PHY_INTERFACE_MODE_1000BASEX) ||
3053 (state->interface == PHY_INTERFACE_MODE_2500BASEX)) {
3054 mt7531_sgmii_pcs_get_state_inband(priv, port, state);
3055 return;
3056 }
3057
3058 state->link = false;
3059 }
3060
mt753x_pcs_config(struct phylink_pcs * pcs,unsigned int mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)3061 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
3062 phy_interface_t interface,
3063 const unsigned long *advertising,
3064 bool permit_pause_to_mac)
3065 {
3066 return 0;
3067 }
3068
mt7530_pcs_an_restart(struct phylink_pcs * pcs)3069 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs)
3070 {
3071 }
3072
3073 static const struct phylink_pcs_ops mt7530_pcs_ops = {
3074 .pcs_validate = mt753x_pcs_validate,
3075 .pcs_get_state = mt7530_pcs_get_state,
3076 .pcs_config = mt753x_pcs_config,
3077 .pcs_an_restart = mt7530_pcs_an_restart,
3078 };
3079
3080 static const struct phylink_pcs_ops mt7531_pcs_ops = {
3081 .pcs_validate = mt753x_pcs_validate,
3082 .pcs_get_state = mt7531_pcs_get_state,
3083 .pcs_config = mt753x_pcs_config,
3084 .pcs_an_restart = mt7531_pcs_an_restart,
3085 .pcs_link_up = mt7531_pcs_link_up,
3086 };
3087
3088 static int
mt753x_setup(struct dsa_switch * ds)3089 mt753x_setup(struct dsa_switch *ds)
3090 {
3091 struct mt7530_priv *priv = ds->priv;
3092 int i, ret;
3093
3094 /* Initialise the PCS devices */
3095 for (i = 0; i < priv->ds->num_ports; i++) {
3096 priv->pcs[i].pcs.ops = priv->info->pcs_ops;
3097 priv->pcs[i].priv = priv;
3098 priv->pcs[i].port = i;
3099 if (mt753x_is_mac_port(i))
3100 priv->pcs[i].pcs.poll = 1;
3101 }
3102
3103 ret = priv->info->sw_setup(ds);
3104 if (ret)
3105 return ret;
3106
3107 ret = mt7530_setup_irq(priv);
3108 if (ret)
3109 return ret;
3110
3111 ret = mt7530_setup_mdio(priv);
3112 if (ret && priv->irq)
3113 mt7530_free_irq_common(priv);
3114
3115 return ret;
3116 }
3117
mt753x_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)3118 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,
3119 struct ethtool_eee *e)
3120 {
3121 struct mt7530_priv *priv = ds->priv;
3122 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
3123
3124 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
3125 e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
3126
3127 return 0;
3128 }
3129
mt753x_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)3130 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
3131 struct ethtool_eee *e)
3132 {
3133 struct mt7530_priv *priv = ds->priv;
3134 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;
3135
3136 if (e->tx_lpi_timer > 0xFFF)
3137 return -EINVAL;
3138
3139 set = SET_LPI_THRESH(e->tx_lpi_timer);
3140 if (!e->tx_lpi_enabled)
3141 /* Force LPI Mode without a delay */
3142 set |= LPI_MODE_EN;
3143 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
3144
3145 return 0;
3146 }
3147
3148 static const struct dsa_switch_ops mt7530_switch_ops = {
3149 .get_tag_protocol = mtk_get_tag_protocol,
3150 .setup = mt753x_setup,
3151 .get_strings = mt7530_get_strings,
3152 .get_ethtool_stats = mt7530_get_ethtool_stats,
3153 .get_sset_count = mt7530_get_sset_count,
3154 .set_ageing_time = mt7530_set_ageing_time,
3155 .port_enable = mt7530_port_enable,
3156 .port_disable = mt7530_port_disable,
3157 .port_change_mtu = mt7530_port_change_mtu,
3158 .port_max_mtu = mt7530_port_max_mtu,
3159 .port_stp_state_set = mt7530_stp_state_set,
3160 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags,
3161 .port_bridge_flags = mt7530_port_bridge_flags,
3162 .port_bridge_join = mt7530_port_bridge_join,
3163 .port_bridge_leave = mt7530_port_bridge_leave,
3164 .port_fdb_add = mt7530_port_fdb_add,
3165 .port_fdb_del = mt7530_port_fdb_del,
3166 .port_fdb_dump = mt7530_port_fdb_dump,
3167 .port_mdb_add = mt7530_port_mdb_add,
3168 .port_mdb_del = mt7530_port_mdb_del,
3169 .port_vlan_filtering = mt7530_port_vlan_filtering,
3170 .port_vlan_add = mt7530_port_vlan_add,
3171 .port_vlan_del = mt7530_port_vlan_del,
3172 .port_mirror_add = mt753x_port_mirror_add,
3173 .port_mirror_del = mt753x_port_mirror_del,
3174 .phylink_get_caps = mt753x_phylink_get_caps,
3175 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs,
3176 .phylink_mac_config = mt753x_phylink_mac_config,
3177 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
3178 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
3179 .get_mac_eee = mt753x_get_mac_eee,
3180 .set_mac_eee = mt753x_set_mac_eee,
3181 };
3182
3183 static const struct mt753x_info mt753x_table[] = {
3184 [ID_MT7621] = {
3185 .id = ID_MT7621,
3186 .pcs_ops = &mt7530_pcs_ops,
3187 .sw_setup = mt7530_setup,
3188 .phy_read = mt7530_phy_read,
3189 .phy_write = mt7530_phy_write,
3190 .pad_setup = mt7530_pad_clk_setup,
3191 .mac_port_get_caps = mt7530_mac_port_get_caps,
3192 .mac_port_config = mt7530_mac_config,
3193 },
3194 [ID_MT7530] = {
3195 .id = ID_MT7530,
3196 .pcs_ops = &mt7530_pcs_ops,
3197 .sw_setup = mt7530_setup,
3198 .phy_read = mt7530_phy_read,
3199 .phy_write = mt7530_phy_write,
3200 .pad_setup = mt7530_pad_clk_setup,
3201 .mac_port_get_caps = mt7530_mac_port_get_caps,
3202 .mac_port_config = mt7530_mac_config,
3203 },
3204 [ID_MT7531] = {
3205 .id = ID_MT7531,
3206 .pcs_ops = &mt7531_pcs_ops,
3207 .sw_setup = mt7531_setup,
3208 .phy_read = mt7531_ind_phy_read,
3209 .phy_write = mt7531_ind_phy_write,
3210 .pad_setup = mt7531_pad_setup,
3211 .cpu_port_config = mt7531_cpu_port_config,
3212 .mac_port_get_caps = mt7531_mac_port_get_caps,
3213 .mac_port_config = mt7531_mac_config,
3214 },
3215 };
3216
3217 static const struct of_device_id mt7530_of_match[] = {
3218 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
3219 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
3220 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
3221 { /* sentinel */ },
3222 };
3223 MODULE_DEVICE_TABLE(of, mt7530_of_match);
3224
3225 static int
mt7530_probe(struct mdio_device * mdiodev)3226 mt7530_probe(struct mdio_device *mdiodev)
3227 {
3228 struct mt7530_priv *priv;
3229 struct device_node *dn;
3230
3231 dn = mdiodev->dev.of_node;
3232
3233 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
3234 if (!priv)
3235 return -ENOMEM;
3236
3237 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
3238 if (!priv->ds)
3239 return -ENOMEM;
3240
3241 priv->ds->dev = &mdiodev->dev;
3242 priv->ds->num_ports = MT7530_NUM_PORTS;
3243
3244 /* Use medatek,mcm property to distinguish hardware type that would
3245 * casues a little bit differences on power-on sequence.
3246 */
3247 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
3248 if (priv->mcm) {
3249 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
3250
3251 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
3252 if (IS_ERR(priv->rstc)) {
3253 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3254 return PTR_ERR(priv->rstc);
3255 }
3256 }
3257
3258 /* Get the hardware identifier from the devicetree node.
3259 * We will need it for some of the clock and regulator setup.
3260 */
3261 priv->info = of_device_get_match_data(&mdiodev->dev);
3262 if (!priv->info)
3263 return -EINVAL;
3264
3265 /* Sanity check if these required device operations are filled
3266 * properly.
3267 */
3268 if (!priv->info->sw_setup || !priv->info->pad_setup ||
3269 !priv->info->phy_read || !priv->info->phy_write ||
3270 !priv->info->mac_port_get_caps ||
3271 !priv->info->mac_port_config)
3272 return -EINVAL;
3273
3274 priv->id = priv->info->id;
3275
3276 if (priv->id == ID_MT7530) {
3277 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
3278 if (IS_ERR(priv->core_pwr))
3279 return PTR_ERR(priv->core_pwr);
3280
3281 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
3282 if (IS_ERR(priv->io_pwr))
3283 return PTR_ERR(priv->io_pwr);
3284 }
3285
3286 /* Not MCM that indicates switch works as the remote standalone
3287 * integrated circuit so the GPIO pin would be used to complete
3288 * the reset, otherwise memory-mapped register accessing used
3289 * through syscon provides in the case of MCM.
3290 */
3291 if (!priv->mcm) {
3292 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
3293 GPIOD_OUT_LOW);
3294 if (IS_ERR(priv->reset)) {
3295 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3296 return PTR_ERR(priv->reset);
3297 }
3298 }
3299
3300 priv->bus = mdiodev->bus;
3301 priv->dev = &mdiodev->dev;
3302 priv->ds->priv = priv;
3303 priv->ds->ops = &mt7530_switch_ops;
3304 mutex_init(&priv->reg_mutex);
3305 dev_set_drvdata(&mdiodev->dev, priv);
3306
3307 return dsa_register_switch(priv->ds);
3308 }
3309
3310 static void
mt7530_remove(struct mdio_device * mdiodev)3311 mt7530_remove(struct mdio_device *mdiodev)
3312 {
3313 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3314 int ret = 0;
3315
3316 if (!priv)
3317 return;
3318
3319 ret = regulator_disable(priv->core_pwr);
3320 if (ret < 0)
3321 dev_err(priv->dev,
3322 "Failed to disable core power: %d\n", ret);
3323
3324 ret = regulator_disable(priv->io_pwr);
3325 if (ret < 0)
3326 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
3327 ret);
3328
3329 if (priv->irq)
3330 mt7530_free_irq(priv);
3331
3332 dsa_unregister_switch(priv->ds);
3333 mutex_destroy(&priv->reg_mutex);
3334 }
3335
mt7530_shutdown(struct mdio_device * mdiodev)3336 static void mt7530_shutdown(struct mdio_device *mdiodev)
3337 {
3338 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3339
3340 if (!priv)
3341 return;
3342
3343 dsa_switch_shutdown(priv->ds);
3344
3345 dev_set_drvdata(&mdiodev->dev, NULL);
3346 }
3347
3348 static struct mdio_driver mt7530_mdio_driver = {
3349 .probe = mt7530_probe,
3350 .remove = mt7530_remove,
3351 .shutdown = mt7530_shutdown,
3352 .mdiodrv.driver = {
3353 .name = "mt7530",
3354 .of_match_table = mt7530_of_match,
3355 },
3356 };
3357
3358 mdio_module_driver(mt7530_mdio_driver);
3359
3360 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
3361 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
3362 MODULE_LICENSE("GPL");
3363