1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
4 //
5 // Copyright (c) 2019, 2020, 2021 Pengutronix,
6 // Marc Kleine-Budde <kernel@pengutronix.de>
7 //
8 // Based on:
9 //
10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
11 //
12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
13 //
14
15 #include <asm/unaligned.h>
16 #include <linux/bitfield.h>
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/property.h>
23
24 #include "mcp251xfd.h"
25
26 #define DEVICE_NAME "mcp251xfd"
27
28 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = {
29 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG |
30 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX |
31 MCP251XFD_QUIRK_ECC,
32 .model = MCP251XFD_MODEL_MCP2517FD,
33 };
34
35 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = {
36 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
37 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
38 .model = MCP251XFD_MODEL_MCP2518FD,
39 };
40
41 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = {
42 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
43 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
44 .model = MCP251XFD_MODEL_MCP251863,
45 };
46
47 /* Autodetect model, start with CRC enabled. */
48 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = {
49 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
50 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
51 .model = MCP251XFD_MODEL_MCP251XFD,
52 };
53
54 static const struct can_bittiming_const mcp251xfd_bittiming_const = {
55 .name = DEVICE_NAME,
56 .tseg1_min = 2,
57 .tseg1_max = 256,
58 .tseg2_min = 1,
59 .tseg2_max = 128,
60 .sjw_max = 128,
61 .brp_min = 1,
62 .brp_max = 256,
63 .brp_inc = 1,
64 };
65
66 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = {
67 .name = DEVICE_NAME,
68 .tseg1_min = 1,
69 .tseg1_max = 32,
70 .tseg2_min = 1,
71 .tseg2_max = 16,
72 .sjw_max = 16,
73 .brp_min = 1,
74 .brp_max = 256,
75 .brp_inc = 1,
76 };
77
__mcp251xfd_get_model_str(enum mcp251xfd_model model)78 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)
79 {
80 switch (model) {
81 case MCP251XFD_MODEL_MCP2517FD:
82 return "MCP2517FD";
83 case MCP251XFD_MODEL_MCP2518FD:
84 return "MCP2518FD";
85 case MCP251XFD_MODEL_MCP251863:
86 return "MCP251863";
87 case MCP251XFD_MODEL_MCP251XFD:
88 return "MCP251xFD";
89 }
90
91 return "<unknown>";
92 }
93
94 static inline const char *
mcp251xfd_get_model_str(const struct mcp251xfd_priv * priv)95 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv)
96 {
97 return __mcp251xfd_get_model_str(priv->devtype_data.model);
98 }
99
mcp251xfd_get_mode_str(const u8 mode)100 static const char *mcp251xfd_get_mode_str(const u8 mode)
101 {
102 switch (mode) {
103 case MCP251XFD_REG_CON_MODE_MIXED:
104 return "Mixed (CAN FD/CAN 2.0)";
105 case MCP251XFD_REG_CON_MODE_SLEEP:
106 return "Sleep";
107 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:
108 return "Internal Loopback";
109 case MCP251XFD_REG_CON_MODE_LISTENONLY:
110 return "Listen Only";
111 case MCP251XFD_REG_CON_MODE_CONFIG:
112 return "Configuration";
113 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:
114 return "External Loopback";
115 case MCP251XFD_REG_CON_MODE_CAN2_0:
116 return "CAN 2.0";
117 case MCP251XFD_REG_CON_MODE_RESTRICTED:
118 return "Restricted Operation";
119 }
120
121 return "<unknown>";
122 }
123
124 static const char *
mcp251xfd_get_osc_str(const u32 osc,const u32 osc_reference)125 mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference)
126 {
127 switch (~osc & osc_reference &
128 (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) {
129 case MCP251XFD_REG_OSC_PLLRDY:
130 return "PLL";
131 case MCP251XFD_REG_OSC_OSCRDY:
132 return "Oscillator";
133 case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY:
134 return "Oscillator/PLL";
135 }
136
137 return "<unknown>";
138 }
139
mcp251xfd_vdd_enable(const struct mcp251xfd_priv * priv)140 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv)
141 {
142 if (!priv->reg_vdd)
143 return 0;
144
145 return regulator_enable(priv->reg_vdd);
146 }
147
mcp251xfd_vdd_disable(const struct mcp251xfd_priv * priv)148 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv)
149 {
150 if (!priv->reg_vdd)
151 return 0;
152
153 return regulator_disable(priv->reg_vdd);
154 }
155
156 static inline int
mcp251xfd_transceiver_enable(const struct mcp251xfd_priv * priv)157 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv)
158 {
159 if (!priv->reg_xceiver)
160 return 0;
161
162 return regulator_enable(priv->reg_xceiver);
163 }
164
165 static inline int
mcp251xfd_transceiver_disable(const struct mcp251xfd_priv * priv)166 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv)
167 {
168 if (!priv->reg_xceiver)
169 return 0;
170
171 return regulator_disable(priv->reg_xceiver);
172 }
173
mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv * priv)174 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv)
175 {
176 int err;
177
178 err = clk_prepare_enable(priv->clk);
179 if (err)
180 return err;
181
182 err = mcp251xfd_vdd_enable(priv);
183 if (err)
184 clk_disable_unprepare(priv->clk);
185
186 /* Wait for oscillator stabilisation time after power up */
187 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US,
188 2 * MCP251XFD_OSC_STAB_SLEEP_US);
189
190 return err;
191 }
192
mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv * priv)193 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv)
194 {
195 int err;
196
197 err = mcp251xfd_vdd_disable(priv);
198 if (err)
199 return err;
200
201 clk_disable_unprepare(priv->clk);
202
203 return 0;
204 }
205
mcp251xfd_reg_invalid(u32 reg)206 static inline bool mcp251xfd_reg_invalid(u32 reg)
207 {
208 return reg == 0x0 || reg == 0xffffffff;
209 }
210
211 static inline int
mcp251xfd_chip_get_mode(const struct mcp251xfd_priv * priv,u8 * mode)212 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode)
213 {
214 u32 val;
215 int err;
216
217 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val);
218 if (err)
219 return err;
220
221 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val);
222
223 return 0;
224 }
225
226 static int
__mcp251xfd_chip_set_mode(const struct mcp251xfd_priv * priv,const u8 mode_req,bool nowait)227 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
228 const u8 mode_req, bool nowait)
229 {
230 u32 con = 0, con_reqop, osc = 0;
231 u8 mode;
232 int err;
233
234 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req);
235 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON,
236 MCP251XFD_REG_CON_REQOP_MASK, con_reqop);
237 if (err == -EBADMSG) {
238 netdev_err(priv->ndev,
239 "Failed to set Requested Operation Mode.\n");
240
241 return -ENODEV;
242 } else if (err) {
243 return err;
244 }
245
246 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait)
247 return 0;
248
249 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con,
250 !mcp251xfd_reg_invalid(con) &&
251 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK,
252 con) == mode_req,
253 MCP251XFD_POLL_SLEEP_US,
254 MCP251XFD_POLL_TIMEOUT_US);
255 if (err != -ETIMEDOUT && err != -EBADMSG)
256 return err;
257
258 /* Ignore return value.
259 * Print below error messages, even if this fails.
260 */
261 regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
262
263 if (mcp251xfd_reg_invalid(con)) {
264 netdev_err(priv->ndev,
265 "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n",
266 con, osc);
267
268 return -ENODEV;
269 }
270
271 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con);
272 netdev_err(priv->ndev,
273 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n",
274 mcp251xfd_get_mode_str(mode_req), mode_req,
275 mcp251xfd_get_mode_str(mode), mode,
276 con, osc);
277
278 return -ETIMEDOUT;
279 }
280
281 static inline int
mcp251xfd_chip_set_mode(const struct mcp251xfd_priv * priv,const u8 mode_req)282 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
283 const u8 mode_req)
284 {
285 return __mcp251xfd_chip_set_mode(priv, mode_req, false);
286 }
287
288 static inline int __maybe_unused
mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv * priv,const u8 mode_req)289 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,
290 const u8 mode_req)
291 {
292 return __mcp251xfd_chip_set_mode(priv, mode_req, true);
293 }
294
295 static int
mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv * priv,u32 osc_reference,u32 osc_mask)296 mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv,
297 u32 osc_reference, u32 osc_mask)
298 {
299 u32 osc;
300 int err;
301
302 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc,
303 !mcp251xfd_reg_invalid(osc) &&
304 (osc & osc_mask) == osc_reference,
305 MCP251XFD_OSC_STAB_SLEEP_US,
306 MCP251XFD_OSC_STAB_TIMEOUT_US);
307 if (err != -ETIMEDOUT)
308 return err;
309
310 if (mcp251xfd_reg_invalid(osc)) {
311 netdev_err(priv->ndev,
312 "Failed to read Oscillator Configuration Register (osc=0x%08x).\n",
313 osc);
314 return -ENODEV;
315 }
316
317 netdev_err(priv->ndev,
318 "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n",
319 mcp251xfd_get_osc_str(osc, osc_reference),
320 osc, osc_reference, osc_mask);
321
322 return -ETIMEDOUT;
323 }
324
mcp251xfd_chip_wake(const struct mcp251xfd_priv * priv)325 static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)
326 {
327 u32 osc, osc_reference, osc_mask;
328 int err;
329
330 /* For normal sleep on MCP2517FD and MCP2518FD, clearing
331 * "Oscillator Disable" will wake the chip. For low power mode
332 * on MCP2518FD, asserting the chip select will wake the
333 * chip. Writing to the Oscillator register will wake it in
334 * both cases.
335 */
336 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
337 MCP251XFD_REG_OSC_CLKODIV_10);
338
339 /* We cannot check for the PLL ready bit (either set or
340 * unset), as the PLL might be enabled. This can happen if the
341 * system reboots, while the mcp251xfd stays powered.
342 */
343 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
344 osc_mask = MCP251XFD_REG_OSC_OSCRDY;
345
346 /* If the controller is in Sleep Mode the following write only
347 * removes the "Oscillator Disable" bit and powers it up. All
348 * other bits are unaffected.
349 */
350 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
351 if (err)
352 return err;
353
354 /* Sometimes the PLL is stuck enabled, the controller never
355 * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our
356 * caller takes care of retry.
357 */
358 return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
359 }
360
mcp251xfd_chip_sleep(const struct mcp251xfd_priv * priv)361 static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv)
362 {
363 if (priv->pll_enable) {
364 u32 osc;
365 int err;
366
367 /* Turn off PLL */
368 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
369 MCP251XFD_REG_OSC_CLKODIV_10);
370 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
371 if (err)
372 netdev_err(priv->ndev,
373 "Failed to disable PLL.\n");
374
375 priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow;
376 }
377
378 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
379 }
380
mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv * priv)381 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv)
382 {
383 const __be16 cmd = mcp251xfd_cmd_reset();
384 int err;
385
386 /* The Set Mode and SPI Reset command only works if the
387 * controller is not in Sleep Mode.
388 */
389 err = mcp251xfd_chip_wake(priv);
390 if (err)
391 return err;
392
393 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
394 if (err)
395 return err;
396
397 /* spi_write_then_read() works with non DMA-safe buffers */
398 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0);
399 }
400
mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv * priv)401 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)
402 {
403 u32 osc_reference, osc_mask;
404 u8 mode;
405 int err;
406
407 /* Check for reset defaults of OSC reg.
408 * This will take care of stabilization period.
409 */
410 osc_reference = MCP251XFD_REG_OSC_OSCRDY |
411 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
412 MCP251XFD_REG_OSC_CLKODIV_10);
413 osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY;
414 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
415 if (err)
416 return err;
417
418 err = mcp251xfd_chip_get_mode(priv, &mode);
419 if (err)
420 return err;
421
422 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) {
423 netdev_info(priv->ndev,
424 "Controller not in Config Mode after reset, but in %s Mode (%u).\n",
425 mcp251xfd_get_mode_str(mode), mode);
426 return -ETIMEDOUT;
427 }
428
429 return 0;
430 }
431
mcp251xfd_chip_softreset(const struct mcp251xfd_priv * priv)432 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv)
433 {
434 int err, i;
435
436 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) {
437 if (i)
438 netdev_info(priv->ndev,
439 "Retrying to reset controller.\n");
440
441 err = mcp251xfd_chip_softreset_do(priv);
442 if (err == -ETIMEDOUT)
443 continue;
444 if (err)
445 return err;
446
447 err = mcp251xfd_chip_softreset_check(priv);
448 if (err == -ETIMEDOUT)
449 continue;
450 if (err)
451 return err;
452
453 return 0;
454 }
455
456 return err;
457 }
458
mcp251xfd_chip_clock_init(const struct mcp251xfd_priv * priv)459 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv)
460 {
461 u32 osc, osc_reference, osc_mask;
462 int err;
463
464 /* Activate Low Power Mode on Oscillator Disable. This only
465 * works on the MCP2518FD. The MCP2517FD will go into normal
466 * Sleep Mode instead.
467 */
468 osc = MCP251XFD_REG_OSC_LPMEN |
469 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
470 MCP251XFD_REG_OSC_CLKODIV_10);
471 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
472 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY;
473
474 if (priv->pll_enable) {
475 osc |= MCP251XFD_REG_OSC_PLLEN;
476 osc_reference |= MCP251XFD_REG_OSC_PLLRDY;
477 }
478
479 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
480 if (err)
481 return err;
482
483 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
484 if (err)
485 return err;
486
487 priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast;
488
489 return 0;
490 }
491
mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv * priv)492 static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv)
493 {
494 /* Set Time Base Counter Prescaler to 1.
495 *
496 * This means an overflow of the 32 bit Time Base Counter
497 * register at 40 MHz every 107 seconds.
498 */
499 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON,
500 MCP251XFD_REG_TSCON_TBCEN);
501 }
502
mcp251xfd_set_bittiming(const struct mcp251xfd_priv * priv)503 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv)
504 {
505 const struct can_bittiming *bt = &priv->can.bittiming;
506 const struct can_bittiming *dbt = &priv->can.data_bittiming;
507 u32 val = 0;
508 s8 tdco;
509 int err;
510
511 /* CAN Control Register
512 *
513 * - no transmit bandwidth sharing
514 * - config mode
515 * - disable transmit queue
516 * - store in transmit FIFO event
517 * - transition to restricted operation mode on system error
518 * - ESI is transmitted recessive when ESI of message is high or
519 * CAN controller error passive
520 * - restricted retransmission attempts,
521 * use TQXCON_TXAT and FIFOCON_TXAT
522 * - wake-up filter bits T11FILTER
523 * - use CAN bus line filter for wakeup
524 * - protocol exception is treated as a form error
525 * - Do not compare data bytes
526 */
527 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK,
528 MCP251XFD_REG_CON_MODE_CONFIG) |
529 MCP251XFD_REG_CON_STEF |
530 MCP251XFD_REG_CON_ESIGM |
531 MCP251XFD_REG_CON_RTXAT |
532 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK,
533 MCP251XFD_REG_CON_WFT_T11FILTER) |
534 MCP251XFD_REG_CON_WAKFIL |
535 MCP251XFD_REG_CON_PXEDIS;
536
537 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
538 val |= MCP251XFD_REG_CON_ISOCRCEN;
539
540 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val);
541 if (err)
542 return err;
543
544 /* Nominal Bit Time */
545 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) |
546 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK,
547 bt->prop_seg + bt->phase_seg1 - 1) |
548 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK,
549 bt->phase_seg2 - 1) |
550 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1);
551
552 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val);
553 if (err)
554 return err;
555
556 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
557 return 0;
558
559 /* Data Bit Time */
560 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) |
561 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK,
562 dbt->prop_seg + dbt->phase_seg1 - 1) |
563 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK,
564 dbt->phase_seg2 - 1) |
565 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1);
566
567 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val);
568 if (err)
569 return err;
570
571 /* Transmitter Delay Compensation */
572 tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1),
573 -64, 63);
574 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK,
575 MCP251XFD_REG_TDC_TDCMOD_AUTO) |
576 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco);
577
578 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val);
579 }
580
mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv * priv)581 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv)
582 {
583 u32 val;
584
585 if (!priv->rx_int)
586 return 0;
587
588 /* Configure GPIOs:
589 * - PIN0: GPIO Input
590 * - PIN1: GPIO Input/RX Interrupt
591 *
592 * PIN1 must be Input, otherwise there is a glitch on the
593 * rx-INT line. It happens between setting the PIN as output
594 * (in the first byte of the SPI transfer) and configuring the
595 * PIN as interrupt (in the last byte of the SPI transfer).
596 */
597 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 |
598 MCP251XFD_REG_IOCON_TRIS0;
599 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
600 }
601
mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv * priv)602 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv)
603 {
604 u32 val;
605
606 if (!priv->rx_int)
607 return 0;
608
609 /* Configure GPIOs:
610 * - PIN0: GPIO Input
611 * - PIN1: GPIO Input
612 */
613 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 |
614 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0;
615 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
616 }
617
mcp251xfd_chip_ecc_init(struct mcp251xfd_priv * priv)618 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv)
619 {
620 struct mcp251xfd_ecc *ecc = &priv->ecc;
621 void *ram;
622 u32 val = 0;
623 int err;
624
625 ecc->ecc_stat = 0;
626
627 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC)
628 val = MCP251XFD_REG_ECCCON_ECCEN;
629
630 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
631 MCP251XFD_REG_ECCCON_ECCEN, val);
632 if (err)
633 return err;
634
635 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL);
636 if (!ram)
637 return -ENOMEM;
638
639 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram,
640 MCP251XFD_RAM_SIZE);
641 kfree(ram);
642
643 return err;
644 }
645
mcp251xfd_get_normal_mode(const struct mcp251xfd_priv * priv)646 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv)
647 {
648 u8 mode;
649
650 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
651 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK;
652 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
653 mode = MCP251XFD_REG_CON_MODE_LISTENONLY;
654 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
655 mode = MCP251XFD_REG_CON_MODE_MIXED;
656 else
657 mode = MCP251XFD_REG_CON_MODE_CAN2_0;
658
659 return mode;
660 }
661
662 static int
__mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv * priv,bool nowait)663 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv,
664 bool nowait)
665 {
666 u8 mode;
667
668 mode = mcp251xfd_get_normal_mode(priv);
669
670 return __mcp251xfd_chip_set_mode(priv, mode, nowait);
671 }
672
673 static inline int
mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv * priv)674 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv)
675 {
676 return __mcp251xfd_chip_set_normal_mode(priv, false);
677 }
678
679 static inline int
mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv * priv)680 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv)
681 {
682 return __mcp251xfd_chip_set_normal_mode(priv, true);
683 }
684
mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv * priv)685 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv)
686 {
687 u32 val;
688 int err;
689
690 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE;
691 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val);
692 if (err)
693 return err;
694
695 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
696 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val);
697 if (err)
698 return err;
699
700 val = MCP251XFD_REG_INT_CERRIE |
701 MCP251XFD_REG_INT_SERRIE |
702 MCP251XFD_REG_INT_RXOVIE |
703 MCP251XFD_REG_INT_TXATIE |
704 MCP251XFD_REG_INT_SPICRCIE |
705 MCP251XFD_REG_INT_ECCIE |
706 MCP251XFD_REG_INT_TEFIE |
707 MCP251XFD_REG_INT_MODIE |
708 MCP251XFD_REG_INT_RXIE;
709
710 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
711 val |= MCP251XFD_REG_INT_IVMIE;
712
713 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val);
714 }
715
mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv * priv)716 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv)
717 {
718 int err;
719 u32 mask;
720
721 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0);
722 if (err)
723 return err;
724
725 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
726 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
727 mask, 0x0);
728 if (err)
729 return err;
730
731 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0);
732 }
733
mcp251xfd_chip_stop(struct mcp251xfd_priv * priv,const enum can_state state)734 static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv,
735 const enum can_state state)
736 {
737 priv->can.state = state;
738
739 mcp251xfd_chip_interrupts_disable(priv);
740 mcp251xfd_chip_rx_int_disable(priv);
741 mcp251xfd_chip_sleep(priv);
742 }
743
mcp251xfd_chip_start(struct mcp251xfd_priv * priv)744 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv)
745 {
746 int err;
747
748 err = mcp251xfd_chip_softreset(priv);
749 if (err)
750 goto out_chip_stop;
751
752 err = mcp251xfd_chip_clock_init(priv);
753 if (err)
754 goto out_chip_stop;
755
756 err = mcp251xfd_chip_timestamp_init(priv);
757 if (err)
758 goto out_chip_stop;
759
760 err = mcp251xfd_set_bittiming(priv);
761 if (err)
762 goto out_chip_stop;
763
764 err = mcp251xfd_chip_rx_int_enable(priv);
765 if (err)
766 goto out_chip_stop;
767
768 err = mcp251xfd_chip_ecc_init(priv);
769 if (err)
770 goto out_chip_stop;
771
772 err = mcp251xfd_ring_init(priv);
773 if (err)
774 goto out_chip_stop;
775
776 err = mcp251xfd_chip_fifo_init(priv);
777 if (err)
778 goto out_chip_stop;
779
780 priv->can.state = CAN_STATE_ERROR_ACTIVE;
781
782 err = mcp251xfd_chip_set_normal_mode(priv);
783 if (err)
784 goto out_chip_stop;
785
786 return 0;
787
788 out_chip_stop:
789 mcp251xfd_dump(priv);
790 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
791
792 return err;
793 }
794
mcp251xfd_set_mode(struct net_device * ndev,enum can_mode mode)795 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode)
796 {
797 struct mcp251xfd_priv *priv = netdev_priv(ndev);
798 int err;
799
800 switch (mode) {
801 case CAN_MODE_START:
802 err = mcp251xfd_chip_start(priv);
803 if (err)
804 return err;
805
806 err = mcp251xfd_chip_interrupts_enable(priv);
807 if (err) {
808 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
809 return err;
810 }
811
812 netif_wake_queue(ndev);
813 break;
814
815 default:
816 return -EOPNOTSUPP;
817 }
818
819 return 0;
820 }
821
__mcp251xfd_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)822 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev,
823 struct can_berr_counter *bec)
824 {
825 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
826 u32 trec;
827 int err;
828
829 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
830 if (err)
831 return err;
832
833 if (trec & MCP251XFD_REG_TREC_TXBO)
834 bec->txerr = 256;
835 else
836 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec);
837 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec);
838
839 return 0;
840 }
841
mcp251xfd_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)842 static int mcp251xfd_get_berr_counter(const struct net_device *ndev,
843 struct can_berr_counter *bec)
844 {
845 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
846
847 /* Avoid waking up the controller if the interface is down */
848 if (!(ndev->flags & IFF_UP))
849 return 0;
850
851 /* The controller is powered down during Bus Off, use saved
852 * bec values.
853 */
854 if (priv->can.state == CAN_STATE_BUS_OFF) {
855 *bec = priv->bec;
856 return 0;
857 }
858
859 return __mcp251xfd_get_berr_counter(ndev, bec);
860 }
861
862 static struct sk_buff *
mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv * priv,struct can_frame ** cf,u32 * timestamp)863 mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv,
864 struct can_frame **cf, u32 *timestamp)
865 {
866 struct sk_buff *skb;
867 int err;
868
869 err = mcp251xfd_get_timestamp(priv, timestamp);
870 if (err)
871 return NULL;
872
873 skb = alloc_can_err_skb(priv->ndev, cf);
874 if (skb)
875 mcp251xfd_skb_set_timestamp(priv, skb, *timestamp);
876
877 return skb;
878 }
879
mcp251xfd_handle_rxovif(struct mcp251xfd_priv * priv)880 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv)
881 {
882 struct net_device_stats *stats = &priv->ndev->stats;
883 struct mcp251xfd_rx_ring *ring;
884 struct sk_buff *skb;
885 struct can_frame *cf;
886 u32 timestamp, rxovif;
887 int err, i;
888
889 stats->rx_over_errors++;
890 stats->rx_errors++;
891
892 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif);
893 if (err)
894 return err;
895
896 mcp251xfd_for_each_rx_ring(priv, ring, i) {
897 if (!(rxovif & BIT(ring->fifo_nr)))
898 continue;
899
900 /* If SERRIF is active, there was a RX MAB overflow. */
901 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) {
902 if (net_ratelimit())
903 netdev_dbg(priv->ndev,
904 "RX-%d: MAB overflow detected.\n",
905 ring->nr);
906 } else {
907 if (net_ratelimit())
908 netdev_dbg(priv->ndev,
909 "RX-%d: FIFO overflow.\n",
910 ring->nr);
911 }
912
913 err = regmap_update_bits(priv->map_reg,
914 MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
915 MCP251XFD_REG_FIFOSTA_RXOVIF,
916 0x0);
917 if (err)
918 return err;
919 }
920
921 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp);
922 if (!skb)
923 return 0;
924
925 cf->can_id |= CAN_ERR_CRTL;
926 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
927
928 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
929 if (err)
930 stats->rx_fifo_errors++;
931
932 return 0;
933 }
934
mcp251xfd_handle_txatif(struct mcp251xfd_priv * priv)935 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv)
936 {
937 netdev_info(priv->ndev, "%s\n", __func__);
938
939 return 0;
940 }
941
mcp251xfd_handle_ivmif(struct mcp251xfd_priv * priv)942 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv)
943 {
944 struct net_device_stats *stats = &priv->ndev->stats;
945 u32 bdiag1, timestamp;
946 struct sk_buff *skb;
947 struct can_frame *cf = NULL;
948 int err;
949
950 err = mcp251xfd_get_timestamp(priv, ×tamp);
951 if (err)
952 return err;
953
954 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1);
955 if (err)
956 return err;
957
958 /* Write 0s to clear error bits, don't write 1s to non active
959 * bits, as they will be set.
960 */
961 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0);
962 if (err)
963 return err;
964
965 priv->can.can_stats.bus_error++;
966
967 skb = alloc_can_err_skb(priv->ndev, &cf);
968 if (cf)
969 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
970
971 /* Controller misconfiguration */
972 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM))
973 netdev_err(priv->ndev,
974 "recv'd DLC is larger than PLSIZE of FIFO element.");
975
976 /* RX errors */
977 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR |
978 MCP251XFD_REG_BDIAG1_NCRCERR)) {
979 netdev_dbg(priv->ndev, "CRC error\n");
980
981 stats->rx_errors++;
982 if (cf)
983 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
984 }
985 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR |
986 MCP251XFD_REG_BDIAG1_NSTUFERR)) {
987 netdev_dbg(priv->ndev, "Stuff error\n");
988
989 stats->rx_errors++;
990 if (cf)
991 cf->data[2] |= CAN_ERR_PROT_STUFF;
992 }
993 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR |
994 MCP251XFD_REG_BDIAG1_NFORMERR)) {
995 netdev_dbg(priv->ndev, "Format error\n");
996
997 stats->rx_errors++;
998 if (cf)
999 cf->data[2] |= CAN_ERR_PROT_FORM;
1000 }
1001
1002 /* TX errors */
1003 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) {
1004 netdev_dbg(priv->ndev, "NACK error\n");
1005
1006 stats->tx_errors++;
1007 if (cf) {
1008 cf->can_id |= CAN_ERR_ACK;
1009 cf->data[2] |= CAN_ERR_PROT_TX;
1010 }
1011 }
1012 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR |
1013 MCP251XFD_REG_BDIAG1_NBIT1ERR)) {
1014 netdev_dbg(priv->ndev, "Bit1 error\n");
1015
1016 stats->tx_errors++;
1017 if (cf)
1018 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1;
1019 }
1020 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR |
1021 MCP251XFD_REG_BDIAG1_NBIT0ERR)) {
1022 netdev_dbg(priv->ndev, "Bit0 error\n");
1023
1024 stats->tx_errors++;
1025 if (cf)
1026 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0;
1027 }
1028
1029 if (!cf)
1030 return 0;
1031
1032 mcp251xfd_skb_set_timestamp(priv, skb, timestamp);
1033 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
1034 if (err)
1035 stats->rx_fifo_errors++;
1036
1037 return 0;
1038 }
1039
mcp251xfd_handle_cerrif(struct mcp251xfd_priv * priv)1040 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv)
1041 {
1042 struct net_device_stats *stats = &priv->ndev->stats;
1043 struct sk_buff *skb;
1044 struct can_frame *cf = NULL;
1045 enum can_state new_state, rx_state, tx_state;
1046 u32 trec, timestamp;
1047 int err;
1048
1049 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
1050 if (err)
1051 return err;
1052
1053 if (trec & MCP251XFD_REG_TREC_TXBO)
1054 tx_state = CAN_STATE_BUS_OFF;
1055 else if (trec & MCP251XFD_REG_TREC_TXBP)
1056 tx_state = CAN_STATE_ERROR_PASSIVE;
1057 else if (trec & MCP251XFD_REG_TREC_TXWARN)
1058 tx_state = CAN_STATE_ERROR_WARNING;
1059 else
1060 tx_state = CAN_STATE_ERROR_ACTIVE;
1061
1062 if (trec & MCP251XFD_REG_TREC_RXBP)
1063 rx_state = CAN_STATE_ERROR_PASSIVE;
1064 else if (trec & MCP251XFD_REG_TREC_RXWARN)
1065 rx_state = CAN_STATE_ERROR_WARNING;
1066 else
1067 rx_state = CAN_STATE_ERROR_ACTIVE;
1068
1069 new_state = max(tx_state, rx_state);
1070 if (new_state == priv->can.state)
1071 return 0;
1072
1073 /* The skb allocation might fail, but can_change_state()
1074 * handles cf == NULL.
1075 */
1076 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp);
1077 can_change_state(priv->ndev, cf, tx_state, rx_state);
1078
1079 if (new_state == CAN_STATE_BUS_OFF) {
1080 /* As we're going to switch off the chip now, let's
1081 * save the error counters and return them to
1082 * userspace, if do_get_berr_counter() is called while
1083 * the chip is in Bus Off.
1084 */
1085 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec);
1086 if (err)
1087 return err;
1088
1089 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF);
1090 can_bus_off(priv->ndev);
1091 }
1092
1093 if (!skb)
1094 return 0;
1095
1096 if (new_state != CAN_STATE_BUS_OFF) {
1097 struct can_berr_counter bec;
1098
1099 err = mcp251xfd_get_berr_counter(priv->ndev, &bec);
1100 if (err)
1101 return err;
1102 cf->can_id |= CAN_ERR_CNT;
1103 cf->data[6] = bec.txerr;
1104 cf->data[7] = bec.rxerr;
1105 }
1106
1107 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
1108 if (err)
1109 stats->rx_fifo_errors++;
1110
1111 return 0;
1112 }
1113
1114 static int
mcp251xfd_handle_modif(const struct mcp251xfd_priv * priv,bool * set_normal_mode)1115 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode)
1116 {
1117 const u8 mode_reference = mcp251xfd_get_normal_mode(priv);
1118 u8 mode;
1119 int err;
1120
1121 err = mcp251xfd_chip_get_mode(priv, &mode);
1122 if (err)
1123 return err;
1124
1125 if (mode == mode_reference) {
1126 netdev_dbg(priv->ndev,
1127 "Controller changed into %s Mode (%u).\n",
1128 mcp251xfd_get_mode_str(mode), mode);
1129 return 0;
1130 }
1131
1132 /* According to MCP2517FD errata DS80000792B 1., during a TX
1133 * MAB underflow, the controller will transition to Restricted
1134 * Operation Mode or Listen Only Mode (depending on SERR2LOM).
1135 *
1136 * However this is not always the case. If SERR2LOM is
1137 * configured for Restricted Operation Mode (SERR2LOM not set)
1138 * the MCP2517FD will sometimes transition to Listen Only Mode
1139 * first. When polling this bit we see that it will transition
1140 * to Restricted Operation Mode shortly after.
1141 */
1142 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) &&
1143 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED ||
1144 mode == MCP251XFD_REG_CON_MODE_LISTENONLY))
1145 netdev_dbg(priv->ndev,
1146 "Controller changed into %s Mode (%u).\n",
1147 mcp251xfd_get_mode_str(mode), mode);
1148 else
1149 netdev_err(priv->ndev,
1150 "Controller changed into %s Mode (%u).\n",
1151 mcp251xfd_get_mode_str(mode), mode);
1152
1153 /* After the application requests Normal mode, the controller
1154 * will automatically attempt to retransmit the message that
1155 * caused the TX MAB underflow.
1156 *
1157 * However, if there is an ECC error in the TX-RAM, we first
1158 * have to reload the tx-object before requesting Normal
1159 * mode. This is done later in mcp251xfd_handle_eccif().
1160 */
1161 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) {
1162 *set_normal_mode = true;
1163 return 0;
1164 }
1165
1166 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1167 }
1168
mcp251xfd_handle_serrif(struct mcp251xfd_priv * priv)1169 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)
1170 {
1171 struct mcp251xfd_ecc *ecc = &priv->ecc;
1172 struct net_device_stats *stats = &priv->ndev->stats;
1173 bool handled = false;
1174
1175 /* TX MAB underflow
1176 *
1177 * According to MCP2517FD Errata DS80000792B 1. a TX MAB
1178 * underflow is indicated by SERRIF and MODIF.
1179 *
1180 * In addition to the effects mentioned in the Errata, there
1181 * are Bus Errors due to the aborted CAN frame, so a IVMIF
1182 * will be seen as well.
1183 *
1184 * Sometimes there is an ECC error in the TX-RAM, which leads
1185 * to a TX MAB underflow.
1186 *
1187 * However, probably due to a race condition, there is no
1188 * associated MODIF pending.
1189 *
1190 * Further, there are situations, where the SERRIF is caused
1191 * by an ECC error in the TX-RAM, but not even the ECCIF is
1192 * set. This only seems to happen _after_ the first occurrence
1193 * of a ECCIF (which is tracked in ecc->cnt).
1194 *
1195 * Treat all as a known system errors..
1196 */
1197 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&
1198 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||
1199 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1200 ecc->cnt) {
1201 const char *msg;
1202
1203 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1204 ecc->cnt)
1205 msg = "TX MAB underflow due to ECC error detected.";
1206 else
1207 msg = "TX MAB underflow detected.";
1208
1209 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)
1210 netdev_dbg(priv->ndev, "%s\n", msg);
1211 else
1212 netdev_info(priv->ndev, "%s\n", msg);
1213
1214 stats->tx_aborted_errors++;
1215 stats->tx_errors++;
1216 handled = true;
1217 }
1218
1219 /* RX MAB overflow
1220 *
1221 * According to MCP2517FD Errata DS80000792B 1. a RX MAB
1222 * overflow is indicated by SERRIF.
1223 *
1224 * In addition to the effects mentioned in the Errata, (most
1225 * of the times) a RXOVIF is raised, if the FIFO that is being
1226 * received into has the RXOVIE activated (and we have enabled
1227 * RXOVIE on all FIFOs).
1228 *
1229 * Sometimes there is no RXOVIF just a RXIF is pending.
1230 *
1231 * Treat all as a known system errors..
1232 */
1233 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||
1234 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {
1235 stats->rx_dropped++;
1236 handled = true;
1237 }
1238
1239 if (!handled)
1240 netdev_err(priv->ndev,
1241 "Unhandled System Error Interrupt (intf=0x%08x)!\n",
1242 priv->regs_status.intf);
1243
1244 return 0;
1245 }
1246
1247 static int
mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv * priv,u8 nr)1248 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr)
1249 {
1250 struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1251 struct mcp251xfd_ecc *ecc = &priv->ecc;
1252 struct mcp251xfd_tx_obj *tx_obj;
1253 u8 chip_tx_tail, tx_tail, offset;
1254 u16 addr;
1255 int err;
1256
1257 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat);
1258
1259 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);
1260 if (err)
1261 return err;
1262
1263 tx_tail = mcp251xfd_get_tx_tail(tx_ring);
1264 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1);
1265
1266 /* Bail out if one of the following is met:
1267 * - tx_tail information is inconsistent
1268 * - for mcp2517fd: offset not 0
1269 * - for mcp2518fd: offset not 0 or 1
1270 */
1271 if (chip_tx_tail != tx_tail ||
1272 !(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) ||
1273 mcp251xfd_is_251863(priv))))) {
1274 netdev_err(priv->ndev,
1275 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n",
1276 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail,
1277 offset);
1278 return -EINVAL;
1279 }
1280
1281 netdev_info(priv->ndev,
1282 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n",
1283 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ?
1284 "Single" : "Double",
1285 addr, nr, tx_ring->tail, tx_tail, offset);
1286
1287 /* reload tx_obj into controller RAM ... */
1288 tx_obj = &tx_ring->obj[nr];
1289 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1);
1290 if (err)
1291 return err;
1292
1293 /* ... and trigger retransmit */
1294 return mcp251xfd_chip_set_normal_mode(priv);
1295 }
1296
1297 static int
mcp251xfd_handle_eccif(struct mcp251xfd_priv * priv,bool set_normal_mode)1298 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode)
1299 {
1300 struct mcp251xfd_ecc *ecc = &priv->ecc;
1301 const char *msg;
1302 bool in_tx_ram;
1303 u32 ecc_stat;
1304 u16 addr;
1305 u8 nr;
1306 int err;
1307
1308 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat);
1309 if (err)
1310 return err;
1311
1312 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT,
1313 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat);
1314 if (err)
1315 return err;
1316
1317 /* Check if ECC error occurred in TX-RAM */
1318 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat);
1319 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr);
1320 if (!err)
1321 in_tx_ram = true;
1322 else if (err == -ENOENT)
1323 in_tx_ram = false;
1324 else
1325 return err;
1326
1327 /* Errata Reference:
1328 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2.
1329 *
1330 * ECC single error correction does not work in all cases:
1331 *
1332 * Fix/Work Around:
1333 * Enable single error correction and double error detection
1334 * interrupts by setting SECIE and DEDIE. Handle SECIF as a
1335 * detection interrupt and do not rely on the error
1336 * correction. Instead, handle both interrupts as a
1337 * notification that the RAM word at ERRADDR was corrupted.
1338 */
1339 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF)
1340 msg = "Single ECC Error detected at address";
1341 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF)
1342 msg = "Double ECC Error detected at address";
1343 else
1344 return -EINVAL;
1345
1346 if (!in_tx_ram) {
1347 ecc->ecc_stat = 0;
1348
1349 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr);
1350 } else {
1351 /* Re-occurring error? */
1352 if (ecc->ecc_stat == ecc_stat) {
1353 ecc->cnt++;
1354 } else {
1355 ecc->ecc_stat = ecc_stat;
1356 ecc->cnt = 1;
1357 }
1358
1359 netdev_info(priv->ndev,
1360 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n",
1361 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : "");
1362
1363 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX)
1364 return mcp251xfd_handle_eccif_recover(priv, nr);
1365 }
1366
1367 if (set_normal_mode)
1368 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1369
1370 return 0;
1371 }
1372
mcp251xfd_handle_spicrcif(struct mcp251xfd_priv * priv)1373 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv)
1374 {
1375 int err;
1376 u32 crc;
1377
1378 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc);
1379 if (err)
1380 return err;
1381
1382 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC,
1383 MCP251XFD_REG_CRC_IF_MASK,
1384 ~crc);
1385 if (err)
1386 return err;
1387
1388 if (crc & MCP251XFD_REG_CRC_FERRIF)
1389 netdev_notice(priv->ndev, "CRC write command format error.\n");
1390 else if (crc & MCP251XFD_REG_CRC_CRCERRIF)
1391 netdev_notice(priv->ndev,
1392 "CRC write error detected. CRC=0x%04lx.\n",
1393 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc));
1394
1395 return 0;
1396 }
1397
mcp251xfd_read_regs_status(struct mcp251xfd_priv * priv)1398 static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv)
1399 {
1400 const int val_bytes = regmap_get_val_bytes(priv->map_reg);
1401 size_t len;
1402
1403 if (priv->rx_ring_num == 1)
1404 len = sizeof(priv->regs_status.intf);
1405 else
1406 len = sizeof(priv->regs_status);
1407
1408 return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT,
1409 &priv->regs_status, len / val_bytes);
1410 }
1411
1412 #define mcp251xfd_handle(priv, irq, ...) \
1413 ({ \
1414 struct mcp251xfd_priv *_priv = (priv); \
1415 int err; \
1416 \
1417 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \
1418 if (err) \
1419 netdev_err(_priv->ndev, \
1420 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \
1421 __stringify(irq), err); \
1422 err; \
1423 })
1424
mcp251xfd_irq(int irq,void * dev_id)1425 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id)
1426 {
1427 struct mcp251xfd_priv *priv = dev_id;
1428 irqreturn_t handled = IRQ_NONE;
1429 int err;
1430
1431 if (priv->rx_int)
1432 do {
1433 int rx_pending;
1434
1435 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1436 if (!rx_pending)
1437 break;
1438
1439 /* Assume 1st RX-FIFO pending, if other FIFOs
1440 * are pending the main IRQ handler will take
1441 * care.
1442 */
1443 priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr);
1444 err = mcp251xfd_handle(priv, rxif);
1445 if (err)
1446 goto out_fail;
1447
1448 handled = IRQ_HANDLED;
1449
1450 /* We don't know which RX-FIFO is pending, but only
1451 * handle the 1st RX-FIFO. Leave loop here if we have
1452 * more than 1 RX-FIFO to avoid starvation.
1453 */
1454 } while (priv->rx_ring_num == 1);
1455
1456 do {
1457 u32 intf_pending, intf_pending_clearable;
1458 bool set_normal_mode = false;
1459
1460 err = mcp251xfd_read_regs_status(priv);
1461 if (err)
1462 goto out_fail;
1463
1464 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK,
1465 priv->regs_status.intf) &
1466 FIELD_GET(MCP251XFD_REG_INT_IE_MASK,
1467 priv->regs_status.intf);
1468
1469 if (!(intf_pending)) {
1470 can_rx_offload_threaded_irq_finish(&priv->offload);
1471 return handled;
1472 }
1473
1474 /* Some interrupts must be ACKed in the
1475 * MCP251XFD_REG_INT register.
1476 * - First ACK then handle, to avoid lost-IRQ race
1477 * condition on fast re-occurring interrupts.
1478 * - Write "0" to clear active IRQs, "1" to all other,
1479 * to avoid r/m/w race condition on the
1480 * MCP251XFD_REG_INT register.
1481 */
1482 intf_pending_clearable = intf_pending &
1483 MCP251XFD_REG_INT_IF_CLEARABLE_MASK;
1484 if (intf_pending_clearable) {
1485 err = regmap_update_bits(priv->map_reg,
1486 MCP251XFD_REG_INT,
1487 MCP251XFD_REG_INT_IF_MASK,
1488 ~intf_pending_clearable);
1489 if (err)
1490 goto out_fail;
1491 }
1492
1493 if (intf_pending & MCP251XFD_REG_INT_MODIF) {
1494 err = mcp251xfd_handle(priv, modif, &set_normal_mode);
1495 if (err)
1496 goto out_fail;
1497 }
1498
1499 if (intf_pending & MCP251XFD_REG_INT_RXIF) {
1500 err = mcp251xfd_handle(priv, rxif);
1501 if (err)
1502 goto out_fail;
1503 }
1504
1505 if (intf_pending & MCP251XFD_REG_INT_TEFIF) {
1506 err = mcp251xfd_handle(priv, tefif);
1507 if (err)
1508 goto out_fail;
1509 }
1510
1511 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) {
1512 err = mcp251xfd_handle(priv, rxovif);
1513 if (err)
1514 goto out_fail;
1515 }
1516
1517 if (intf_pending & MCP251XFD_REG_INT_TXATIF) {
1518 err = mcp251xfd_handle(priv, txatif);
1519 if (err)
1520 goto out_fail;
1521 }
1522
1523 if (intf_pending & MCP251XFD_REG_INT_IVMIF) {
1524 err = mcp251xfd_handle(priv, ivmif);
1525 if (err)
1526 goto out_fail;
1527 }
1528
1529 if (intf_pending & MCP251XFD_REG_INT_SERRIF) {
1530 err = mcp251xfd_handle(priv, serrif);
1531 if (err)
1532 goto out_fail;
1533 }
1534
1535 if (intf_pending & MCP251XFD_REG_INT_ECCIF) {
1536 err = mcp251xfd_handle(priv, eccif, set_normal_mode);
1537 if (err)
1538 goto out_fail;
1539 }
1540
1541 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) {
1542 err = mcp251xfd_handle(priv, spicrcif);
1543 if (err)
1544 goto out_fail;
1545 }
1546
1547 /* On the MCP2527FD and MCP2518FD, we don't get a
1548 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX
1549 * ERROR_ACTIVE.
1550 */
1551 if (intf_pending & MCP251XFD_REG_INT_CERRIF ||
1552 priv->can.state > CAN_STATE_ERROR_ACTIVE) {
1553 err = mcp251xfd_handle(priv, cerrif);
1554 if (err)
1555 goto out_fail;
1556
1557 /* In Bus Off we completely shut down the
1558 * controller. Every subsequent register read
1559 * will read bogus data, and if
1560 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC
1561 * check will fail, too. So leave IRQ handler
1562 * directly.
1563 */
1564 if (priv->can.state == CAN_STATE_BUS_OFF) {
1565 can_rx_offload_threaded_irq_finish(&priv->offload);
1566 return IRQ_HANDLED;
1567 }
1568 }
1569
1570 handled = IRQ_HANDLED;
1571 } while (1);
1572
1573 out_fail:
1574 can_rx_offload_threaded_irq_finish(&priv->offload);
1575
1576 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n",
1577 err, priv->regs_status.intf);
1578 mcp251xfd_dump(priv);
1579 mcp251xfd_chip_interrupts_disable(priv);
1580 mcp251xfd_timestamp_stop(priv);
1581
1582 return handled;
1583 }
1584
mcp251xfd_open(struct net_device * ndev)1585 static int mcp251xfd_open(struct net_device *ndev)
1586 {
1587 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1588 const struct spi_device *spi = priv->spi;
1589 int err;
1590
1591 err = open_candev(ndev);
1592 if (err)
1593 return err;
1594
1595 err = pm_runtime_resume_and_get(ndev->dev.parent);
1596 if (err)
1597 goto out_close_candev;
1598
1599 err = mcp251xfd_ring_alloc(priv);
1600 if (err)
1601 goto out_pm_runtime_put;
1602
1603 err = mcp251xfd_transceiver_enable(priv);
1604 if (err)
1605 goto out_mcp251xfd_ring_free;
1606
1607 err = mcp251xfd_chip_start(priv);
1608 if (err)
1609 goto out_transceiver_disable;
1610
1611 mcp251xfd_timestamp_init(priv);
1612 clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1613 can_rx_offload_enable(&priv->offload);
1614
1615 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq,
1616 IRQF_SHARED | IRQF_ONESHOT,
1617 dev_name(&spi->dev), priv);
1618 if (err)
1619 goto out_can_rx_offload_disable;
1620
1621 err = mcp251xfd_chip_interrupts_enable(priv);
1622 if (err)
1623 goto out_free_irq;
1624
1625 netif_start_queue(ndev);
1626
1627 return 0;
1628
1629 out_free_irq:
1630 free_irq(spi->irq, priv);
1631 out_can_rx_offload_disable:
1632 can_rx_offload_disable(&priv->offload);
1633 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1634 mcp251xfd_timestamp_stop(priv);
1635 out_transceiver_disable:
1636 mcp251xfd_transceiver_disable(priv);
1637 out_mcp251xfd_ring_free:
1638 mcp251xfd_ring_free(priv);
1639 out_pm_runtime_put:
1640 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1641 pm_runtime_put(ndev->dev.parent);
1642 out_close_candev:
1643 close_candev(ndev);
1644
1645 return err;
1646 }
1647
mcp251xfd_stop(struct net_device * ndev)1648 static int mcp251xfd_stop(struct net_device *ndev)
1649 {
1650 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1651
1652 netif_stop_queue(ndev);
1653 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1654 hrtimer_cancel(&priv->rx_irq_timer);
1655 hrtimer_cancel(&priv->tx_irq_timer);
1656 mcp251xfd_chip_interrupts_disable(priv);
1657 free_irq(ndev->irq, priv);
1658 can_rx_offload_disable(&priv->offload);
1659 mcp251xfd_timestamp_stop(priv);
1660 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1661 mcp251xfd_transceiver_disable(priv);
1662 mcp251xfd_ring_free(priv);
1663 close_candev(ndev);
1664
1665 pm_runtime_put(ndev->dev.parent);
1666
1667 return 0;
1668 }
1669
1670 static const struct net_device_ops mcp251xfd_netdev_ops = {
1671 .ndo_open = mcp251xfd_open,
1672 .ndo_stop = mcp251xfd_stop,
1673 .ndo_start_xmit = mcp251xfd_start_xmit,
1674 .ndo_eth_ioctl = can_eth_ioctl_hwts,
1675 .ndo_change_mtu = can_change_mtu,
1676 };
1677
1678 static void
mcp251xfd_register_quirks(struct mcp251xfd_priv * priv)1679 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv)
1680 {
1681 const struct spi_device *spi = priv->spi;
1682 const struct spi_controller *ctlr = spi->controller;
1683
1684 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
1685 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX;
1686 }
1687
mcp251xfd_register_chip_detect(struct mcp251xfd_priv * priv)1688 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)
1689 {
1690 const struct net_device *ndev = priv->ndev;
1691 const struct mcp251xfd_devtype_data *devtype_data;
1692 u32 osc;
1693 int err;
1694
1695 /* The OSC_LPMEN is only supported on MCP2518FD and MCP251863,
1696 * so use it to autodetect the model.
1697 */
1698 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC,
1699 MCP251XFD_REG_OSC_LPMEN,
1700 MCP251XFD_REG_OSC_LPMEN);
1701 if (err)
1702 return err;
1703
1704 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
1705 if (err)
1706 return err;
1707
1708 if (osc & MCP251XFD_REG_OSC_LPMEN) {
1709 /* We cannot distinguish between MCP2518FD and
1710 * MCP251863. If firmware specifies MCP251863, keep
1711 * it, otherwise set to MCP2518FD.
1712 */
1713 if (mcp251xfd_is_251863(priv))
1714 devtype_data = &mcp251xfd_devtype_data_mcp251863;
1715 else
1716 devtype_data = &mcp251xfd_devtype_data_mcp2518fd;
1717 } else {
1718 devtype_data = &mcp251xfd_devtype_data_mcp2517fd;
1719 }
1720
1721 if (!mcp251xfd_is_251XFD(priv) &&
1722 priv->devtype_data.model != devtype_data->model) {
1723 netdev_info(ndev,
1724 "Detected %s, but firmware specifies a %s. Fixing up.\n",
1725 __mcp251xfd_get_model_str(devtype_data->model),
1726 mcp251xfd_get_model_str(priv));
1727 }
1728 priv->devtype_data = *devtype_data;
1729
1730 /* We need to preserve the Half Duplex Quirk. */
1731 mcp251xfd_register_quirks(priv);
1732
1733 /* Re-init regmap with quirks of detected model. */
1734 return mcp251xfd_regmap_init(priv);
1735 }
1736
mcp251xfd_register_check_rx_int(struct mcp251xfd_priv * priv)1737 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv)
1738 {
1739 int err, rx_pending;
1740
1741 if (!priv->rx_int)
1742 return 0;
1743
1744 err = mcp251xfd_chip_rx_int_enable(priv);
1745 if (err)
1746 return err;
1747
1748 /* Check if RX_INT is properly working. The RX_INT should not
1749 * be active after a softreset.
1750 */
1751 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1752
1753 err = mcp251xfd_chip_rx_int_disable(priv);
1754 if (err)
1755 return err;
1756
1757 if (!rx_pending)
1758 return 0;
1759
1760 netdev_info(priv->ndev,
1761 "RX_INT active after softreset, disabling RX_INT support.\n");
1762 devm_gpiod_put(&priv->spi->dev, priv->rx_int);
1763 priv->rx_int = NULL;
1764
1765 return 0;
1766 }
1767
1768 static int
mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv * priv,u32 * dev_id,u32 * effective_speed_hz_slow,u32 * effective_speed_hz_fast)1769 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,
1770 u32 *effective_speed_hz_slow,
1771 u32 *effective_speed_hz_fast)
1772 {
1773 struct mcp251xfd_map_buf_nocrc *buf_rx;
1774 struct mcp251xfd_map_buf_nocrc *buf_tx;
1775 struct spi_transfer xfer[2] = { };
1776 int err;
1777
1778 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL);
1779 if (!buf_rx)
1780 return -ENOMEM;
1781
1782 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL);
1783 if (!buf_tx) {
1784 err = -ENOMEM;
1785 goto out_kfree_buf_rx;
1786 }
1787
1788 xfer[0].tx_buf = buf_tx;
1789 xfer[0].len = sizeof(buf_tx->cmd);
1790 xfer[0].speed_hz = priv->spi_max_speed_hz_slow;
1791 xfer[1].rx_buf = buf_rx->data;
1792 xfer[1].len = sizeof(*dev_id);
1793 xfer[1].speed_hz = priv->spi_max_speed_hz_fast;
1794
1795 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID);
1796
1797 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer));
1798 if (err)
1799 goto out_kfree_buf_tx;
1800
1801 *dev_id = get_unaligned_le32(buf_rx->data);
1802 *effective_speed_hz_slow = xfer[0].effective_speed_hz;
1803 *effective_speed_hz_fast = xfer[1].effective_speed_hz;
1804
1805 out_kfree_buf_tx:
1806 kfree(buf_tx);
1807 out_kfree_buf_rx:
1808 kfree(buf_rx);
1809
1810 return err;
1811 }
1812
1813 #define MCP251XFD_QUIRK_ACTIVE(quirk) \
1814 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-')
1815
1816 static int
mcp251xfd_register_done(const struct mcp251xfd_priv * priv)1817 mcp251xfd_register_done(const struct mcp251xfd_priv *priv)
1818 {
1819 u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast;
1820 unsigned long clk_rate;
1821 int err;
1822
1823 err = mcp251xfd_register_get_dev_id(priv, &dev_id,
1824 &effective_speed_hz_slow,
1825 &effective_speed_hz_fast);
1826 if (err)
1827 return err;
1828
1829 clk_rate = clk_get_rate(priv->clk);
1830
1831 netdev_info(priv->ndev,
1832 "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n",
1833 mcp251xfd_get_model_str(priv),
1834 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id),
1835 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id),
1836 priv->rx_int ? '+' : '-',
1837 priv->pll_enable ? '+' : '-',
1838 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN),
1839 MCP251XFD_QUIRK_ACTIVE(CRC_REG),
1840 MCP251XFD_QUIRK_ACTIVE(CRC_RX),
1841 MCP251XFD_QUIRK_ACTIVE(CRC_TX),
1842 MCP251XFD_QUIRK_ACTIVE(ECC),
1843 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX),
1844 clk_rate / 1000000,
1845 clk_rate % 1000000 / 1000 / 10,
1846 priv->can.clock.freq / 1000000,
1847 priv->can.clock.freq % 1000000 / 1000 / 10,
1848 priv->spi_max_speed_hz_orig / 1000000,
1849 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10,
1850 priv->spi_max_speed_hz_slow / 1000000,
1851 priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10,
1852 effective_speed_hz_slow / 1000000,
1853 effective_speed_hz_slow % 1000000 / 1000 / 10,
1854 priv->spi_max_speed_hz_fast / 1000000,
1855 priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10,
1856 effective_speed_hz_fast / 1000000,
1857 effective_speed_hz_fast % 1000000 / 1000 / 10);
1858
1859 return 0;
1860 }
1861
mcp251xfd_register(struct mcp251xfd_priv * priv)1862 static int mcp251xfd_register(struct mcp251xfd_priv *priv)
1863 {
1864 struct net_device *ndev = priv->ndev;
1865 int err;
1866
1867 err = mcp251xfd_clks_and_vdd_enable(priv);
1868 if (err)
1869 return err;
1870
1871 pm_runtime_get_noresume(ndev->dev.parent);
1872 err = pm_runtime_set_active(ndev->dev.parent);
1873 if (err)
1874 goto out_runtime_put_noidle;
1875 pm_runtime_enable(ndev->dev.parent);
1876
1877 mcp251xfd_register_quirks(priv);
1878
1879 err = mcp251xfd_chip_softreset(priv);
1880 if (err == -ENODEV)
1881 goto out_runtime_disable;
1882 if (err)
1883 goto out_chip_sleep;
1884
1885 err = mcp251xfd_chip_clock_init(priv);
1886 if (err == -ENODEV)
1887 goto out_runtime_disable;
1888 if (err)
1889 goto out_chip_sleep;
1890
1891 err = mcp251xfd_register_chip_detect(priv);
1892 if (err)
1893 goto out_chip_sleep;
1894
1895 err = mcp251xfd_register_check_rx_int(priv);
1896 if (err)
1897 goto out_chip_sleep;
1898
1899 mcp251xfd_ethtool_init(priv);
1900
1901 err = register_candev(ndev);
1902 if (err)
1903 goto out_chip_sleep;
1904
1905 err = mcp251xfd_register_done(priv);
1906 if (err)
1907 goto out_unregister_candev;
1908
1909 /* Put controller into sleep mode and let pm_runtime_put()
1910 * disable the clocks and vdd. If CONFIG_PM is not enabled,
1911 * the clocks and vdd will stay powered.
1912 */
1913 err = mcp251xfd_chip_sleep(priv);
1914 if (err)
1915 goto out_unregister_candev;
1916
1917 pm_runtime_put(ndev->dev.parent);
1918
1919 return 0;
1920
1921 out_unregister_candev:
1922 unregister_candev(ndev);
1923 out_chip_sleep:
1924 mcp251xfd_chip_sleep(priv);
1925 out_runtime_disable:
1926 pm_runtime_disable(ndev->dev.parent);
1927 out_runtime_put_noidle:
1928 pm_runtime_put_noidle(ndev->dev.parent);
1929 mcp251xfd_clks_and_vdd_disable(priv);
1930
1931 return err;
1932 }
1933
mcp251xfd_unregister(struct mcp251xfd_priv * priv)1934 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv)
1935 {
1936 struct net_device *ndev = priv->ndev;
1937
1938 unregister_candev(ndev);
1939
1940 if (pm_runtime_enabled(ndev->dev.parent))
1941 pm_runtime_disable(ndev->dev.parent);
1942 else
1943 mcp251xfd_clks_and_vdd_disable(priv);
1944 }
1945
1946 static const struct of_device_id mcp251xfd_of_match[] = {
1947 {
1948 .compatible = "microchip,mcp2517fd",
1949 .data = &mcp251xfd_devtype_data_mcp2517fd,
1950 }, {
1951 .compatible = "microchip,mcp2518fd",
1952 .data = &mcp251xfd_devtype_data_mcp2518fd,
1953 }, {
1954 .compatible = "microchip,mcp251863",
1955 .data = &mcp251xfd_devtype_data_mcp251863,
1956 }, {
1957 .compatible = "microchip,mcp251xfd",
1958 .data = &mcp251xfd_devtype_data_mcp251xfd,
1959 }, {
1960 /* sentinel */
1961 },
1962 };
1963 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match);
1964
1965 static const struct spi_device_id mcp251xfd_id_table[] = {
1966 {
1967 .name = "mcp2517fd",
1968 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd,
1969 }, {
1970 .name = "mcp2518fd",
1971 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd,
1972 }, {
1973 .name = "mcp251863",
1974 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863,
1975 }, {
1976 .name = "mcp251xfd",
1977 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd,
1978 }, {
1979 /* sentinel */
1980 },
1981 };
1982 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table);
1983
mcp251xfd_probe(struct spi_device * spi)1984 static int mcp251xfd_probe(struct spi_device *spi)
1985 {
1986 const void *match;
1987 struct net_device *ndev;
1988 struct mcp251xfd_priv *priv;
1989 struct gpio_desc *rx_int;
1990 struct regulator *reg_vdd, *reg_xceiver;
1991 struct clk *clk;
1992 bool pll_enable = false;
1993 u32 freq = 0;
1994 int err;
1995
1996 if (!spi->irq)
1997 return dev_err_probe(&spi->dev, -ENXIO,
1998 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n");
1999
2000 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int",
2001 GPIOD_IN);
2002 if (IS_ERR(rx_int))
2003 return dev_err_probe(&spi->dev, PTR_ERR(rx_int),
2004 "Failed to get RX-INT!\n");
2005
2006 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd");
2007 if (PTR_ERR(reg_vdd) == -ENODEV)
2008 reg_vdd = NULL;
2009 else if (IS_ERR(reg_vdd))
2010 return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd),
2011 "Failed to get VDD regulator!\n");
2012
2013 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
2014 if (PTR_ERR(reg_xceiver) == -ENODEV)
2015 reg_xceiver = NULL;
2016 else if (IS_ERR(reg_xceiver))
2017 return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver),
2018 "Failed to get Transceiver regulator!\n");
2019
2020 clk = devm_clk_get_optional(&spi->dev, NULL);
2021 if (IS_ERR(clk))
2022 return dev_err_probe(&spi->dev, PTR_ERR(clk),
2023 "Failed to get Oscillator (clock)!\n");
2024 if (clk) {
2025 freq = clk_get_rate(clk);
2026 } else {
2027 err = device_property_read_u32(&spi->dev, "clock-frequency",
2028 &freq);
2029 if (err)
2030 return dev_err_probe(&spi->dev, err,
2031 "Failed to get clock-frequency!\n");
2032 }
2033
2034 /* Sanity check */
2035 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN ||
2036 freq > MCP251XFD_SYSCLOCK_HZ_MAX) {
2037 dev_err(&spi->dev,
2038 "Oscillator frequency (%u Hz) is too low or high.\n",
2039 freq);
2040 return -ERANGE;
2041 }
2042
2043 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER)
2044 pll_enable = true;
2045
2046 ndev = alloc_candev(sizeof(struct mcp251xfd_priv),
2047 MCP251XFD_TX_OBJ_NUM_MAX);
2048 if (!ndev)
2049 return -ENOMEM;
2050
2051 SET_NETDEV_DEV(ndev, &spi->dev);
2052
2053 ndev->netdev_ops = &mcp251xfd_netdev_ops;
2054 ndev->irq = spi->irq;
2055 ndev->flags |= IFF_ECHO;
2056
2057 priv = netdev_priv(ndev);
2058 spi_set_drvdata(spi, priv);
2059 priv->can.clock.freq = freq;
2060 if (pll_enable)
2061 priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER;
2062 priv->can.do_set_mode = mcp251xfd_set_mode;
2063 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter;
2064 priv->can.bittiming_const = &mcp251xfd_bittiming_const;
2065 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const;
2066 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2067 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING |
2068 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO |
2069 CAN_CTRLMODE_CC_LEN8_DLC;
2070 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
2071 priv->ndev = ndev;
2072 priv->spi = spi;
2073 priv->rx_int = rx_int;
2074 priv->clk = clk;
2075 priv->pll_enable = pll_enable;
2076 priv->reg_vdd = reg_vdd;
2077 priv->reg_xceiver = reg_xceiver;
2078
2079 match = device_get_match_data(&spi->dev);
2080 if (match)
2081 priv->devtype_data = *(struct mcp251xfd_devtype_data *)match;
2082 else
2083 priv->devtype_data = *(struct mcp251xfd_devtype_data *)
2084 spi_get_device_id(spi)->driver_data;
2085
2086 /* Errata Reference:
2087 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789C 4.
2088 *
2089 * The SPI can write corrupted data to the RAM at fast SPI
2090 * speeds:
2091 *
2092 * Simultaneous activity on the CAN bus while writing data to
2093 * RAM via the SPI interface, with high SCK frequency, can
2094 * lead to corrupted data being written to RAM.
2095 *
2096 * Fix/Work Around:
2097 * Ensure that FSCK is less than or equal to 0.85 *
2098 * (FSYSCLK/2).
2099 *
2100 * Known good combinations are:
2101 *
2102 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config
2103 *
2104 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2105 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2106 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2107 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2108 * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default
2109 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
2110 *
2111 */
2112 priv->spi_max_speed_hz_orig = spi->max_speed_hz;
2113 priv->spi_max_speed_hz_slow = min(spi->max_speed_hz,
2114 freq / 2 / 1000 * 850);
2115 if (priv->pll_enable)
2116 priv->spi_max_speed_hz_fast = min(spi->max_speed_hz,
2117 freq *
2118 MCP251XFD_OSC_PLL_MULTIPLIER /
2119 2 / 1000 * 850);
2120 else
2121 priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow;
2122 spi->max_speed_hz = priv->spi_max_speed_hz_slow;
2123 spi->bits_per_word = 8;
2124 spi->rt = true;
2125 err = spi_setup(spi);
2126 if (err)
2127 goto out_free_candev;
2128
2129 err = mcp251xfd_regmap_init(priv);
2130 if (err)
2131 goto out_free_candev;
2132
2133 err = can_rx_offload_add_manual(ndev, &priv->offload,
2134 MCP251XFD_NAPI_WEIGHT);
2135 if (err)
2136 goto out_free_candev;
2137
2138 err = mcp251xfd_register(priv);
2139 if (err) {
2140 dev_err_probe(&spi->dev, err, "Failed to detect %s.\n",
2141 mcp251xfd_get_model_str(priv));
2142 goto out_can_rx_offload_del;
2143 }
2144
2145 return 0;
2146
2147 out_can_rx_offload_del:
2148 can_rx_offload_del(&priv->offload);
2149 out_free_candev:
2150 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2151
2152 free_candev(ndev);
2153
2154 return err;
2155 }
2156
mcp251xfd_remove(struct spi_device * spi)2157 static void mcp251xfd_remove(struct spi_device *spi)
2158 {
2159 struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
2160 struct net_device *ndev = priv->ndev;
2161
2162 can_rx_offload_del(&priv->offload);
2163 mcp251xfd_unregister(priv);
2164 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2165 free_candev(ndev);
2166 }
2167
mcp251xfd_runtime_suspend(struct device * device)2168 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device)
2169 {
2170 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2171
2172 return mcp251xfd_clks_and_vdd_disable(priv);
2173 }
2174
mcp251xfd_runtime_resume(struct device * device)2175 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device)
2176 {
2177 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2178
2179 return mcp251xfd_clks_and_vdd_enable(priv);
2180 }
2181
2182 static const struct dev_pm_ops mcp251xfd_pm_ops = {
2183 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend,
2184 mcp251xfd_runtime_resume, NULL)
2185 };
2186
2187 static struct spi_driver mcp251xfd_driver = {
2188 .driver = {
2189 .name = DEVICE_NAME,
2190 .pm = &mcp251xfd_pm_ops,
2191 .of_match_table = mcp251xfd_of_match,
2192 },
2193 .probe = mcp251xfd_probe,
2194 .remove = mcp251xfd_remove,
2195 .id_table = mcp251xfd_id_table,
2196 };
2197 module_spi_driver(mcp251xfd_driver);
2198
2199 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
2200 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver");
2201 MODULE_LICENSE("GPL v2");
2202