1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Samsung S5K4ECGX 1/4" 5Mp CMOS Image Sensor SoC
4 * with an Embedded Image Signal Processor.
5 *
6 * Copyright (C) 2012, Linaro, Sangwook Lee <sangwook.lee@linaro.org>
7 * Copyright (C) 2012, Insignal Co,. Ltd, Homin Lee <suapapa@insignal.co.kr>
8 *
9 * Based on s5k6aa and noon010pc30 driver
10 * Copyright (C) 2011, Samsung Electronics Co., Ltd.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/crc32.h>
15 #include <linux/ctype.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/gpio.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <asm/unaligned.h>
24
25 #include <media/media-entity.h>
26 #include <media/i2c/s5k4ecgx.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
31
32 static int debug;
33 module_param(debug, int, 0644);
34
35 #define S5K4ECGX_DRIVER_NAME "s5k4ecgx"
36 #define S5K4ECGX_FIRMWARE "s5k4ecgx.bin"
37
38 /* Firmware revision information */
39 #define REG_FW_REVISION 0x700001a6
40 #define REG_FW_VERSION 0x700001a4
41 #define S5K4ECGX_REVISION_1_1 0x11
42 #define S5K4ECGX_FW_VERSION 0x4ec0
43
44 /* General purpose parameters */
45 #define REG_USER_BRIGHTNESS 0x7000022c
46 #define REG_USER_CONTRAST 0x7000022e
47 #define REG_USER_SATURATION 0x70000230
48
49 #define REG_G_ENABLE_PREV 0x7000023e
50 #define REG_G_ENABLE_PREV_CHG 0x70000240
51 #define REG_G_NEW_CFG_SYNC 0x7000024a
52 #define REG_G_PREV_IN_WIDTH 0x70000250
53 #define REG_G_PREV_IN_HEIGHT 0x70000252
54 #define REG_G_PREV_IN_XOFFS 0x70000254
55 #define REG_G_PREV_IN_YOFFS 0x70000256
56 #define REG_G_CAP_IN_WIDTH 0x70000258
57 #define REG_G_CAP_IN_HEIGHT 0x7000025a
58 #define REG_G_CAP_IN_XOFFS 0x7000025c
59 #define REG_G_CAP_IN_YOFFS 0x7000025e
60 #define REG_G_INPUTS_CHANGE_REQ 0x70000262
61 #define REG_G_ACTIVE_PREV_CFG 0x70000266
62 #define REG_G_PREV_CFG_CHG 0x70000268
63 #define REG_G_PREV_OPEN_AFTER_CH 0x7000026a
64
65 /* Preview context register sets. n = 0...4. */
66 #define PREG(n, x) ((n) * 0x30 + (x))
67 #define REG_P_OUT_WIDTH(n) PREG(n, 0x700002a6)
68 #define REG_P_OUT_HEIGHT(n) PREG(n, 0x700002a8)
69 #define REG_P_FMT(n) PREG(n, 0x700002aa)
70 #define REG_P_PVI_MASK(n) PREG(n, 0x700002b4)
71 #define REG_P_FR_TIME_TYPE(n) PREG(n, 0x700002be)
72 #define FR_TIME_DYNAMIC 0
73 #define FR_TIME_FIXED 1
74 #define FR_TIME_FIXED_ACCURATE 2
75 #define REG_P_FR_TIME_Q_TYPE(n) PREG(n, 0x700002c0)
76 #define FR_TIME_Q_DYNAMIC 0
77 #define FR_TIME_Q_BEST_FRRATE 1
78 #define FR_TIME_Q_BEST_QUALITY 2
79
80 /* Frame period in 0.1 ms units */
81 #define REG_P_MAX_FR_TIME(n) PREG(n, 0x700002c2)
82 #define REG_P_MIN_FR_TIME(n) PREG(n, 0x700002c4)
83 #define US_TO_FR_TIME(__t) ((__t) / 100)
84 #define REG_P_PREV_MIRROR(n) PREG(n, 0x700002d0)
85 #define REG_P_CAP_MIRROR(n) PREG(n, 0x700002d2)
86
87 #define REG_G_PREVZOOM_IN_WIDTH 0x70000494
88 #define REG_G_PREVZOOM_IN_HEIGHT 0x70000496
89 #define REG_G_PREVZOOM_IN_XOFFS 0x70000498
90 #define REG_G_PREVZOOM_IN_YOFFS 0x7000049a
91 #define REG_G_CAPZOOM_IN_WIDTH 0x7000049c
92 #define REG_G_CAPZOOM_IN_HEIGHT 0x7000049e
93 #define REG_G_CAPZOOM_IN_XOFFS 0x700004a0
94 #define REG_G_CAPZOOM_IN_YOFFS 0x700004a2
95
96 /* n = 0...4 */
97 #define REG_USER_SHARPNESS(n) (0x70000a28 + (n) * 0xb6)
98
99 /* Reduce sharpness range for user space API */
100 #define SHARPNESS_DIV 8208
101 #define TOK_TERM 0xffffffff
102
103 /*
104 * FIXME: This is copied from s5k6aa, because of no information
105 * in the S5K4ECGX datasheet.
106 * H/W register Interface (0xd0000000 - 0xd0000fff)
107 */
108 #define AHB_MSB_ADDR_PTR 0xfcfc
109 #define GEN_REG_OFFSH 0xd000
110 #define REG_CMDWR_ADDRH 0x0028
111 #define REG_CMDWR_ADDRL 0x002a
112 #define REG_CMDRD_ADDRH 0x002c
113 #define REG_CMDRD_ADDRL 0x002e
114 #define REG_CMDBUF0_ADDR 0x0f12
115
116 struct s5k4ecgx_frmsize {
117 struct v4l2_frmsize_discrete size;
118 /* Fixed sensor matrix crop rectangle */
119 struct v4l2_rect input_window;
120 };
121
122 struct regval_list {
123 u32 addr;
124 u16 val;
125 };
126
127 /*
128 * TODO: currently only preview is supported and snapshot (capture)
129 * is not implemented yet
130 */
131 static const struct s5k4ecgx_frmsize s5k4ecgx_prev_sizes[] = {
132 {
133 .size = { 176, 144 },
134 .input_window = { 0x00, 0x00, 0x928, 0x780 },
135 }, {
136 .size = { 352, 288 },
137 .input_window = { 0x00, 0x00, 0x928, 0x780 },
138 }, {
139 .size = { 640, 480 },
140 .input_window = { 0x00, 0x00, 0xa00, 0x780 },
141 }, {
142 .size = { 720, 480 },
143 .input_window = { 0x00, 0x00, 0xa00, 0x6a8 },
144 }
145 };
146
147 #define S5K4ECGX_NUM_PREV ARRAY_SIZE(s5k4ecgx_prev_sizes)
148
149 struct s5k4ecgx_pixfmt {
150 u32 code;
151 u32 colorspace;
152 /* REG_TC_PCFG_Format register value */
153 u16 reg_p_format;
154 };
155
156 /* By default value, output from sensor will be YUV422 0-255 */
157 static const struct s5k4ecgx_pixfmt s5k4ecgx_formats[] = {
158 { MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG, 5 },
159 };
160
161 static const char * const s5k4ecgx_supply_names[] = {
162 /*
163 * Usually 2.8V is used for analog power (vdda)
164 * and digital IO (vddio, vdddcore)
165 */
166 "vdda",
167 "vddio",
168 "vddcore",
169 "vddreg", /* The internal s5k4ecgx regulator's supply (1.8V) */
170 };
171
172 #define S5K4ECGX_NUM_SUPPLIES ARRAY_SIZE(s5k4ecgx_supply_names)
173
174 enum s5k4ecgx_gpio_id {
175 STBY,
176 RSET,
177 GPIO_NUM,
178 };
179
180 struct s5k4ecgx {
181 struct v4l2_subdev sd;
182 struct media_pad pad;
183 struct v4l2_ctrl_handler handler;
184
185 struct s5k4ecgx_platform_data *pdata;
186 const struct s5k4ecgx_pixfmt *curr_pixfmt;
187 const struct s5k4ecgx_frmsize *curr_frmsize;
188 struct mutex lock;
189 u8 streaming;
190 u8 set_params;
191
192 struct regulator_bulk_data supplies[S5K4ECGX_NUM_SUPPLIES];
193 struct s5k4ecgx_gpio gpio[GPIO_NUM];
194 };
195
to_s5k4ecgx(struct v4l2_subdev * sd)196 static inline struct s5k4ecgx *to_s5k4ecgx(struct v4l2_subdev *sd)
197 {
198 return container_of(sd, struct s5k4ecgx, sd);
199 }
200
s5k4ecgx_i2c_read(struct i2c_client * client,u16 addr,u16 * val)201 static int s5k4ecgx_i2c_read(struct i2c_client *client, u16 addr, u16 *val)
202 {
203 u8 wbuf[2] = { addr >> 8, addr & 0xff };
204 struct i2c_msg msg[2];
205 u8 rbuf[2];
206 int ret;
207
208 msg[0].addr = client->addr;
209 msg[0].flags = 0;
210 msg[0].len = 2;
211 msg[0].buf = wbuf;
212
213 msg[1].addr = client->addr;
214 msg[1].flags = I2C_M_RD;
215 msg[1].len = 2;
216 msg[1].buf = rbuf;
217
218 ret = i2c_transfer(client->adapter, msg, 2);
219 *val = be16_to_cpu(*((__be16 *)rbuf));
220
221 v4l2_dbg(4, debug, client, "i2c_read: 0x%04X : 0x%04x\n", addr, *val);
222
223 return ret == 2 ? 0 : ret;
224 }
225
s5k4ecgx_i2c_write(struct i2c_client * client,u16 addr,u16 val)226 static int s5k4ecgx_i2c_write(struct i2c_client *client, u16 addr, u16 val)
227 {
228 u8 buf[4] = { addr >> 8, addr & 0xff, val >> 8, val & 0xff };
229
230 int ret = i2c_master_send(client, buf, 4);
231 v4l2_dbg(4, debug, client, "i2c_write: 0x%04x : 0x%04x\n", addr, val);
232
233 return ret == 4 ? 0 : ret;
234 }
235
s5k4ecgx_write(struct i2c_client * client,u32 addr,u16 val)236 static int s5k4ecgx_write(struct i2c_client *client, u32 addr, u16 val)
237 {
238 u16 high = addr >> 16, low = addr & 0xffff;
239 int ret;
240
241 v4l2_dbg(3, debug, client, "write: 0x%08x : 0x%04x\n", addr, val);
242
243 ret = s5k4ecgx_i2c_write(client, REG_CMDWR_ADDRH, high);
244 if (!ret)
245 ret = s5k4ecgx_i2c_write(client, REG_CMDWR_ADDRL, low);
246 if (!ret)
247 ret = s5k4ecgx_i2c_write(client, REG_CMDBUF0_ADDR, val);
248
249 return ret;
250 }
251
s5k4ecgx_read(struct i2c_client * client,u32 addr,u16 * val)252 static int s5k4ecgx_read(struct i2c_client *client, u32 addr, u16 *val)
253 {
254 u16 high = addr >> 16, low = addr & 0xffff;
255 int ret;
256
257 ret = s5k4ecgx_i2c_write(client, REG_CMDRD_ADDRH, high);
258 if (!ret)
259 ret = s5k4ecgx_i2c_write(client, REG_CMDRD_ADDRL, low);
260 if (!ret)
261 ret = s5k4ecgx_i2c_read(client, REG_CMDBUF0_ADDR, val);
262
263 return ret;
264 }
265
s5k4ecgx_read_fw_ver(struct v4l2_subdev * sd)266 static int s5k4ecgx_read_fw_ver(struct v4l2_subdev *sd)
267 {
268 struct i2c_client *client = v4l2_get_subdevdata(sd);
269 u16 hw_rev, fw_ver = 0;
270 int ret;
271
272 ret = s5k4ecgx_read(client, REG_FW_VERSION, &fw_ver);
273 if (ret < 0 || fw_ver != S5K4ECGX_FW_VERSION) {
274 v4l2_err(sd, "FW version check failed!\n");
275 return -ENODEV;
276 }
277
278 ret = s5k4ecgx_read(client, REG_FW_REVISION, &hw_rev);
279 if (ret < 0)
280 return ret;
281
282 v4l2_info(sd, "chip found FW ver: 0x%x, HW rev: 0x%x\n",
283 fw_ver, hw_rev);
284 return 0;
285 }
286
s5k4ecgx_set_ahb_address(struct v4l2_subdev * sd)287 static int s5k4ecgx_set_ahb_address(struct v4l2_subdev *sd)
288 {
289 struct i2c_client *client = v4l2_get_subdevdata(sd);
290 int ret;
291
292 /* Set APB peripherals start address */
293 ret = s5k4ecgx_i2c_write(client, AHB_MSB_ADDR_PTR, GEN_REG_OFFSH);
294 if (ret < 0)
295 return ret;
296 /*
297 * FIXME: This is copied from s5k6aa, because of no information
298 * in s5k4ecgx's datasheet.
299 * sw_reset is activated to put device into idle status
300 */
301 ret = s5k4ecgx_i2c_write(client, 0x0010, 0x0001);
302 if (ret < 0)
303 return ret;
304
305 ret = s5k4ecgx_i2c_write(client, 0x1030, 0x0000);
306 if (ret < 0)
307 return ret;
308 /* Halt ARM CPU */
309 return s5k4ecgx_i2c_write(client, 0x0014, 0x0001);
310 }
311
312 #define FW_CRC_SIZE 4
313 /* Register address, value are 4, 2 bytes */
314 #define FW_RECORD_SIZE 6
315 /*
316 * The firmware has following format:
317 * < total number of records (4 bytes + 2 bytes padding) N >,
318 * < record 0 >, ..., < record N - 1 >, < CRC32-CCITT (4-bytes) >,
319 * where "record" is a 4-byte register address followed by 2-byte
320 * register value (little endian).
321 * The firmware generator can be found in following git repository:
322 * git://git.linaro.org/people/sangwook/fimc-v4l2-app.git
323 */
s5k4ecgx_load_firmware(struct v4l2_subdev * sd)324 static int s5k4ecgx_load_firmware(struct v4l2_subdev *sd)
325 {
326 struct i2c_client *client = v4l2_get_subdevdata(sd);
327 const struct firmware *fw;
328 const u8 *ptr;
329 int err, i, regs_num;
330 u32 addr, crc, crc_file, addr_inc = 0;
331 u16 val;
332
333 err = request_firmware(&fw, S5K4ECGX_FIRMWARE, sd->v4l2_dev->dev);
334 if (err) {
335 v4l2_err(sd, "Failed to read firmware %s\n", S5K4ECGX_FIRMWARE);
336 return err;
337 }
338 regs_num = get_unaligned_le32(fw->data);
339
340 v4l2_dbg(3, debug, sd, "FW: %s size %zu register sets %d\n",
341 S5K4ECGX_FIRMWARE, fw->size, regs_num);
342
343 regs_num++; /* Add header */
344 if (fw->size != regs_num * FW_RECORD_SIZE + FW_CRC_SIZE) {
345 err = -EINVAL;
346 goto fw_out;
347 }
348 crc_file = get_unaligned_le32(fw->data + regs_num * FW_RECORD_SIZE);
349 crc = crc32_le(~0, fw->data, regs_num * FW_RECORD_SIZE);
350 if (crc != crc_file) {
351 v4l2_err(sd, "FW: invalid crc (%#x:%#x)\n", crc, crc_file);
352 err = -EINVAL;
353 goto fw_out;
354 }
355 ptr = fw->data + FW_RECORD_SIZE;
356 for (i = 1; i < regs_num; i++) {
357 addr = get_unaligned_le32(ptr);
358 ptr += sizeof(u32);
359 val = get_unaligned_le16(ptr);
360 ptr += sizeof(u16);
361 if (addr - addr_inc != 2)
362 err = s5k4ecgx_write(client, addr, val);
363 else
364 err = s5k4ecgx_i2c_write(client, REG_CMDBUF0_ADDR, val);
365 if (err)
366 break;
367 addr_inc = addr;
368 }
369 fw_out:
370 release_firmware(fw);
371 return err;
372 }
373
374 /* Set preview and capture input window */
s5k4ecgx_set_input_window(struct i2c_client * c,const struct v4l2_rect * r)375 static int s5k4ecgx_set_input_window(struct i2c_client *c,
376 const struct v4l2_rect *r)
377 {
378 int ret;
379
380 ret = s5k4ecgx_write(c, REG_G_PREV_IN_WIDTH, r->width);
381 if (!ret)
382 ret = s5k4ecgx_write(c, REG_G_PREV_IN_HEIGHT, r->height);
383 if (!ret)
384 ret = s5k4ecgx_write(c, REG_G_PREV_IN_XOFFS, r->left);
385 if (!ret)
386 ret = s5k4ecgx_write(c, REG_G_PREV_IN_YOFFS, r->top);
387 if (!ret)
388 ret = s5k4ecgx_write(c, REG_G_CAP_IN_WIDTH, r->width);
389 if (!ret)
390 ret = s5k4ecgx_write(c, REG_G_CAP_IN_HEIGHT, r->height);
391 if (!ret)
392 ret = s5k4ecgx_write(c, REG_G_CAP_IN_XOFFS, r->left);
393 if (!ret)
394 ret = s5k4ecgx_write(c, REG_G_CAP_IN_YOFFS, r->top);
395
396 return ret;
397 }
398
399 /* Set preview and capture zoom input window */
s5k4ecgx_set_zoom_window(struct i2c_client * c,const struct v4l2_rect * r)400 static int s5k4ecgx_set_zoom_window(struct i2c_client *c,
401 const struct v4l2_rect *r)
402 {
403 int ret;
404
405 ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_WIDTH, r->width);
406 if (!ret)
407 ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_HEIGHT, r->height);
408 if (!ret)
409 ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_XOFFS, r->left);
410 if (!ret)
411 ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_YOFFS, r->top);
412 if (!ret)
413 ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_WIDTH, r->width);
414 if (!ret)
415 ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_HEIGHT, r->height);
416 if (!ret)
417 ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_XOFFS, r->left);
418 if (!ret)
419 ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_YOFFS, r->top);
420
421 return ret;
422 }
423
s5k4ecgx_set_output_framefmt(struct s5k4ecgx * priv)424 static int s5k4ecgx_set_output_framefmt(struct s5k4ecgx *priv)
425 {
426 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
427 int ret;
428
429 ret = s5k4ecgx_write(client, REG_P_OUT_WIDTH(0),
430 priv->curr_frmsize->size.width);
431 if (!ret)
432 ret = s5k4ecgx_write(client, REG_P_OUT_HEIGHT(0),
433 priv->curr_frmsize->size.height);
434 if (!ret)
435 ret = s5k4ecgx_write(client, REG_P_FMT(0),
436 priv->curr_pixfmt->reg_p_format);
437 return ret;
438 }
439
s5k4ecgx_init_sensor(struct v4l2_subdev * sd)440 static int s5k4ecgx_init_sensor(struct v4l2_subdev *sd)
441 {
442 int ret;
443
444 ret = s5k4ecgx_set_ahb_address(sd);
445
446 /* The delay is from manufacturer's settings */
447 msleep(100);
448
449 if (!ret)
450 ret = s5k4ecgx_load_firmware(sd);
451 if (ret)
452 v4l2_err(sd, "Failed to write initial settings\n");
453
454 return ret;
455 }
456
s5k4ecgx_gpio_set_value(struct s5k4ecgx * priv,int id,u32 val)457 static int s5k4ecgx_gpio_set_value(struct s5k4ecgx *priv, int id, u32 val)
458 {
459 if (!gpio_is_valid(priv->gpio[id].gpio))
460 return 0;
461 gpio_set_value(priv->gpio[id].gpio, val);
462
463 return 1;
464 }
465
__s5k4ecgx_power_on(struct s5k4ecgx * priv)466 static int __s5k4ecgx_power_on(struct s5k4ecgx *priv)
467 {
468 int ret;
469
470 ret = regulator_bulk_enable(S5K4ECGX_NUM_SUPPLIES, priv->supplies);
471 if (ret)
472 return ret;
473 usleep_range(30, 50);
474
475 /* The polarity of STBY is controlled by TSP */
476 if (s5k4ecgx_gpio_set_value(priv, STBY, priv->gpio[STBY].level))
477 usleep_range(30, 50);
478
479 if (s5k4ecgx_gpio_set_value(priv, RSET, priv->gpio[RSET].level))
480 usleep_range(30, 50);
481
482 return 0;
483 }
484
__s5k4ecgx_power_off(struct s5k4ecgx * priv)485 static int __s5k4ecgx_power_off(struct s5k4ecgx *priv)
486 {
487 if (s5k4ecgx_gpio_set_value(priv, RSET, !priv->gpio[RSET].level))
488 usleep_range(30, 50);
489
490 if (s5k4ecgx_gpio_set_value(priv, STBY, !priv->gpio[STBY].level))
491 usleep_range(30, 50);
492
493 priv->streaming = 0;
494
495 return regulator_bulk_disable(S5K4ECGX_NUM_SUPPLIES, priv->supplies);
496 }
497
498 /* Find nearest matching image pixel size. */
s5k4ecgx_try_frame_size(struct v4l2_mbus_framefmt * mf,const struct s5k4ecgx_frmsize ** size)499 static int s5k4ecgx_try_frame_size(struct v4l2_mbus_framefmt *mf,
500 const struct s5k4ecgx_frmsize **size)
501 {
502 unsigned int min_err = ~0;
503 int i = ARRAY_SIZE(s5k4ecgx_prev_sizes);
504 const struct s5k4ecgx_frmsize *fsize = &s5k4ecgx_prev_sizes[0],
505 *match = NULL;
506
507 while (i--) {
508 int err = abs(fsize->size.width - mf->width)
509 + abs(fsize->size.height - mf->height);
510 if (err < min_err) {
511 min_err = err;
512 match = fsize;
513 }
514 fsize++;
515 }
516 if (match) {
517 mf->width = match->size.width;
518 mf->height = match->size.height;
519 if (size)
520 *size = match;
521 return 0;
522 }
523
524 return -EINVAL;
525 }
526
s5k4ecgx_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)527 static int s5k4ecgx_enum_mbus_code(struct v4l2_subdev *sd,
528 struct v4l2_subdev_state *sd_state,
529 struct v4l2_subdev_mbus_code_enum *code)
530 {
531 if (code->index >= ARRAY_SIZE(s5k4ecgx_formats))
532 return -EINVAL;
533 code->code = s5k4ecgx_formats[code->index].code;
534
535 return 0;
536 }
537
s5k4ecgx_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)538 static int s5k4ecgx_get_fmt(struct v4l2_subdev *sd,
539 struct v4l2_subdev_state *sd_state,
540 struct v4l2_subdev_format *fmt)
541 {
542 struct s5k4ecgx *priv = to_s5k4ecgx(sd);
543 struct v4l2_mbus_framefmt *mf;
544
545 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
546 if (sd_state) {
547 mf = v4l2_subdev_get_try_format(sd, sd_state, 0);
548 fmt->format = *mf;
549 }
550 return 0;
551 }
552
553 mf = &fmt->format;
554
555 mutex_lock(&priv->lock);
556 mf->width = priv->curr_frmsize->size.width;
557 mf->height = priv->curr_frmsize->size.height;
558 mf->code = priv->curr_pixfmt->code;
559 mf->colorspace = priv->curr_pixfmt->colorspace;
560 mf->field = V4L2_FIELD_NONE;
561 mutex_unlock(&priv->lock);
562
563 return 0;
564 }
565
s5k4ecgx_try_fmt(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * mf)566 static const struct s5k4ecgx_pixfmt *s5k4ecgx_try_fmt(struct v4l2_subdev *sd,
567 struct v4l2_mbus_framefmt *mf)
568 {
569 int i = ARRAY_SIZE(s5k4ecgx_formats);
570
571 while (--i)
572 if (mf->code == s5k4ecgx_formats[i].code)
573 break;
574 mf->code = s5k4ecgx_formats[i].code;
575
576 return &s5k4ecgx_formats[i];
577 }
578
s5k4ecgx_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)579 static int s5k4ecgx_set_fmt(struct v4l2_subdev *sd,
580 struct v4l2_subdev_state *sd_state,
581 struct v4l2_subdev_format *fmt)
582 {
583 struct s5k4ecgx *priv = to_s5k4ecgx(sd);
584 const struct s5k4ecgx_frmsize *fsize = NULL;
585 const struct s5k4ecgx_pixfmt *pf;
586 struct v4l2_mbus_framefmt *mf;
587 int ret = 0;
588
589 pf = s5k4ecgx_try_fmt(sd, &fmt->format);
590 s5k4ecgx_try_frame_size(&fmt->format, &fsize);
591 fmt->format.colorspace = V4L2_COLORSPACE_JPEG;
592 fmt->format.field = V4L2_FIELD_NONE;
593
594 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
595 if (sd_state) {
596 mf = v4l2_subdev_get_try_format(sd, sd_state, 0);
597 *mf = fmt->format;
598 }
599 return 0;
600 }
601
602 mutex_lock(&priv->lock);
603 if (!priv->streaming) {
604 priv->curr_frmsize = fsize;
605 priv->curr_pixfmt = pf;
606 priv->set_params = 1;
607 } else {
608 ret = -EBUSY;
609 }
610 mutex_unlock(&priv->lock);
611
612 return ret;
613 }
614
615 static const struct v4l2_subdev_pad_ops s5k4ecgx_pad_ops = {
616 .enum_mbus_code = s5k4ecgx_enum_mbus_code,
617 .get_fmt = s5k4ecgx_get_fmt,
618 .set_fmt = s5k4ecgx_set_fmt,
619 };
620
621 /*
622 * V4L2 subdev controls
623 */
s5k4ecgx_s_ctrl(struct v4l2_ctrl * ctrl)624 static int s5k4ecgx_s_ctrl(struct v4l2_ctrl *ctrl)
625 {
626 struct v4l2_subdev *sd = &container_of(ctrl->handler, struct s5k4ecgx,
627 handler)->sd;
628 struct i2c_client *client = v4l2_get_subdevdata(sd);
629 struct s5k4ecgx *priv = to_s5k4ecgx(sd);
630 unsigned int i;
631 int err = 0;
632
633 v4l2_dbg(1, debug, sd, "ctrl: 0x%x, value: %d\n", ctrl->id, ctrl->val);
634
635 mutex_lock(&priv->lock);
636 switch (ctrl->id) {
637 case V4L2_CID_CONTRAST:
638 err = s5k4ecgx_write(client, REG_USER_CONTRAST, ctrl->val);
639 break;
640
641 case V4L2_CID_SATURATION:
642 err = s5k4ecgx_write(client, REG_USER_SATURATION, ctrl->val);
643 break;
644
645 case V4L2_CID_SHARPNESS:
646 /* TODO: Revisit, is this setting for all presets ? */
647 for (i = 0; i < 4 && !err; i++)
648 err = s5k4ecgx_write(client, REG_USER_SHARPNESS(i),
649 ctrl->val * SHARPNESS_DIV);
650 break;
651
652 case V4L2_CID_BRIGHTNESS:
653 err = s5k4ecgx_write(client, REG_USER_BRIGHTNESS, ctrl->val);
654 break;
655 }
656 mutex_unlock(&priv->lock);
657 if (err < 0)
658 v4l2_err(sd, "Failed to write s_ctrl err %d\n", err);
659
660 return err;
661 }
662
663 static const struct v4l2_ctrl_ops s5k4ecgx_ctrl_ops = {
664 .s_ctrl = s5k4ecgx_s_ctrl,
665 };
666
667 /*
668 * Reading s5k4ecgx version information
669 */
s5k4ecgx_registered(struct v4l2_subdev * sd)670 static int s5k4ecgx_registered(struct v4l2_subdev *sd)
671 {
672 int ret;
673 struct s5k4ecgx *priv = to_s5k4ecgx(sd);
674
675 mutex_lock(&priv->lock);
676 ret = __s5k4ecgx_power_on(priv);
677 if (!ret) {
678 ret = s5k4ecgx_read_fw_ver(sd);
679 __s5k4ecgx_power_off(priv);
680 }
681 mutex_unlock(&priv->lock);
682
683 return ret;
684 }
685
686 /*
687 * V4L2 subdev internal operations
688 */
s5k4ecgx_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)689 static int s5k4ecgx_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
690 {
691 struct v4l2_mbus_framefmt *mf = v4l2_subdev_get_try_format(sd,
692 fh->state,
693 0);
694
695 mf->width = s5k4ecgx_prev_sizes[0].size.width;
696 mf->height = s5k4ecgx_prev_sizes[0].size.height;
697 mf->code = s5k4ecgx_formats[0].code;
698 mf->colorspace = V4L2_COLORSPACE_JPEG;
699 mf->field = V4L2_FIELD_NONE;
700
701 return 0;
702 }
703
704 static const struct v4l2_subdev_internal_ops s5k4ecgx_subdev_internal_ops = {
705 .registered = s5k4ecgx_registered,
706 .open = s5k4ecgx_open,
707 };
708
s5k4ecgx_s_power(struct v4l2_subdev * sd,int on)709 static int s5k4ecgx_s_power(struct v4l2_subdev *sd, int on)
710 {
711 struct s5k4ecgx *priv = to_s5k4ecgx(sd);
712 int ret;
713
714 v4l2_dbg(1, debug, sd, "Switching %s\n", on ? "on" : "off");
715
716 if (on) {
717 ret = __s5k4ecgx_power_on(priv);
718 if (ret < 0)
719 return ret;
720 /* Time to stabilize sensor */
721 msleep(100);
722 ret = s5k4ecgx_init_sensor(sd);
723 if (ret < 0)
724 __s5k4ecgx_power_off(priv);
725 else
726 priv->set_params = 1;
727 } else {
728 ret = __s5k4ecgx_power_off(priv);
729 }
730
731 return ret;
732 }
733
s5k4ecgx_log_status(struct v4l2_subdev * sd)734 static int s5k4ecgx_log_status(struct v4l2_subdev *sd)
735 {
736 v4l2_ctrl_handler_log_status(sd->ctrl_handler, sd->name);
737
738 return 0;
739 }
740
741 static const struct v4l2_subdev_core_ops s5k4ecgx_core_ops = {
742 .s_power = s5k4ecgx_s_power,
743 .log_status = s5k4ecgx_log_status,
744 };
745
__s5k4ecgx_s_params(struct s5k4ecgx * priv)746 static int __s5k4ecgx_s_params(struct s5k4ecgx *priv)
747 {
748 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
749 const struct v4l2_rect *crop_rect = &priv->curr_frmsize->input_window;
750 int ret;
751
752 ret = s5k4ecgx_set_input_window(client, crop_rect);
753 if (!ret)
754 ret = s5k4ecgx_set_zoom_window(client, crop_rect);
755 if (!ret)
756 ret = s5k4ecgx_write(client, REG_G_INPUTS_CHANGE_REQ, 1);
757 if (!ret)
758 ret = s5k4ecgx_write(client, 0x70000a1e, 0x28);
759 if (!ret)
760 ret = s5k4ecgx_write(client, 0x70000ad4, 0x3c);
761 if (!ret)
762 ret = s5k4ecgx_set_output_framefmt(priv);
763 if (!ret)
764 ret = s5k4ecgx_write(client, REG_P_PVI_MASK(0), 0x52);
765 if (!ret)
766 ret = s5k4ecgx_write(client, REG_P_FR_TIME_TYPE(0),
767 FR_TIME_DYNAMIC);
768 if (!ret)
769 ret = s5k4ecgx_write(client, REG_P_FR_TIME_Q_TYPE(0),
770 FR_TIME_Q_BEST_FRRATE);
771 if (!ret)
772 ret = s5k4ecgx_write(client, REG_P_MIN_FR_TIME(0),
773 US_TO_FR_TIME(33300));
774 if (!ret)
775 ret = s5k4ecgx_write(client, REG_P_MAX_FR_TIME(0),
776 US_TO_FR_TIME(66600));
777 if (!ret)
778 ret = s5k4ecgx_write(client, REG_P_PREV_MIRROR(0), 0);
779 if (!ret)
780 ret = s5k4ecgx_write(client, REG_P_CAP_MIRROR(0), 0);
781 if (!ret)
782 ret = s5k4ecgx_write(client, REG_G_ACTIVE_PREV_CFG, 0);
783 if (!ret)
784 ret = s5k4ecgx_write(client, REG_G_PREV_OPEN_AFTER_CH, 1);
785 if (!ret)
786 ret = s5k4ecgx_write(client, REG_G_NEW_CFG_SYNC, 1);
787 if (!ret)
788 ret = s5k4ecgx_write(client, REG_G_PREV_CFG_CHG, 1);
789
790 return ret;
791 }
792
__s5k4ecgx_s_stream(struct s5k4ecgx * priv,int on)793 static int __s5k4ecgx_s_stream(struct s5k4ecgx *priv, int on)
794 {
795 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
796 int ret;
797
798 if (on && priv->set_params) {
799 ret = __s5k4ecgx_s_params(priv);
800 if (ret < 0)
801 return ret;
802 priv->set_params = 0;
803 }
804 /*
805 * This enables/disables preview stream only. Capture requests
806 * are not supported yet.
807 */
808 ret = s5k4ecgx_write(client, REG_G_ENABLE_PREV, on);
809 if (ret < 0)
810 return ret;
811 return s5k4ecgx_write(client, REG_G_ENABLE_PREV_CHG, 1);
812 }
813
s5k4ecgx_s_stream(struct v4l2_subdev * sd,int on)814 static int s5k4ecgx_s_stream(struct v4l2_subdev *sd, int on)
815 {
816 struct s5k4ecgx *priv = to_s5k4ecgx(sd);
817 int ret = 0;
818
819 v4l2_dbg(1, debug, sd, "Turn streaming %s\n", on ? "on" : "off");
820
821 mutex_lock(&priv->lock);
822
823 if (priv->streaming == !on) {
824 ret = __s5k4ecgx_s_stream(priv, on);
825 if (!ret)
826 priv->streaming = on & 1;
827 }
828
829 mutex_unlock(&priv->lock);
830 return ret;
831 }
832
833 static const struct v4l2_subdev_video_ops s5k4ecgx_video_ops = {
834 .s_stream = s5k4ecgx_s_stream,
835 };
836
837 static const struct v4l2_subdev_ops s5k4ecgx_ops = {
838 .core = &s5k4ecgx_core_ops,
839 .pad = &s5k4ecgx_pad_ops,
840 .video = &s5k4ecgx_video_ops,
841 };
842
843 /*
844 * GPIO setup
845 */
s5k4ecgx_config_gpio(int nr,int val,const char * name)846 static int s5k4ecgx_config_gpio(int nr, int val, const char *name)
847 {
848 unsigned long flags = val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
849 int ret;
850
851 if (!gpio_is_valid(nr))
852 return 0;
853 ret = gpio_request_one(nr, flags, name);
854 if (!ret)
855 gpio_export(nr, 0);
856
857 return ret;
858 }
859
s5k4ecgx_free_gpios(struct s5k4ecgx * priv)860 static void s5k4ecgx_free_gpios(struct s5k4ecgx *priv)
861 {
862 int i;
863
864 for (i = 0; i < ARRAY_SIZE(priv->gpio); i++) {
865 if (!gpio_is_valid(priv->gpio[i].gpio))
866 continue;
867 gpio_free(priv->gpio[i].gpio);
868 priv->gpio[i].gpio = -EINVAL;
869 }
870 }
871
s5k4ecgx_config_gpios(struct s5k4ecgx * priv,const struct s5k4ecgx_platform_data * pdata)872 static int s5k4ecgx_config_gpios(struct s5k4ecgx *priv,
873 const struct s5k4ecgx_platform_data *pdata)
874 {
875 const struct s5k4ecgx_gpio *gpio = &pdata->gpio_stby;
876 int ret;
877
878 priv->gpio[STBY].gpio = -EINVAL;
879 priv->gpio[RSET].gpio = -EINVAL;
880
881 ret = s5k4ecgx_config_gpio(gpio->gpio, gpio->level, "S5K4ECGX_STBY");
882
883 if (ret) {
884 s5k4ecgx_free_gpios(priv);
885 return ret;
886 }
887 priv->gpio[STBY] = *gpio;
888 if (gpio_is_valid(gpio->gpio))
889 gpio_set_value(gpio->gpio, 0);
890
891 gpio = &pdata->gpio_reset;
892
893 ret = s5k4ecgx_config_gpio(gpio->gpio, gpio->level, "S5K4ECGX_RST");
894 if (ret) {
895 s5k4ecgx_free_gpios(priv);
896 return ret;
897 }
898 priv->gpio[RSET] = *gpio;
899 if (gpio_is_valid(gpio->gpio))
900 gpio_set_value(gpio->gpio, 0);
901
902 return 0;
903 }
904
s5k4ecgx_init_v4l2_ctrls(struct s5k4ecgx * priv)905 static int s5k4ecgx_init_v4l2_ctrls(struct s5k4ecgx *priv)
906 {
907 const struct v4l2_ctrl_ops *ops = &s5k4ecgx_ctrl_ops;
908 struct v4l2_ctrl_handler *hdl = &priv->handler;
909 int ret;
910
911 ret = v4l2_ctrl_handler_init(hdl, 4);
912 if (ret)
913 return ret;
914
915 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -208, 127, 1, 0);
916 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0);
917 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0);
918
919 /* Sharpness default is 24612, and then (24612/SHARPNESS_DIV) = 2 */
920 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -32704/SHARPNESS_DIV,
921 24612/SHARPNESS_DIV, 1, 2);
922 if (hdl->error) {
923 ret = hdl->error;
924 v4l2_ctrl_handler_free(hdl);
925 return ret;
926 }
927 priv->sd.ctrl_handler = hdl;
928
929 return 0;
930 };
931
s5k4ecgx_probe(struct i2c_client * client,const struct i2c_device_id * id)932 static int s5k4ecgx_probe(struct i2c_client *client,
933 const struct i2c_device_id *id)
934 {
935 struct s5k4ecgx_platform_data *pdata = client->dev.platform_data;
936 struct v4l2_subdev *sd;
937 struct s5k4ecgx *priv;
938 int ret, i;
939
940 if (pdata == NULL) {
941 dev_err(&client->dev, "platform data is missing!\n");
942 return -EINVAL;
943 }
944
945 priv = devm_kzalloc(&client->dev, sizeof(struct s5k4ecgx), GFP_KERNEL);
946 if (!priv)
947 return -ENOMEM;
948
949 mutex_init(&priv->lock);
950 priv->streaming = 0;
951
952 sd = &priv->sd;
953 /* Registering subdev */
954 v4l2_i2c_subdev_init(sd, client, &s5k4ecgx_ops);
955 /* Static name; NEVER use in new drivers! */
956 strscpy(sd->name, S5K4ECGX_DRIVER_NAME, sizeof(sd->name));
957
958 sd->internal_ops = &s5k4ecgx_subdev_internal_ops;
959 /* Support v4l2 sub-device user space API */
960 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
961
962 priv->pad.flags = MEDIA_PAD_FL_SOURCE;
963 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
964 ret = media_entity_pads_init(&sd->entity, 1, &priv->pad);
965 if (ret)
966 return ret;
967
968 ret = s5k4ecgx_config_gpios(priv, pdata);
969 if (ret) {
970 dev_err(&client->dev, "Failed to set gpios\n");
971 goto out_err1;
972 }
973 for (i = 0; i < S5K4ECGX_NUM_SUPPLIES; i++)
974 priv->supplies[i].supply = s5k4ecgx_supply_names[i];
975
976 ret = devm_regulator_bulk_get(&client->dev, S5K4ECGX_NUM_SUPPLIES,
977 priv->supplies);
978 if (ret) {
979 dev_err(&client->dev, "Failed to get regulators\n");
980 goto out_err2;
981 }
982 ret = s5k4ecgx_init_v4l2_ctrls(priv);
983 if (ret)
984 goto out_err2;
985
986 priv->curr_pixfmt = &s5k4ecgx_formats[0];
987 priv->curr_frmsize = &s5k4ecgx_prev_sizes[0];
988
989 return 0;
990
991 out_err2:
992 s5k4ecgx_free_gpios(priv);
993 out_err1:
994 media_entity_cleanup(&priv->sd.entity);
995
996 return ret;
997 }
998
s5k4ecgx_remove(struct i2c_client * client)999 static void s5k4ecgx_remove(struct i2c_client *client)
1000 {
1001 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1002 struct s5k4ecgx *priv = to_s5k4ecgx(sd);
1003
1004 mutex_destroy(&priv->lock);
1005 s5k4ecgx_free_gpios(priv);
1006 v4l2_device_unregister_subdev(sd);
1007 v4l2_ctrl_handler_free(&priv->handler);
1008 media_entity_cleanup(&sd->entity);
1009 }
1010
1011 static const struct i2c_device_id s5k4ecgx_id[] = {
1012 { S5K4ECGX_DRIVER_NAME, 0 },
1013 {}
1014 };
1015 MODULE_DEVICE_TABLE(i2c, s5k4ecgx_id);
1016
1017 static struct i2c_driver v4l2_i2c_driver = {
1018 .driver = {
1019 .name = S5K4ECGX_DRIVER_NAME,
1020 },
1021 .probe = s5k4ecgx_probe,
1022 .remove = s5k4ecgx_remove,
1023 .id_table = s5k4ecgx_id,
1024 };
1025
1026 module_i2c_driver(v4l2_i2c_driver);
1027
1028 MODULE_DESCRIPTION("Samsung S5K4ECGX 5MP SOC camera");
1029 MODULE_AUTHOR("Sangwook Lee <sangwook.lee@linaro.org>");
1030 MODULE_AUTHOR("Seok-Young Jang <quartz.jang@samsung.com>");
1031 MODULE_LICENSE("GPL");
1032 MODULE_FIRMWARE(S5K4ECGX_FIRMWARE);
1033