1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
35
36 #include <rdma/ib_verbs.h>
37 #include <rdma/hns-abi.h>
38
39 #define PCI_REVISION_ID_HIP08 0x21
40 #define PCI_REVISION_ID_HIP09 0x30
41
42 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
43
44 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
45
46 #define BA_BYTE_LEN 8
47
48 #define HNS_ROCE_MIN_CQE_NUM 0x40
49 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1
50
51 #define HNS_ROCE_MAX_IRQ_NUM 128
52
53 #define HNS_ROCE_SGE_IN_WQE 2
54 #define HNS_ROCE_SGE_SHIFT 4
55
56 #define EQ_ENABLE 1
57 #define EQ_DISABLE 0
58
59 #define HNS_ROCE_CEQ 0
60 #define HNS_ROCE_AEQ 1
61
62 #define HNS_ROCE_CEQE_SIZE 0x4
63 #define HNS_ROCE_AEQE_SIZE 0x10
64
65 #define HNS_ROCE_V3_EQE_SIZE 0x40
66
67 #define HNS_ROCE_V2_CQE_SIZE 32
68 #define HNS_ROCE_V3_CQE_SIZE 64
69
70 #define HNS_ROCE_V2_QPC_SZ 256
71 #define HNS_ROCE_V3_QPC_SZ 512
72
73 #define HNS_ROCE_MAX_PORTS 6
74 #define HNS_ROCE_GID_SIZE 16
75 #define HNS_ROCE_SGE_SIZE 16
76 #define HNS_ROCE_DWQE_SIZE 65536
77
78 #define HNS_ROCE_HOP_NUM_0 0xff
79
80 #define MR_TYPE_MR 0x00
81 #define MR_TYPE_FRMR 0x01
82 #define MR_TYPE_DMA 0x03
83
84 #define HNS_ROCE_FRMR_MAX_PA 512
85
86 #define PKEY_ID 0xffff
87 #define NODE_DESC_SIZE 64
88 #define DB_REG_OFFSET 0x1000
89
90 /* Configure to HW for PAGE_SIZE larger than 4KB */
91 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
92
93 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
94 #define SRQ_DB_REG 0x230
95
96 #define HNS_ROCE_QP_BANK_NUM 8
97 #define HNS_ROCE_CQ_BANK_NUM 4
98
99 #define CQ_BANKID_SHIFT 2
100
101 enum {
102 SERV_TYPE_RC,
103 SERV_TYPE_UC,
104 SERV_TYPE_RD,
105 SERV_TYPE_UD,
106 SERV_TYPE_XRC = 5,
107 };
108
109 enum hns_roce_event {
110 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
111 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
112 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
113 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
114 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
115 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
116 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
117 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
118 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
119 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
120 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
121 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
122 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
123 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
124 /* 0x10 and 0x11 is unused in currently application case */
125 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
126 HNS_ROCE_EVENT_TYPE_MB = 0x13,
127 HNS_ROCE_EVENT_TYPE_FLR = 0x15,
128 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16,
129 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17,
130 };
131
132 enum {
133 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
134 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
135 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
136 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3),
137 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4),
138 HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
139 HNS_ROCE_CAP_FLAG_XRC = BIT(6),
140 HNS_ROCE_CAP_FLAG_MW = BIT(7),
141 HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
142 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9),
143 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
144 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12),
145 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14),
146 HNS_ROCE_CAP_FLAG_STASH = BIT(17),
147 };
148
149 #define HNS_ROCE_DB_TYPE_COUNT 2
150 #define HNS_ROCE_DB_UNIT_SIZE 4
151
152 enum {
153 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
154 };
155
156 enum hns_roce_reset_stage {
157 HNS_ROCE_STATE_NON_RST,
158 HNS_ROCE_STATE_RST_BEF_DOWN,
159 HNS_ROCE_STATE_RST_DOWN,
160 HNS_ROCE_STATE_RST_UNINIT,
161 HNS_ROCE_STATE_RST_INIT,
162 HNS_ROCE_STATE_RST_INITED,
163 };
164
165 enum hns_roce_instance_state {
166 HNS_ROCE_STATE_NON_INIT,
167 HNS_ROCE_STATE_INIT,
168 HNS_ROCE_STATE_INITED,
169 HNS_ROCE_STATE_UNINIT,
170 };
171
172 enum {
173 HNS_ROCE_RST_DIRECT_RETURN = 0,
174 };
175
176 #define HNS_ROCE_CMD_SUCCESS 1
177
178 /* The minimum page size is 4K for hardware */
179 #define HNS_HW_PAGE_SHIFT 12
180 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
181
182 struct hns_roce_uar {
183 u64 pfn;
184 unsigned long index;
185 unsigned long logic_idx;
186 };
187
188 enum hns_roce_mmap_type {
189 HNS_ROCE_MMAP_TYPE_DB = 1,
190 HNS_ROCE_MMAP_TYPE_DWQE,
191 };
192
193 struct hns_user_mmap_entry {
194 struct rdma_user_mmap_entry rdma_entry;
195 enum hns_roce_mmap_type mmap_type;
196 u64 address;
197 };
198
199 struct hns_roce_ucontext {
200 struct ib_ucontext ibucontext;
201 struct hns_roce_uar uar;
202 struct list_head page_list;
203 struct mutex page_mutex;
204 struct hns_user_mmap_entry *db_mmap_entry;
205 u32 config;
206 };
207
208 struct hns_roce_pd {
209 struct ib_pd ibpd;
210 unsigned long pdn;
211 };
212
213 struct hns_roce_xrcd {
214 struct ib_xrcd ibxrcd;
215 u32 xrcdn;
216 };
217
218 struct hns_roce_bitmap {
219 /* Bitmap Traversal last a bit which is 1 */
220 unsigned long last;
221 unsigned long top;
222 unsigned long max;
223 unsigned long reserved_top;
224 unsigned long mask;
225 spinlock_t lock;
226 unsigned long *table;
227 };
228
229 struct hns_roce_ida {
230 struct ida ida;
231 u32 min; /* Lowest ID to allocate. */
232 u32 max; /* Highest ID to allocate. */
233 };
234
235 /* For Hardware Entry Memory */
236 struct hns_roce_hem_table {
237 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
238 u32 type;
239 /* HEM array elment num */
240 unsigned long num_hem;
241 /* Single obj size */
242 unsigned long obj_size;
243 unsigned long table_chunk_size;
244 struct mutex mutex;
245 struct hns_roce_hem **hem;
246 u64 **bt_l1;
247 dma_addr_t *bt_l1_dma_addr;
248 u64 **bt_l0;
249 dma_addr_t *bt_l0_dma_addr;
250 };
251
252 struct hns_roce_buf_region {
253 u32 offset; /* page offset */
254 u32 count; /* page count */
255 int hopnum; /* addressing hop num */
256 };
257
258 #define HNS_ROCE_MAX_BT_REGION 3
259 #define HNS_ROCE_MAX_BT_LEVEL 3
260 struct hns_roce_hem_list {
261 struct list_head root_bt;
262 /* link all bt dma mem by hop config */
263 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
264 struct list_head btm_bt; /* link all bottom bt in @mid_bt */
265 dma_addr_t root_ba; /* pointer to the root ba table */
266 };
267
268 struct hns_roce_buf_attr {
269 struct {
270 size_t size; /* region size */
271 int hopnum; /* multi-hop addressing hop num */
272 } region[HNS_ROCE_MAX_BT_REGION];
273 unsigned int region_count; /* valid region count */
274 unsigned int page_shift; /* buffer page shift */
275 unsigned int user_access; /* umem access flag */
276 bool mtt_only; /* only alloc buffer-required MTT memory */
277 };
278
279 struct hns_roce_hem_cfg {
280 dma_addr_t root_ba; /* root BA table's address */
281 bool is_direct; /* addressing without BA table */
282 unsigned int ba_pg_shift; /* BA table page shift */
283 unsigned int buf_pg_shift; /* buffer page shift */
284 unsigned int buf_pg_count; /* buffer page count */
285 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
286 unsigned int region_count;
287 };
288
289 /* memory translate region */
290 struct hns_roce_mtr {
291 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
292 struct ib_umem *umem; /* user space buffer */
293 struct hns_roce_buf *kmem; /* kernel space buffer */
294 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */
295 };
296
297 struct hns_roce_mw {
298 struct ib_mw ibmw;
299 u32 pdn;
300 u32 rkey;
301 int enabled; /* MW's active status */
302 u32 pbl_hop_num;
303 u32 pbl_ba_pg_sz;
304 u32 pbl_buf_pg_sz;
305 };
306
307 struct hns_roce_mr {
308 struct ib_mr ibmr;
309 u64 iova; /* MR's virtual original addr */
310 u64 size; /* Address range of MR */
311 u32 key; /* Key of MR */
312 u32 pd; /* PD num of MR */
313 u32 access; /* Access permission of MR */
314 int enabled; /* MR's active status */
315 int type; /* MR's register type */
316 u32 pbl_hop_num; /* multi-hop number */
317 struct hns_roce_mtr pbl_mtr;
318 u32 npages;
319 dma_addr_t *page_list;
320 };
321
322 struct hns_roce_mr_table {
323 struct hns_roce_ida mtpt_ida;
324 struct hns_roce_hem_table mtpt_table;
325 };
326
327 struct hns_roce_wq {
328 u64 *wrid; /* Work request ID */
329 spinlock_t lock;
330 u32 wqe_cnt; /* WQE num */
331 u32 max_gs;
332 u32 rsv_sge;
333 u32 offset;
334 u32 wqe_shift; /* WQE size */
335 u32 head;
336 u32 tail;
337 void __iomem *db_reg;
338 u32 ext_sge_cnt;
339 };
340
341 struct hns_roce_sge {
342 unsigned int sge_cnt; /* SGE num */
343 u32 offset;
344 u32 sge_shift; /* SGE size */
345 };
346
347 struct hns_roce_buf_list {
348 void *buf;
349 dma_addr_t map;
350 };
351
352 /*
353 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
354 * dma address range.
355 *
356 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
357 *
358 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
359 * the allocated size is smaller than the required size.
360 */
361 enum {
362 HNS_ROCE_BUF_DIRECT = BIT(0),
363 HNS_ROCE_BUF_NOSLEEP = BIT(1),
364 HNS_ROCE_BUF_NOFAIL = BIT(2),
365 };
366
367 struct hns_roce_buf {
368 struct hns_roce_buf_list *trunk_list;
369 u32 ntrunks;
370 u32 npages;
371 unsigned int trunk_shift;
372 unsigned int page_shift;
373 };
374
375 struct hns_roce_db_pgdir {
376 struct list_head list;
377 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
378 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
379 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT];
380 u32 *page;
381 dma_addr_t db_dma;
382 };
383
384 struct hns_roce_user_db_page {
385 struct list_head list;
386 struct ib_umem *umem;
387 unsigned long user_virt;
388 refcount_t refcount;
389 };
390
391 struct hns_roce_db {
392 u32 *db_record;
393 union {
394 struct hns_roce_db_pgdir *pgdir;
395 struct hns_roce_user_db_page *user_page;
396 } u;
397 dma_addr_t dma;
398 void *virt_addr;
399 unsigned long index;
400 unsigned long order;
401 };
402
403 struct hns_roce_cq {
404 struct ib_cq ib_cq;
405 struct hns_roce_mtr mtr;
406 struct hns_roce_db db;
407 u32 flags;
408 spinlock_t lock;
409 u32 cq_depth;
410 u32 cons_index;
411 u32 *set_ci_db;
412 void __iomem *db_reg;
413 int arm_sn;
414 int cqe_size;
415 unsigned long cqn;
416 u32 vector;
417 refcount_t refcount;
418 struct completion free;
419 struct list_head sq_list; /* all qps on this send cq */
420 struct list_head rq_list; /* all qps on this recv cq */
421 int is_armed; /* cq is armed */
422 struct list_head node; /* all armed cqs are on a list */
423 };
424
425 struct hns_roce_idx_que {
426 struct hns_roce_mtr mtr;
427 u32 entry_shift;
428 unsigned long *bitmap;
429 u32 head;
430 u32 tail;
431 };
432
433 struct hns_roce_srq {
434 struct ib_srq ibsrq;
435 unsigned long srqn;
436 u32 wqe_cnt;
437 int max_gs;
438 u32 rsv_sge;
439 u32 wqe_shift;
440 u32 cqn;
441 u32 xrcdn;
442 void __iomem *db_reg;
443
444 refcount_t refcount;
445 struct completion free;
446
447 struct hns_roce_mtr buf_mtr;
448
449 u64 *wrid;
450 struct hns_roce_idx_que idx_que;
451 spinlock_t lock;
452 struct mutex mutex;
453 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
454 };
455
456 struct hns_roce_uar_table {
457 struct hns_roce_bitmap bitmap;
458 };
459
460 struct hns_roce_bank {
461 struct ida ida;
462 u32 inuse; /* Number of IDs allocated */
463 u32 min; /* Lowest ID to allocate. */
464 u32 max; /* Highest ID to allocate. */
465 u32 next; /* Next ID to allocate. */
466 };
467
468 struct hns_roce_idx_table {
469 u32 *spare_idx;
470 u32 head;
471 u32 tail;
472 };
473
474 struct hns_roce_qp_table {
475 struct hns_roce_hem_table qp_table;
476 struct hns_roce_hem_table irrl_table;
477 struct hns_roce_hem_table trrl_table;
478 struct hns_roce_hem_table sccc_table;
479 struct mutex scc_mutex;
480 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
481 struct mutex bank_mutex;
482 struct hns_roce_idx_table idx_table;
483 };
484
485 struct hns_roce_cq_table {
486 struct xarray array;
487 struct hns_roce_hem_table table;
488 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
489 struct mutex bank_mutex;
490 };
491
492 struct hns_roce_srq_table {
493 struct hns_roce_ida srq_ida;
494 struct xarray xa;
495 struct hns_roce_hem_table table;
496 };
497
498 struct hns_roce_av {
499 u8 port;
500 u8 gid_index;
501 u8 stat_rate;
502 u8 hop_limit;
503 u32 flowlabel;
504 u16 udp_sport;
505 u8 sl;
506 u8 tclass;
507 u8 dgid[HNS_ROCE_GID_SIZE];
508 u8 mac[ETH_ALEN];
509 u16 vlan_id;
510 u8 vlan_en;
511 };
512
513 struct hns_roce_ah {
514 struct ib_ah ibah;
515 struct hns_roce_av av;
516 };
517
518 struct hns_roce_cmd_context {
519 struct completion done;
520 int result;
521 int next;
522 u64 out_param;
523 u16 token;
524 u16 busy;
525 };
526
527 enum hns_roce_cmdq_state {
528 HNS_ROCE_CMDQ_STATE_NORMAL,
529 HNS_ROCE_CMDQ_STATE_FATAL_ERR,
530 };
531
532 struct hns_roce_cmdq {
533 struct dma_pool *pool;
534 struct semaphore poll_sem;
535 /*
536 * Event mode: cmd register mutex protection,
537 * ensure to not exceed max_cmds and user use limit region
538 */
539 struct semaphore event_sem;
540 int max_cmds;
541 spinlock_t context_lock;
542 int free_head;
543 struct hns_roce_cmd_context *context;
544 /*
545 * Process whether use event mode, init default non-zero
546 * After the event queue of cmd event ready,
547 * can switch into event mode
548 * close device, switch into poll mode(non event mode)
549 */
550 u8 use_events;
551 enum hns_roce_cmdq_state state;
552 };
553
554 struct hns_roce_cmd_mailbox {
555 void *buf;
556 dma_addr_t dma;
557 };
558
559 struct hns_roce_mbox_msg {
560 u64 in_param;
561 u64 out_param;
562 u8 cmd;
563 u32 tag;
564 u16 token;
565 u8 event_en;
566 };
567
568 struct hns_roce_dev;
569
570 struct hns_roce_rinl_sge {
571 void *addr;
572 u32 len;
573 };
574
575 struct hns_roce_rinl_wqe {
576 struct hns_roce_rinl_sge *sg_list;
577 u32 sge_cnt;
578 };
579
580 struct hns_roce_rinl_buf {
581 struct hns_roce_rinl_wqe *wqe_list;
582 u32 wqe_cnt;
583 };
584
585 enum {
586 HNS_ROCE_FLUSH_FLAG = 0,
587 };
588
589 struct hns_roce_work {
590 struct hns_roce_dev *hr_dev;
591 struct work_struct work;
592 int event_type;
593 int sub_type;
594 u32 queue_num;
595 };
596
597 struct hns_roce_qp {
598 struct ib_qp ibqp;
599 struct hns_roce_wq rq;
600 struct hns_roce_db rdb;
601 struct hns_roce_db sdb;
602 unsigned long en_flags;
603 enum ib_sig_type sq_signal_bits;
604 struct hns_roce_wq sq;
605
606 struct hns_roce_mtr mtr;
607
608 u32 buff_size;
609 struct mutex mutex;
610 u8 port;
611 u8 phy_port;
612 u8 sl;
613 u8 resp_depth;
614 u8 state;
615 u32 atomic_rd_en;
616 u32 qkey;
617 void (*event)(struct hns_roce_qp *qp,
618 enum hns_roce_event event_type);
619 unsigned long qpn;
620
621 u32 xrcdn;
622
623 refcount_t refcount;
624 struct completion free;
625
626 struct hns_roce_sge sge;
627 u32 next_sge;
628 enum ib_mtu path_mtu;
629 u32 max_inline_data;
630 u8 free_mr_en;
631
632 /* 0: flush needed, 1: unneeded */
633 unsigned long flush_flag;
634 struct hns_roce_work flush_work;
635 struct hns_roce_rinl_buf rq_inl_buf;
636 struct list_head node; /* all qps are on a list */
637 struct list_head rq_node; /* all recv qps are on a list */
638 struct list_head sq_node; /* all send qps are on a list */
639 struct hns_user_mmap_entry *dwqe_mmap_entry;
640 u32 config;
641 };
642
643 struct hns_roce_ib_iboe {
644 spinlock_t lock;
645 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
646 struct notifier_block nb;
647 u8 phy_port[HNS_ROCE_MAX_PORTS];
648 };
649
650 struct hns_roce_ceqe {
651 __le32 comp;
652 __le32 rsv[15];
653 };
654
655 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l)
656
657 #define CEQE_CQN CEQE_FIELD_LOC(23, 0)
658 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31)
659
660 struct hns_roce_aeqe {
661 __le32 asyn;
662 union {
663 struct {
664 __le32 num;
665 u32 rsv0;
666 u32 rsv1;
667 } queue_event;
668
669 struct {
670 __le64 out_param;
671 __le16 token;
672 u8 status;
673 u8 rsv0;
674 } __packed cmd;
675 } event;
676 __le32 rsv[12];
677 };
678
679 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l)
680
681 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0)
682 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8)
683 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31)
684 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32)
685
686 struct hns_roce_eq {
687 struct hns_roce_dev *hr_dev;
688 void __iomem *db_reg;
689
690 int type_flag; /* Aeq:1 ceq:0 */
691 int eqn;
692 u32 entries;
693 int eqe_size;
694 int irq;
695 u32 cons_index;
696 int over_ignore;
697 int coalesce;
698 int arm_st;
699 int hop_num;
700 struct hns_roce_mtr mtr;
701 u16 eq_max_cnt;
702 u32 eq_period;
703 int shift;
704 int event_type;
705 int sub_type;
706 };
707
708 struct hns_roce_eq_table {
709 struct hns_roce_eq *eq;
710 };
711
712 enum cong_type {
713 CONG_TYPE_DCQCN,
714 CONG_TYPE_LDCP,
715 CONG_TYPE_HC3,
716 CONG_TYPE_DIP,
717 };
718
719 struct hns_roce_caps {
720 u64 fw_ver;
721 u8 num_ports;
722 int gid_table_len[HNS_ROCE_MAX_PORTS];
723 int pkey_table_len[HNS_ROCE_MAX_PORTS];
724 int local_ca_ack_delay;
725 int num_uars;
726 u32 phy_num_uars;
727 u32 max_sq_sg;
728 u32 max_sq_inline;
729 u32 max_rq_sg;
730 u32 rsv0;
731 u32 num_qps;
732 u32 num_pi_qps;
733 u32 reserved_qps;
734 u32 num_srqs;
735 u32 max_wqes;
736 u32 max_srq_wrs;
737 u32 max_srq_sges;
738 u32 max_sq_desc_sz;
739 u32 max_rq_desc_sz;
740 u32 rsv2;
741 int max_qp_init_rdma;
742 int max_qp_dest_rdma;
743 u32 num_cqs;
744 u32 max_cqes;
745 u32 min_cqes;
746 u32 min_wqes;
747 u32 reserved_cqs;
748 u32 reserved_srqs;
749 int num_aeq_vectors;
750 int num_comp_vectors;
751 int num_other_vectors;
752 u32 num_mtpts;
753 u32 rsv1;
754 u32 num_srqwqe_segs;
755 u32 num_idx_segs;
756 int reserved_mrws;
757 int reserved_uars;
758 int num_pds;
759 int reserved_pds;
760 u32 num_xrcds;
761 u32 reserved_xrcds;
762 u32 mtt_entry_sz;
763 u32 cqe_sz;
764 u32 page_size_cap;
765 u32 reserved_lkey;
766 int mtpt_entry_sz;
767 int qpc_sz;
768 int irrl_entry_sz;
769 int trrl_entry_sz;
770 int cqc_entry_sz;
771 int sccc_sz;
772 int qpc_timer_entry_sz;
773 int cqc_timer_entry_sz;
774 int srqc_entry_sz;
775 int idx_entry_sz;
776 u32 pbl_ba_pg_sz;
777 u32 pbl_buf_pg_sz;
778 u32 pbl_hop_num;
779 int aeqe_depth;
780 int ceqe_depth;
781 u32 aeqe_size;
782 u32 ceqe_size;
783 enum ib_mtu max_mtu;
784 u32 qpc_bt_num;
785 u32 qpc_timer_bt_num;
786 u32 srqc_bt_num;
787 u32 cqc_bt_num;
788 u32 cqc_timer_bt_num;
789 u32 mpt_bt_num;
790 u32 eqc_bt_num;
791 u32 smac_bt_num;
792 u32 sgid_bt_num;
793 u32 sccc_bt_num;
794 u32 gmv_bt_num;
795 u32 qpc_ba_pg_sz;
796 u32 qpc_buf_pg_sz;
797 u32 qpc_hop_num;
798 u32 srqc_ba_pg_sz;
799 u32 srqc_buf_pg_sz;
800 u32 srqc_hop_num;
801 u32 cqc_ba_pg_sz;
802 u32 cqc_buf_pg_sz;
803 u32 cqc_hop_num;
804 u32 mpt_ba_pg_sz;
805 u32 mpt_buf_pg_sz;
806 u32 mpt_hop_num;
807 u32 mtt_ba_pg_sz;
808 u32 mtt_buf_pg_sz;
809 u32 mtt_hop_num;
810 u32 wqe_sq_hop_num;
811 u32 wqe_sge_hop_num;
812 u32 wqe_rq_hop_num;
813 u32 sccc_ba_pg_sz;
814 u32 sccc_buf_pg_sz;
815 u32 sccc_hop_num;
816 u32 qpc_timer_ba_pg_sz;
817 u32 qpc_timer_buf_pg_sz;
818 u32 qpc_timer_hop_num;
819 u32 cqc_timer_ba_pg_sz;
820 u32 cqc_timer_buf_pg_sz;
821 u32 cqc_timer_hop_num;
822 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
823 u32 cqe_buf_pg_sz;
824 u32 cqe_hop_num;
825 u32 srqwqe_ba_pg_sz;
826 u32 srqwqe_buf_pg_sz;
827 u32 srqwqe_hop_num;
828 u32 idx_ba_pg_sz;
829 u32 idx_buf_pg_sz;
830 u32 idx_hop_num;
831 u32 eqe_ba_pg_sz;
832 u32 eqe_buf_pg_sz;
833 u32 eqe_hop_num;
834 u32 gmv_entry_num;
835 u32 gmv_entry_sz;
836 u32 gmv_ba_pg_sz;
837 u32 gmv_buf_pg_sz;
838 u32 gmv_hop_num;
839 u32 sl_num;
840 u32 llm_buf_pg_sz;
841 u32 chunk_sz; /* chunk size in non multihop mode */
842 u64 flags;
843 u16 default_ceq_max_cnt;
844 u16 default_ceq_period;
845 u16 default_aeq_max_cnt;
846 u16 default_aeq_period;
847 u16 default_aeq_arm_st;
848 u16 default_ceq_arm_st;
849 enum cong_type cong_type;
850 };
851
852 enum hns_roce_device_state {
853 HNS_ROCE_DEVICE_STATE_INITED,
854 HNS_ROCE_DEVICE_STATE_RST_DOWN,
855 HNS_ROCE_DEVICE_STATE_UNINIT,
856 };
857
858 struct hns_roce_hw {
859 int (*cmq_init)(struct hns_roce_dev *hr_dev);
860 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
861 int (*hw_profile)(struct hns_roce_dev *hr_dev);
862 int (*hw_init)(struct hns_roce_dev *hr_dev);
863 void (*hw_exit)(struct hns_roce_dev *hr_dev);
864 int (*post_mbox)(struct hns_roce_dev *hr_dev,
865 struct hns_roce_mbox_msg *mbox_msg);
866 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev);
867 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
868 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index,
869 const union ib_gid *gid, const struct ib_gid_attr *attr);
870 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port,
871 const u8 *addr);
872 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
873 struct hns_roce_mr *mr);
874 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
875 struct hns_roce_mr *mr, int flags,
876 void *mb_buf);
877 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
878 struct hns_roce_mr *mr);
879 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
880 void (*write_cqc)(struct hns_roce_dev *hr_dev,
881 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
882 dma_addr_t dma_handle);
883 int (*set_hem)(struct hns_roce_dev *hr_dev,
884 struct hns_roce_hem_table *table, int obj, u32 step_idx);
885 int (*clear_hem)(struct hns_roce_dev *hr_dev,
886 struct hns_roce_hem_table *table, int obj,
887 u32 step_idx);
888 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
889 int attr_mask, enum ib_qp_state cur_state,
890 enum ib_qp_state new_state);
891 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
892 struct hns_roce_qp *hr_qp);
893 void (*dereg_mr)(struct hns_roce_dev *hr_dev);
894 int (*init_eq)(struct hns_roce_dev *hr_dev);
895 void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
896 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
897 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer);
898 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer);
899 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer);
900 const struct ib_device_ops *hns_roce_dev_ops;
901 const struct ib_device_ops *hns_roce_dev_srq_ops;
902 };
903
904 struct hns_roce_dev {
905 struct ib_device ib_dev;
906 struct pci_dev *pci_dev;
907 struct device *dev;
908 struct hns_roce_uar priv_uar;
909 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
910 spinlock_t sm_lock;
911 bool active;
912 bool is_reset;
913 bool dis_db;
914 unsigned long reset_cnt;
915 struct hns_roce_ib_iboe iboe;
916 enum hns_roce_device_state state;
917 struct list_head qp_list; /* list of all qps on this dev */
918 spinlock_t qp_list_lock; /* protect qp_list */
919 struct list_head dip_list; /* list of all dest ips on this dev */
920 spinlock_t dip_list_lock; /* protect dip_list */
921
922 struct list_head pgdir_list;
923 struct mutex pgdir_mutex;
924 int irq[HNS_ROCE_MAX_IRQ_NUM];
925 u8 __iomem *reg_base;
926 void __iomem *mem_base;
927 struct hns_roce_caps caps;
928 struct xarray qp_table_xa;
929
930 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
931 u64 sys_image_guid;
932 u32 vendor_id;
933 u32 vendor_part_id;
934 u32 hw_rev;
935 void __iomem *priv_addr;
936
937 struct hns_roce_cmdq cmd;
938 struct hns_roce_ida pd_ida;
939 struct hns_roce_ida xrcd_ida;
940 struct hns_roce_ida uar_ida;
941 struct hns_roce_mr_table mr_table;
942 struct hns_roce_cq_table cq_table;
943 struct hns_roce_srq_table srq_table;
944 struct hns_roce_qp_table qp_table;
945 struct hns_roce_eq_table eq_table;
946 struct hns_roce_hem_table qpc_timer_table;
947 struct hns_roce_hem_table cqc_timer_table;
948 /* GMV is the memory area that the driver allocates for the hardware
949 * to store SGID, SMAC and VLAN information.
950 */
951 struct hns_roce_hem_table gmv_table;
952
953 int cmd_mod;
954 int loop_idc;
955 u32 sdb_offset;
956 u32 odb_offset;
957 const struct hns_roce_hw *hw;
958 void *priv;
959 struct workqueue_struct *irq_workq;
960 struct work_struct ecc_work;
961 u32 func_num;
962 u32 is_vf;
963 u32 cong_algo_tmpl_id;
964 u64 dwqe_page;
965 };
966
to_hr_dev(struct ib_device * ib_dev)967 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
968 {
969 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
970 }
971
972 static inline struct hns_roce_ucontext
to_hr_ucontext(struct ib_ucontext * ibucontext)973 *to_hr_ucontext(struct ib_ucontext *ibucontext)
974 {
975 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
976 }
977
to_hr_pd(struct ib_pd * ibpd)978 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
979 {
980 return container_of(ibpd, struct hns_roce_pd, ibpd);
981 }
982
to_hr_xrcd(struct ib_xrcd * ibxrcd)983 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
984 {
985 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
986 }
987
to_hr_ah(struct ib_ah * ibah)988 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
989 {
990 return container_of(ibah, struct hns_roce_ah, ibah);
991 }
992
to_hr_mr(struct ib_mr * ibmr)993 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
994 {
995 return container_of(ibmr, struct hns_roce_mr, ibmr);
996 }
997
to_hr_mw(struct ib_mw * ibmw)998 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
999 {
1000 return container_of(ibmw, struct hns_roce_mw, ibmw);
1001 }
1002
to_hr_qp(struct ib_qp * ibqp)1003 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1004 {
1005 return container_of(ibqp, struct hns_roce_qp, ibqp);
1006 }
1007
to_hr_cq(struct ib_cq * ib_cq)1008 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1009 {
1010 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1011 }
1012
to_hr_srq(struct ib_srq * ibsrq)1013 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1014 {
1015 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1016 }
1017
1018 static inline struct hns_user_mmap_entry *
to_hns_mmap(struct rdma_user_mmap_entry * rdma_entry)1019 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry)
1020 {
1021 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry);
1022 }
1023
hns_roce_write64_k(__le32 val[2],void __iomem * dest)1024 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1025 {
1026 writeq(*(u64 *)val, dest);
1027 }
1028
1029 static inline struct hns_roce_qp
__hns_roce_qp_lookup(struct hns_roce_dev * hr_dev,u32 qpn)1030 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1031 {
1032 return xa_load(&hr_dev->qp_table_xa, qpn);
1033 }
1034
hns_roce_buf_offset(struct hns_roce_buf * buf,unsigned int offset)1035 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1036 unsigned int offset)
1037 {
1038 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1039 (offset & ((1 << buf->trunk_shift) - 1));
1040 }
1041
hns_roce_buf_dma_addr(struct hns_roce_buf * buf,unsigned int offset)1042 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf,
1043 unsigned int offset)
1044 {
1045 return buf->trunk_list[offset >> buf->trunk_shift].map +
1046 (offset & ((1 << buf->trunk_shift) - 1));
1047 }
1048
hns_roce_buf_page(struct hns_roce_buf * buf,u32 idx)1049 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1050 {
1051 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift);
1052 }
1053
1054 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1055
to_hr_hw_page_addr(u64 addr)1056 static inline u64 to_hr_hw_page_addr(u64 addr)
1057 {
1058 return addr >> HNS_HW_PAGE_SHIFT;
1059 }
1060
to_hr_hw_page_shift(u32 page_shift)1061 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1062 {
1063 return page_shift - HNS_HW_PAGE_SHIFT;
1064 }
1065
to_hr_hem_hopnum(u32 hopnum,u32 count)1066 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1067 {
1068 if (count > 0)
1069 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1070
1071 return 0;
1072 }
1073
to_hr_hem_entries_size(u32 count,u32 buf_shift)1074 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1075 {
1076 return hr_hw_page_align(count << buf_shift);
1077 }
1078
to_hr_hem_entries_count(u32 count,u32 buf_shift)1079 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1080 {
1081 return hr_hw_page_align(count << buf_shift) >> buf_shift;
1082 }
1083
to_hr_hem_entries_shift(u32 count,u32 buf_shift)1084 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1085 {
1086 if (!count)
1087 return 0;
1088
1089 return ilog2(to_hr_hem_entries_count(count, buf_shift));
1090 }
1091
1092 #define DSCP_SHIFT 2
1093
get_tclass(const struct ib_global_route * grh)1094 static inline u8 get_tclass(const struct ib_global_route *grh)
1095 {
1096 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1097 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1098 }
1099
1100 void hns_roce_init_uar_table(struct hns_roce_dev *dev);
1101 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1102
1103 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1104 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1105 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1106 u64 out_param);
1107 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1108 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1109
1110 /* hns roce hw need current block and next block addr from mtt */
1111 #define MTT_MIN_COUNT 2
1112 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1113 u32 offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1114 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1115 struct hns_roce_buf_attr *buf_attr,
1116 unsigned int page_shift, struct ib_udata *udata,
1117 unsigned long user_addr);
1118 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1119 struct hns_roce_mtr *mtr);
1120 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1121 dma_addr_t *pages, unsigned int page_cnt);
1122
1123 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1124 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1125 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1126 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1127 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1128 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1129
1130 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1131 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1132 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1133
1134 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1135
1136 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1137 struct ib_udata *udata);
1138 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
hns_roce_destroy_ah(struct ib_ah * ah,u32 flags)1139 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1140 {
1141 return 0;
1142 }
1143
1144 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1145 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1146
1147 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1148 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1149 u64 virt_addr, int access_flags,
1150 struct ib_udata *udata);
1151 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1152 u64 length, u64 virt_addr,
1153 int mr_access_flags, struct ib_pd *pd,
1154 struct ib_udata *udata);
1155 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1156 u32 max_num_sg);
1157 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1158 unsigned int *sg_offset);
1159 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1160 unsigned long key_to_hw_index(u32 key);
1161
1162 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1163 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1164
1165 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1166 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1167 u32 page_shift, u32 flags);
1168
1169 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1170 int buf_cnt, struct hns_roce_buf *buf,
1171 unsigned int page_shift);
1172 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1173 int buf_cnt, struct ib_umem *umem,
1174 unsigned int page_shift);
1175
1176 int hns_roce_create_srq(struct ib_srq *srq,
1177 struct ib_srq_init_attr *srq_init_attr,
1178 struct ib_udata *udata);
1179 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1180 enum ib_srq_attr_mask srq_attr_mask,
1181 struct ib_udata *udata);
1182 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1183
1184 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1185 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1186
1187 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr,
1188 struct ib_udata *udata);
1189 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1190 int attr_mask, struct ib_udata *udata);
1191 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1192 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1193 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1194 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1195 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1196 struct ib_cq *ib_cq);
1197 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1198 struct hns_roce_cq *recv_cq);
1199 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1200 struct hns_roce_cq *recv_cq);
1201 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1202 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1203 struct ib_udata *udata);
1204 __be32 send_ieth(const struct ib_send_wr *wr);
1205 int to_hr_qp_type(int qp_type);
1206
1207 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1208 struct ib_udata *udata);
1209
1210 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1211 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1212 struct hns_roce_db *db);
1213 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1214 struct hns_roce_db *db);
1215 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1216 int order);
1217 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1218
1219 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1220 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1221 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp);
1222 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1223 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1224 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index);
1225 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1226 int hns_roce_init(struct hns_roce_dev *hr_dev);
1227 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1228 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq);
1229 int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq);
1230 int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp);
1231 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp);
1232 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr);
1233 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr);
1234 struct hns_user_mmap_entry *
1235 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
1236 size_t length,
1237 enum hns_roce_mmap_type mmap_type);
1238 #endif /* _HNS_ROCE_DEVICE_H */
1239