1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IIO driver for the Apex Embedded Systems STX104
4 * Copyright (C) 2016 William Breathitt Gray
5 */
6 #include <linux/bitops.h>
7 #include <linux/device.h>
8 #include <linux/errno.h>
9 #include <linux/gpio/driver.h>
10 #include <linux/iio/iio.h>
11 #include <linux/iio/types.h>
12 #include <linux/io.h>
13 #include <linux/ioport.h>
14 #include <linux/isa.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/spinlock.h>
19 #include <linux/types.h>
20
21 #define STX104_OUT_CHAN(chan) { \
22 .type = IIO_VOLTAGE, \
23 .channel = chan, \
24 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
25 .indexed = 1, \
26 .output = 1 \
27 }
28 #define STX104_IN_CHAN(chan, diff) { \
29 .type = IIO_VOLTAGE, \
30 .channel = chan, \
31 .channel2 = chan, \
32 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_HARDWAREGAIN) | \
33 BIT(IIO_CHAN_INFO_OFFSET) | BIT(IIO_CHAN_INFO_SCALE), \
34 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
35 .indexed = 1, \
36 .differential = diff \
37 }
38
39 #define STX104_NUM_OUT_CHAN 2
40
41 #define STX104_EXTENT 16
42
43 static unsigned int base[max_num_isa_dev(STX104_EXTENT)];
44 static unsigned int num_stx104;
45 module_param_hw_array(base, uint, ioport, &num_stx104, 0);
46 MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
47
48 /**
49 * struct stx104_reg - device register structure
50 * @ssr_ad: Software Strobe Register and ADC Data
51 * @achan: ADC Channel
52 * @dio: Digital I/O
53 * @dac: DAC Channels
54 * @cir_asr: Clear Interrupts and ADC Status
55 * @acr: ADC Control
56 * @pccr_fsh: Pacer Clock Control and FIFO Status MSB
57 * @acfg: ADC Configuration
58 */
59 struct stx104_reg {
60 u16 ssr_ad;
61 u8 achan;
62 u8 dio;
63 u16 dac[2];
64 u8 cir_asr;
65 u8 acr;
66 u8 pccr_fsh;
67 u8 acfg;
68 };
69
70 /**
71 * struct stx104_iio - IIO device private data structure
72 * @chan_out_states: channels' output states
73 * @reg: I/O address offset for the device registers
74 */
75 struct stx104_iio {
76 unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
77 struct stx104_reg __iomem *reg;
78 };
79
80 /**
81 * struct stx104_gpio - GPIO device private data structure
82 * @chip: instance of the gpio_chip
83 * @lock: synchronization lock to prevent I/O race conditions
84 * @base: base port address of the GPIO device
85 * @out_state: output bits state
86 */
87 struct stx104_gpio {
88 struct gpio_chip chip;
89 spinlock_t lock;
90 u8 __iomem *base;
91 unsigned int out_state;
92 };
93
stx104_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)94 static int stx104_read_raw(struct iio_dev *indio_dev,
95 struct iio_chan_spec const *chan, int *val, int *val2, long mask)
96 {
97 struct stx104_iio *const priv = iio_priv(indio_dev);
98 struct stx104_reg __iomem *const reg = priv->reg;
99 unsigned int adc_config;
100 int adbu;
101 int gain;
102
103 switch (mask) {
104 case IIO_CHAN_INFO_HARDWAREGAIN:
105 /* get gain configuration */
106 adc_config = ioread8(®->acfg);
107 gain = adc_config & 0x3;
108
109 *val = 1 << gain;
110 return IIO_VAL_INT;
111 case IIO_CHAN_INFO_RAW:
112 if (chan->output) {
113 *val = priv->chan_out_states[chan->channel];
114 return IIO_VAL_INT;
115 }
116
117 /* select ADC channel */
118 iowrite8(chan->channel | (chan->channel << 4), ®->achan);
119
120 /* trigger ADC sample capture by writing to the 8-bit
121 * Software Strobe Register and wait for completion
122 */
123 iowrite8(0, ®->ssr_ad);
124 while (ioread8(®->cir_asr) & BIT(7));
125
126 *val = ioread16(®->ssr_ad);
127 return IIO_VAL_INT;
128 case IIO_CHAN_INFO_OFFSET:
129 /* get ADC bipolar/unipolar configuration */
130 adc_config = ioread8(®->acfg);
131 adbu = !(adc_config & BIT(2));
132
133 *val = -32768 * adbu;
134 return IIO_VAL_INT;
135 case IIO_CHAN_INFO_SCALE:
136 /* get ADC bipolar/unipolar and gain configuration */
137 adc_config = ioread8(®->acfg);
138 adbu = !(adc_config & BIT(2));
139 gain = adc_config & 0x3;
140
141 *val = 5;
142 *val2 = 15 - adbu + gain;
143 return IIO_VAL_FRACTIONAL_LOG2;
144 }
145
146 return -EINVAL;
147 }
148
stx104_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)149 static int stx104_write_raw(struct iio_dev *indio_dev,
150 struct iio_chan_spec const *chan, int val, int val2, long mask)
151 {
152 struct stx104_iio *const priv = iio_priv(indio_dev);
153
154 switch (mask) {
155 case IIO_CHAN_INFO_HARDWAREGAIN:
156 /* Only four gain states (x1, x2, x4, x8) */
157 switch (val) {
158 case 1:
159 iowrite8(0, &priv->reg->acfg);
160 break;
161 case 2:
162 iowrite8(1, &priv->reg->acfg);
163 break;
164 case 4:
165 iowrite8(2, &priv->reg->acfg);
166 break;
167 case 8:
168 iowrite8(3, &priv->reg->acfg);
169 break;
170 default:
171 return -EINVAL;
172 }
173
174 return 0;
175 case IIO_CHAN_INFO_RAW:
176 if (chan->output) {
177 /* DAC can only accept up to a 16-bit value */
178 if ((unsigned int)val > 65535)
179 return -EINVAL;
180
181 priv->chan_out_states[chan->channel] = val;
182 iowrite16(val, &priv->reg->dac[chan->channel]);
183
184 return 0;
185 }
186 return -EINVAL;
187 }
188
189 return -EINVAL;
190 }
191
192 static const struct iio_info stx104_info = {
193 .read_raw = stx104_read_raw,
194 .write_raw = stx104_write_raw
195 };
196
197 /* single-ended input channels configuration */
198 static const struct iio_chan_spec stx104_channels_sing[] = {
199 STX104_OUT_CHAN(0), STX104_OUT_CHAN(1),
200 STX104_IN_CHAN(0, 0), STX104_IN_CHAN(1, 0), STX104_IN_CHAN(2, 0),
201 STX104_IN_CHAN(3, 0), STX104_IN_CHAN(4, 0), STX104_IN_CHAN(5, 0),
202 STX104_IN_CHAN(6, 0), STX104_IN_CHAN(7, 0), STX104_IN_CHAN(8, 0),
203 STX104_IN_CHAN(9, 0), STX104_IN_CHAN(10, 0), STX104_IN_CHAN(11, 0),
204 STX104_IN_CHAN(12, 0), STX104_IN_CHAN(13, 0), STX104_IN_CHAN(14, 0),
205 STX104_IN_CHAN(15, 0)
206 };
207 /* differential input channels configuration */
208 static const struct iio_chan_spec stx104_channels_diff[] = {
209 STX104_OUT_CHAN(0), STX104_OUT_CHAN(1),
210 STX104_IN_CHAN(0, 1), STX104_IN_CHAN(1, 1), STX104_IN_CHAN(2, 1),
211 STX104_IN_CHAN(3, 1), STX104_IN_CHAN(4, 1), STX104_IN_CHAN(5, 1),
212 STX104_IN_CHAN(6, 1), STX104_IN_CHAN(7, 1)
213 };
214
stx104_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)215 static int stx104_gpio_get_direction(struct gpio_chip *chip,
216 unsigned int offset)
217 {
218 /* GPIO 0-3 are input only, while the rest are output only */
219 if (offset < 4)
220 return 1;
221
222 return 0;
223 }
224
stx104_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)225 static int stx104_gpio_direction_input(struct gpio_chip *chip,
226 unsigned int offset)
227 {
228 if (offset >= 4)
229 return -EINVAL;
230
231 return 0;
232 }
233
stx104_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)234 static int stx104_gpio_direction_output(struct gpio_chip *chip,
235 unsigned int offset, int value)
236 {
237 if (offset < 4)
238 return -EINVAL;
239
240 chip->set(chip, offset, value);
241 return 0;
242 }
243
stx104_gpio_get(struct gpio_chip * chip,unsigned int offset)244 static int stx104_gpio_get(struct gpio_chip *chip, unsigned int offset)
245 {
246 struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
247
248 if (offset >= 4)
249 return -EINVAL;
250
251 return !!(ioread8(stx104gpio->base) & BIT(offset));
252 }
253
stx104_gpio_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)254 static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
255 unsigned long *bits)
256 {
257 struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
258
259 *bits = ioread8(stx104gpio->base);
260
261 return 0;
262 }
263
stx104_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)264 static void stx104_gpio_set(struct gpio_chip *chip, unsigned int offset,
265 int value)
266 {
267 struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
268 const unsigned int mask = BIT(offset) >> 4;
269 unsigned long flags;
270
271 if (offset < 4)
272 return;
273
274 spin_lock_irqsave(&stx104gpio->lock, flags);
275
276 if (value)
277 stx104gpio->out_state |= mask;
278 else
279 stx104gpio->out_state &= ~mask;
280
281 iowrite8(stx104gpio->out_state, stx104gpio->base);
282
283 spin_unlock_irqrestore(&stx104gpio->lock, flags);
284 }
285
286 #define STX104_NGPIO 8
287 static const char *stx104_names[STX104_NGPIO] = {
288 "DIN0", "DIN1", "DIN2", "DIN3", "DOUT0", "DOUT1", "DOUT2", "DOUT3"
289 };
290
stx104_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)291 static void stx104_gpio_set_multiple(struct gpio_chip *chip,
292 unsigned long *mask, unsigned long *bits)
293 {
294 struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip);
295 unsigned long flags;
296
297 /* verify masked GPIO are output */
298 if (!(*mask & 0xF0))
299 return;
300
301 *mask >>= 4;
302 *bits >>= 4;
303
304 spin_lock_irqsave(&stx104gpio->lock, flags);
305
306 stx104gpio->out_state &= ~*mask;
307 stx104gpio->out_state |= *mask & *bits;
308 iowrite8(stx104gpio->out_state, stx104gpio->base);
309
310 spin_unlock_irqrestore(&stx104gpio->lock, flags);
311 }
312
stx104_probe(struct device * dev,unsigned int id)313 static int stx104_probe(struct device *dev, unsigned int id)
314 {
315 struct iio_dev *indio_dev;
316 struct stx104_iio *priv;
317 struct stx104_gpio *stx104gpio;
318 int err;
319
320 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
321 if (!indio_dev)
322 return -ENOMEM;
323
324 stx104gpio = devm_kzalloc(dev, sizeof(*stx104gpio), GFP_KERNEL);
325 if (!stx104gpio)
326 return -ENOMEM;
327
328 if (!devm_request_region(dev, base[id], STX104_EXTENT,
329 dev_name(dev))) {
330 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
331 base[id], base[id] + STX104_EXTENT);
332 return -EBUSY;
333 }
334
335 priv = iio_priv(indio_dev);
336 priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT);
337 if (!priv->reg)
338 return -ENOMEM;
339
340 indio_dev->info = &stx104_info;
341 indio_dev->modes = INDIO_DIRECT_MODE;
342
343 /* determine if differential inputs */
344 if (ioread8(&priv->reg->cir_asr) & BIT(5)) {
345 indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff);
346 indio_dev->channels = stx104_channels_diff;
347 } else {
348 indio_dev->num_channels = ARRAY_SIZE(stx104_channels_sing);
349 indio_dev->channels = stx104_channels_sing;
350 }
351
352 indio_dev->name = dev_name(dev);
353
354 /* configure device for software trigger operation */
355 iowrite8(0, &priv->reg->acr);
356
357 /* initialize gain setting to x1 */
358 iowrite8(0, &priv->reg->acfg);
359
360 /* initialize DAC output to 0V */
361 iowrite16(0, &priv->reg->dac[0]);
362 iowrite16(0, &priv->reg->dac[1]);
363
364 stx104gpio->chip.label = dev_name(dev);
365 stx104gpio->chip.parent = dev;
366 stx104gpio->chip.owner = THIS_MODULE;
367 stx104gpio->chip.base = -1;
368 stx104gpio->chip.ngpio = STX104_NGPIO;
369 stx104gpio->chip.names = stx104_names;
370 stx104gpio->chip.get_direction = stx104_gpio_get_direction;
371 stx104gpio->chip.direction_input = stx104_gpio_direction_input;
372 stx104gpio->chip.direction_output = stx104_gpio_direction_output;
373 stx104gpio->chip.get = stx104_gpio_get;
374 stx104gpio->chip.get_multiple = stx104_gpio_get_multiple;
375 stx104gpio->chip.set = stx104_gpio_set;
376 stx104gpio->chip.set_multiple = stx104_gpio_set_multiple;
377 stx104gpio->base = &priv->reg->dio;
378 stx104gpio->out_state = 0x0;
379
380 spin_lock_init(&stx104gpio->lock);
381
382 err = devm_gpiochip_add_data(dev, &stx104gpio->chip, stx104gpio);
383 if (err) {
384 dev_err(dev, "GPIO registering failed (%d)\n", err);
385 return err;
386 }
387
388 return devm_iio_device_register(dev, indio_dev);
389 }
390
391 static struct isa_driver stx104_driver = {
392 .probe = stx104_probe,
393 .driver = {
394 .name = "stx104"
395 },
396 };
397
398 module_isa_driver(stx104_driver, num_stx104);
399
400 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
401 MODULE_DESCRIPTION("Apex Embedded Systems STX104 IIO driver");
402 MODULE_LICENSE("GPL v2");
403