1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Freescale i.MX7D ADC driver
4 *
5 * Copyright (C) 2015 Freescale Semiconductor, Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/completion.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/regulator/consumer.h>
18
19 #include <linux/iio/iio.h>
20 #include <linux/iio/driver.h>
21 #include <linux/iio/sysfs.h>
22
23 /* ADC register */
24 #define IMX7D_REG_ADC_CH_A_CFG1 0x00
25 #define IMX7D_REG_ADC_CH_A_CFG2 0x10
26 #define IMX7D_REG_ADC_CH_B_CFG1 0x20
27 #define IMX7D_REG_ADC_CH_B_CFG2 0x30
28 #define IMX7D_REG_ADC_CH_C_CFG1 0x40
29 #define IMX7D_REG_ADC_CH_C_CFG2 0x50
30 #define IMX7D_REG_ADC_CH_D_CFG1 0x60
31 #define IMX7D_REG_ADC_CH_D_CFG2 0x70
32 #define IMX7D_REG_ADC_CH_SW_CFG 0x80
33 #define IMX7D_REG_ADC_TIMER_UNIT 0x90
34 #define IMX7D_REG_ADC_DMA_FIFO 0xa0
35 #define IMX7D_REG_ADC_FIFO_STATUS 0xb0
36 #define IMX7D_REG_ADC_INT_SIG_EN 0xc0
37 #define IMX7D_REG_ADC_INT_EN 0xd0
38 #define IMX7D_REG_ADC_INT_STATUS 0xe0
39 #define IMX7D_REG_ADC_CHA_B_CNV_RSLT 0xf0
40 #define IMX7D_REG_ADC_CHC_D_CNV_RSLT 0x100
41 #define IMX7D_REG_ADC_CH_SW_CNV_RSLT 0x110
42 #define IMX7D_REG_ADC_DMA_FIFO_DAT 0x120
43 #define IMX7D_REG_ADC_ADC_CFG 0x130
44
45 #define IMX7D_REG_ADC_CHANNEL_CFG2_BASE 0x10
46 #define IMX7D_EACH_CHANNEL_REG_OFFSET 0x20
47
48 #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN (0x1 << 31)
49 #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE BIT(30)
50 #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN BIT(29)
51 #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(x) ((x) << 24)
52
53 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4 (0x0 << 12)
54 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8 (0x1 << 12)
55 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16 (0x2 << 12)
56 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32 (0x3 << 12)
57
58 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4 (0x0 << 29)
59 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8 (0x1 << 29)
60 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16 (0x2 << 29)
61 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32 (0x3 << 29)
62 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64 (0x4 << 29)
63 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128 (0x5 << 29)
64
65 #define IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN BIT(31)
66 #define IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN BIT(1)
67 #define IMX7D_REG_ADC_ADC_CFG_ADC_EN BIT(0)
68
69 #define IMX7D_REG_ADC_INT_CHA_COV_INT_EN BIT(8)
70 #define IMX7D_REG_ADC_INT_CHB_COV_INT_EN BIT(9)
71 #define IMX7D_REG_ADC_INT_CHC_COV_INT_EN BIT(10)
72 #define IMX7D_REG_ADC_INT_CHD_COV_INT_EN BIT(11)
73 #define IMX7D_REG_ADC_INT_CHANNEL_INT_EN \
74 (IMX7D_REG_ADC_INT_CHA_COV_INT_EN | \
75 IMX7D_REG_ADC_INT_CHB_COV_INT_EN | \
76 IMX7D_REG_ADC_INT_CHC_COV_INT_EN | \
77 IMX7D_REG_ADC_INT_CHD_COV_INT_EN)
78 #define IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS 0xf00
79 #define IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT 0xf0000
80
81 #define IMX7D_ADC_TIMEOUT msecs_to_jiffies(100)
82 #define IMX7D_ADC_INPUT_CLK 24000000
83
84 enum imx7d_adc_clk_pre_div {
85 IMX7D_ADC_ANALOG_CLK_PRE_DIV_4,
86 IMX7D_ADC_ANALOG_CLK_PRE_DIV_8,
87 IMX7D_ADC_ANALOG_CLK_PRE_DIV_16,
88 IMX7D_ADC_ANALOG_CLK_PRE_DIV_32,
89 IMX7D_ADC_ANALOG_CLK_PRE_DIV_64,
90 IMX7D_ADC_ANALOG_CLK_PRE_DIV_128,
91 };
92
93 enum imx7d_adc_average_num {
94 IMX7D_ADC_AVERAGE_NUM_4,
95 IMX7D_ADC_AVERAGE_NUM_8,
96 IMX7D_ADC_AVERAGE_NUM_16,
97 IMX7D_ADC_AVERAGE_NUM_32,
98 };
99
100 struct imx7d_adc_feature {
101 enum imx7d_adc_clk_pre_div clk_pre_div;
102 enum imx7d_adc_average_num avg_num;
103
104 u32 core_time_unit; /* impact the sample rate */
105 };
106
107 struct imx7d_adc {
108 struct device *dev;
109 void __iomem *regs;
110 struct clk *clk;
111
112 u32 vref_uv;
113 u32 value;
114 u32 channel;
115 u32 pre_div_num;
116
117 struct regulator *vref;
118 struct imx7d_adc_feature adc_feature;
119
120 struct completion completion;
121 };
122
123 struct imx7d_adc_analogue_core_clk {
124 u32 pre_div;
125 u32 reg_config;
126 };
127
128 #define IMX7D_ADC_ANALOGUE_CLK_CONFIG(_pre_div, _reg_conf) { \
129 .pre_div = (_pre_div), \
130 .reg_config = (_reg_conf), \
131 }
132
133 static const struct imx7d_adc_analogue_core_clk imx7d_adc_analogue_clk[] = {
134 IMX7D_ADC_ANALOGUE_CLK_CONFIG(4, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4),
135 IMX7D_ADC_ANALOGUE_CLK_CONFIG(8, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8),
136 IMX7D_ADC_ANALOGUE_CLK_CONFIG(16, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16),
137 IMX7D_ADC_ANALOGUE_CLK_CONFIG(32, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32),
138 IMX7D_ADC_ANALOGUE_CLK_CONFIG(64, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64),
139 IMX7D_ADC_ANALOGUE_CLK_CONFIG(128, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128),
140 };
141
142 #define IMX7D_ADC_CHAN(_idx) { \
143 .type = IIO_VOLTAGE, \
144 .indexed = 1, \
145 .channel = (_idx), \
146 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
147 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
148 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
149 }
150
151 static const struct iio_chan_spec imx7d_adc_iio_channels[] = {
152 IMX7D_ADC_CHAN(0),
153 IMX7D_ADC_CHAN(1),
154 IMX7D_ADC_CHAN(2),
155 IMX7D_ADC_CHAN(3),
156 IMX7D_ADC_CHAN(4),
157 IMX7D_ADC_CHAN(5),
158 IMX7D_ADC_CHAN(6),
159 IMX7D_ADC_CHAN(7),
160 IMX7D_ADC_CHAN(8),
161 IMX7D_ADC_CHAN(9),
162 IMX7D_ADC_CHAN(10),
163 IMX7D_ADC_CHAN(11),
164 IMX7D_ADC_CHAN(12),
165 IMX7D_ADC_CHAN(13),
166 IMX7D_ADC_CHAN(14),
167 IMX7D_ADC_CHAN(15),
168 };
169
170 static const u32 imx7d_adc_average_num[] = {
171 IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4,
172 IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8,
173 IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16,
174 IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32,
175 };
176
imx7d_adc_feature_config(struct imx7d_adc * info)177 static void imx7d_adc_feature_config(struct imx7d_adc *info)
178 {
179 info->adc_feature.clk_pre_div = IMX7D_ADC_ANALOG_CLK_PRE_DIV_4;
180 info->adc_feature.avg_num = IMX7D_ADC_AVERAGE_NUM_32;
181 info->adc_feature.core_time_unit = 1;
182 }
183
imx7d_adc_sample_rate_set(struct imx7d_adc * info)184 static void imx7d_adc_sample_rate_set(struct imx7d_adc *info)
185 {
186 struct imx7d_adc_feature *adc_feature = &info->adc_feature;
187 struct imx7d_adc_analogue_core_clk adc_analogure_clk;
188 u32 i;
189 u32 tmp_cfg1;
190 u32 sample_rate = 0;
191
192 /*
193 * Before sample set, disable channel A,B,C,D. Here we
194 * clear the bit 31 of register REG_ADC_CH_A\B\C\D_CFG1.
195 */
196 for (i = 0; i < 4; i++) {
197 tmp_cfg1 =
198 readl(info->regs + i * IMX7D_EACH_CHANNEL_REG_OFFSET);
199 tmp_cfg1 &= ~IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN;
200 writel(tmp_cfg1,
201 info->regs + i * IMX7D_EACH_CHANNEL_REG_OFFSET);
202 }
203
204 adc_analogure_clk = imx7d_adc_analogue_clk[adc_feature->clk_pre_div];
205 sample_rate |= adc_analogure_clk.reg_config;
206 info->pre_div_num = adc_analogure_clk.pre_div;
207
208 sample_rate |= adc_feature->core_time_unit;
209 writel(sample_rate, info->regs + IMX7D_REG_ADC_TIMER_UNIT);
210 }
211
imx7d_adc_hw_init(struct imx7d_adc * info)212 static void imx7d_adc_hw_init(struct imx7d_adc *info)
213 {
214 u32 cfg;
215
216 /* power up and enable adc analogue core */
217 cfg = readl(info->regs + IMX7D_REG_ADC_ADC_CFG);
218 cfg &= ~(IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN |
219 IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN);
220 cfg |= IMX7D_REG_ADC_ADC_CFG_ADC_EN;
221 writel(cfg, info->regs + IMX7D_REG_ADC_ADC_CFG);
222
223 /* enable channel A,B,C,D interrupt */
224 writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN,
225 info->regs + IMX7D_REG_ADC_INT_SIG_EN);
226 writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN,
227 info->regs + IMX7D_REG_ADC_INT_EN);
228
229 imx7d_adc_sample_rate_set(info);
230 }
231
imx7d_adc_channel_set(struct imx7d_adc * info)232 static void imx7d_adc_channel_set(struct imx7d_adc *info)
233 {
234 u32 cfg1 = 0;
235 u32 cfg2;
236 u32 channel;
237
238 channel = info->channel;
239
240 /* the channel choose single conversion, and enable average mode */
241 cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN |
242 IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE |
243 IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN);
244
245 /*
246 * physical channel 0 chose logical channel A
247 * physical channel 1 chose logical channel B
248 * physical channel 2 chose logical channel C
249 * physical channel 3 chose logical channel D
250 */
251 cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel);
252
253 /*
254 * read register REG_ADC_CH_A\B\C\D_CFG2, according to the
255 * channel chosen
256 */
257 cfg2 = readl(info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
258 IMX7D_REG_ADC_CHANNEL_CFG2_BASE);
259
260 cfg2 |= imx7d_adc_average_num[info->adc_feature.avg_num];
261
262 /*
263 * write the register REG_ADC_CH_A\B\C\D_CFG2, according to
264 * the channel chosen
265 */
266 writel(cfg2, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
267 IMX7D_REG_ADC_CHANNEL_CFG2_BASE);
268 writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel);
269 }
270
imx7d_adc_get_sample_rate(struct imx7d_adc * info)271 static u32 imx7d_adc_get_sample_rate(struct imx7d_adc *info)
272 {
273 u32 analogue_core_clk;
274 u32 core_time_unit = info->adc_feature.core_time_unit;
275 u32 tmp;
276
277 analogue_core_clk = IMX7D_ADC_INPUT_CLK / info->pre_div_num;
278 tmp = (core_time_unit + 1) * 6;
279
280 return analogue_core_clk / tmp;
281 }
282
imx7d_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)283 static int imx7d_adc_read_raw(struct iio_dev *indio_dev,
284 struct iio_chan_spec const *chan,
285 int *val,
286 int *val2,
287 long mask)
288 {
289 struct imx7d_adc *info = iio_priv(indio_dev);
290
291 u32 channel;
292 long ret;
293
294 switch (mask) {
295 case IIO_CHAN_INFO_RAW:
296 mutex_lock(&indio_dev->mlock);
297 reinit_completion(&info->completion);
298
299 channel = chan->channel & 0x03;
300 info->channel = channel;
301 imx7d_adc_channel_set(info);
302
303 ret = wait_for_completion_interruptible_timeout
304 (&info->completion, IMX7D_ADC_TIMEOUT);
305 if (ret == 0) {
306 mutex_unlock(&indio_dev->mlock);
307 return -ETIMEDOUT;
308 }
309 if (ret < 0) {
310 mutex_unlock(&indio_dev->mlock);
311 return ret;
312 }
313
314 *val = info->value;
315 mutex_unlock(&indio_dev->mlock);
316 return IIO_VAL_INT;
317
318 case IIO_CHAN_INFO_SCALE:
319 info->vref_uv = regulator_get_voltage(info->vref);
320 *val = info->vref_uv / 1000;
321 *val2 = 12;
322 return IIO_VAL_FRACTIONAL_LOG2;
323
324 case IIO_CHAN_INFO_SAMP_FREQ:
325 *val = imx7d_adc_get_sample_rate(info);
326 return IIO_VAL_INT;
327
328 default:
329 return -EINVAL;
330 }
331 }
332
imx7d_adc_read_data(struct imx7d_adc * info)333 static int imx7d_adc_read_data(struct imx7d_adc *info)
334 {
335 u32 channel;
336 u32 value;
337
338 channel = info->channel & 0x03;
339
340 /*
341 * channel A and B conversion result share one register,
342 * bit[27~16] is the channel B conversion result,
343 * bit[11~0] is the channel A conversion result.
344 * channel C and D is the same.
345 */
346 if (channel < 2)
347 value = readl(info->regs + IMX7D_REG_ADC_CHA_B_CNV_RSLT);
348 else
349 value = readl(info->regs + IMX7D_REG_ADC_CHC_D_CNV_RSLT);
350 if (channel & 0x1) /* channel B or D */
351 value = (value >> 16) & 0xFFF;
352 else /* channel A or C */
353 value &= 0xFFF;
354
355 return value;
356 }
357
imx7d_adc_isr(int irq,void * dev_id)358 static irqreturn_t imx7d_adc_isr(int irq, void *dev_id)
359 {
360 struct imx7d_adc *info = dev_id;
361 int status;
362
363 status = readl(info->regs + IMX7D_REG_ADC_INT_STATUS);
364 if (status & IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS) {
365 info->value = imx7d_adc_read_data(info);
366 complete(&info->completion);
367
368 /*
369 * The register IMX7D_REG_ADC_INT_STATUS can't clear
370 * itself after read operation, need software to write
371 * 0 to the related bit. Here we clear the channel A/B/C/D
372 * conversion finished flag.
373 */
374 status &= ~IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS;
375 writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS);
376 }
377
378 /*
379 * If the channel A/B/C/D conversion timeout, report it and clear these
380 * timeout flags.
381 */
382 if (status & IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT) {
383 dev_err(info->dev,
384 "ADC got conversion time out interrupt: 0x%08x\n",
385 status);
386 status &= ~IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT;
387 writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS);
388 }
389
390 return IRQ_HANDLED;
391 }
392
imx7d_adc_reg_access(struct iio_dev * indio_dev,unsigned reg,unsigned writeval,unsigned * readval)393 static int imx7d_adc_reg_access(struct iio_dev *indio_dev,
394 unsigned reg, unsigned writeval,
395 unsigned *readval)
396 {
397 struct imx7d_adc *info = iio_priv(indio_dev);
398
399 if (!readval || reg % 4 || reg > IMX7D_REG_ADC_ADC_CFG)
400 return -EINVAL;
401
402 *readval = readl(info->regs + reg);
403
404 return 0;
405 }
406
407 static const struct iio_info imx7d_adc_iio_info = {
408 .read_raw = &imx7d_adc_read_raw,
409 .debugfs_reg_access = &imx7d_adc_reg_access,
410 };
411
412 static const struct of_device_id imx7d_adc_match[] = {
413 { .compatible = "fsl,imx7d-adc", },
414 { /* sentinel */ }
415 };
416 MODULE_DEVICE_TABLE(of, imx7d_adc_match);
417
imx7d_adc_power_down(struct imx7d_adc * info)418 static void imx7d_adc_power_down(struct imx7d_adc *info)
419 {
420 u32 adc_cfg;
421
422 adc_cfg = readl(info->regs + IMX7D_REG_ADC_ADC_CFG);
423 adc_cfg |= IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN |
424 IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN;
425 adc_cfg &= ~IMX7D_REG_ADC_ADC_CFG_ADC_EN;
426 writel(adc_cfg, info->regs + IMX7D_REG_ADC_ADC_CFG);
427 }
428
imx7d_adc_enable(struct device * dev)429 static int imx7d_adc_enable(struct device *dev)
430 {
431 struct iio_dev *indio_dev = dev_get_drvdata(dev);
432 struct imx7d_adc *info = iio_priv(indio_dev);
433 int ret;
434
435 ret = regulator_enable(info->vref);
436 if (ret) {
437 dev_err(info->dev,
438 "Can't enable adc reference top voltage, err = %d\n",
439 ret);
440 return ret;
441 }
442
443 ret = clk_prepare_enable(info->clk);
444 if (ret) {
445 dev_err(info->dev,
446 "Could not prepare or enable clock.\n");
447 regulator_disable(info->vref);
448 return ret;
449 }
450
451 imx7d_adc_hw_init(info);
452
453 return 0;
454 }
455
imx7d_adc_disable(struct device * dev)456 static int imx7d_adc_disable(struct device *dev)
457 {
458 struct iio_dev *indio_dev = dev_get_drvdata(dev);
459 struct imx7d_adc *info = iio_priv(indio_dev);
460
461 imx7d_adc_power_down(info);
462
463 clk_disable_unprepare(info->clk);
464 regulator_disable(info->vref);
465
466 return 0;
467 }
468
__imx7d_adc_disable(void * data)469 static void __imx7d_adc_disable(void *data)
470 {
471 imx7d_adc_disable(data);
472 }
473
imx7d_adc_probe(struct platform_device * pdev)474 static int imx7d_adc_probe(struct platform_device *pdev)
475 {
476 struct imx7d_adc *info;
477 struct iio_dev *indio_dev;
478 struct device *dev = &pdev->dev;
479 int irq;
480 int ret;
481
482 indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
483 if (!indio_dev) {
484 dev_err(&pdev->dev, "Failed allocating iio device\n");
485 return -ENOMEM;
486 }
487
488 info = iio_priv(indio_dev);
489 info->dev = dev;
490
491 info->regs = devm_platform_ioremap_resource(pdev, 0);
492 if (IS_ERR(info->regs))
493 return PTR_ERR(info->regs);
494
495 irq = platform_get_irq(pdev, 0);
496 if (irq < 0)
497 return dev_err_probe(dev, irq, "Failed getting irq\n");
498
499 info->clk = devm_clk_get(dev, "adc");
500 if (IS_ERR(info->clk))
501 return dev_err_probe(dev, PTR_ERR(info->clk), "Failed getting clock\n");
502
503 info->vref = devm_regulator_get(dev, "vref");
504 if (IS_ERR(info->vref))
505 return dev_err_probe(dev, PTR_ERR(info->vref),
506 "Failed getting reference voltage\n");
507
508 platform_set_drvdata(pdev, indio_dev);
509
510 init_completion(&info->completion);
511
512 indio_dev->name = dev_name(dev);
513 indio_dev->info = &imx7d_adc_iio_info;
514 indio_dev->modes = INDIO_DIRECT_MODE;
515 indio_dev->channels = imx7d_adc_iio_channels;
516 indio_dev->num_channels = ARRAY_SIZE(imx7d_adc_iio_channels);
517
518 ret = devm_request_irq(dev, irq, imx7d_adc_isr, 0, dev_name(dev), info);
519 if (ret < 0) {
520 dev_err(dev, "Failed requesting irq, irq = %d\n", irq);
521 return ret;
522 }
523
524 imx7d_adc_feature_config(info);
525
526 ret = imx7d_adc_enable(dev);
527 if (ret)
528 return ret;
529
530 ret = devm_add_action_or_reset(dev, __imx7d_adc_disable, dev);
531 if (ret)
532 return ret;
533
534 ret = devm_iio_device_register(dev, indio_dev);
535 if (ret) {
536 dev_err(&pdev->dev, "Couldn't register the device.\n");
537 return ret;
538 }
539
540 return 0;
541 }
542
543 static DEFINE_SIMPLE_DEV_PM_OPS(imx7d_adc_pm_ops, imx7d_adc_disable,
544 imx7d_adc_enable);
545
546 static struct platform_driver imx7d_adc_driver = {
547 .probe = imx7d_adc_probe,
548 .driver = {
549 .name = "imx7d_adc",
550 .of_match_table = imx7d_adc_match,
551 .pm = pm_sleep_ptr(&imx7d_adc_pm_ops),
552 },
553 };
554
555 module_platform_driver(imx7d_adc_driver);
556
557 MODULE_AUTHOR("Haibo Chen <haibo.chen@freescale.com>");
558 MODULE_DESCRIPTION("Freescale IMX7D ADC driver");
559 MODULE_LICENSE("GPL v2");
560