1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2016 Broadcom
4  */
5 
6 /**
7  * DOC: VC4 DSI0/DSI1 module
8  *
9  * BCM2835 contains two DSI modules, DSI0 and DSI1.  DSI0 is a
10  * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
11  * controller.
12  *
13  * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
14  * while the compute module brings both DSI0 and DSI1 out.
15  *
16  * This driver has been tested for DSI1 video-mode display only
17  * currently, with most of the information necessary for DSI0
18  * hopefully present.
19  */
20 
21 #include <linux/clk-provider.h>
22 #include <linux/clk.h>
23 #include <linux/completion.h>
24 #include <linux/component.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/dmaengine.h>
27 #include <linux/i2c.h>
28 #include <linux/io.h>
29 #include <linux/of_address.h>
30 #include <linux/of_platform.h>
31 #include <linux/pm_runtime.h>
32 
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_bridge.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_mipi_dsi.h>
37 #include <drm/drm_of.h>
38 #include <drm/drm_panel.h>
39 #include <drm/drm_probe_helper.h>
40 #include <drm/drm_simple_kms_helper.h>
41 
42 #include "vc4_drv.h"
43 #include "vc4_regs.h"
44 
45 #define DSI_CMD_FIFO_DEPTH  16
46 #define DSI_PIX_FIFO_DEPTH 256
47 #define DSI_PIX_FIFO_WIDTH   4
48 
49 #define DSI0_CTRL		0x00
50 
51 /* Command packet control. */
52 #define DSI0_TXPKT1C		0x04 /* AKA PKTC */
53 #define DSI1_TXPKT1C		0x04
54 # define DSI_TXPKT1C_TRIG_CMD_MASK	VC4_MASK(31, 24)
55 # define DSI_TXPKT1C_TRIG_CMD_SHIFT	24
56 # define DSI_TXPKT1C_CMD_REPEAT_MASK	VC4_MASK(23, 10)
57 # define DSI_TXPKT1C_CMD_REPEAT_SHIFT	10
58 
59 # define DSI_TXPKT1C_DISPLAY_NO_MASK	VC4_MASK(9, 8)
60 # define DSI_TXPKT1C_DISPLAY_NO_SHIFT	8
61 /* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
62 # define DSI_TXPKT1C_DISPLAY_NO_SHORT		0
63 /* Primary display where cmdfifo provides part of the payload and
64  * pixelvalve the rest.
65  */
66 # define DSI_TXPKT1C_DISPLAY_NO_PRIMARY		1
67 /* Secondary display where cmdfifo provides part of the payload and
68  * pixfifo the rest.
69  */
70 # define DSI_TXPKT1C_DISPLAY_NO_SECONDARY	2
71 
72 # define DSI_TXPKT1C_CMD_TX_TIME_MASK	VC4_MASK(7, 6)
73 # define DSI_TXPKT1C_CMD_TX_TIME_SHIFT	6
74 
75 # define DSI_TXPKT1C_CMD_CTRL_MASK	VC4_MASK(5, 4)
76 # define DSI_TXPKT1C_CMD_CTRL_SHIFT	4
77 /* Command only.  Uses TXPKT1H and DISPLAY_NO */
78 # define DSI_TXPKT1C_CMD_CTRL_TX	0
79 /* Command with BTA for either ack or read data. */
80 # define DSI_TXPKT1C_CMD_CTRL_RX	1
81 /* Trigger according to TRIG_CMD */
82 # define DSI_TXPKT1C_CMD_CTRL_TRIG	2
83 /* BTA alone for getting error status after a command, or a TE trigger
84  * without a previous command.
85  */
86 # define DSI_TXPKT1C_CMD_CTRL_BTA	3
87 
88 # define DSI_TXPKT1C_CMD_MODE_LP	BIT(3)
89 # define DSI_TXPKT1C_CMD_TYPE_LONG	BIT(2)
90 # define DSI_TXPKT1C_CMD_TE_EN		BIT(1)
91 # define DSI_TXPKT1C_CMD_EN		BIT(0)
92 
93 /* Command packet header. */
94 #define DSI0_TXPKT1H		0x08 /* AKA PKTH */
95 #define DSI1_TXPKT1H		0x08
96 # define DSI_TXPKT1H_BC_CMDFIFO_MASK	VC4_MASK(31, 24)
97 # define DSI_TXPKT1H_BC_CMDFIFO_SHIFT	24
98 # define DSI_TXPKT1H_BC_PARAM_MASK	VC4_MASK(23, 8)
99 # define DSI_TXPKT1H_BC_PARAM_SHIFT	8
100 # define DSI_TXPKT1H_BC_DT_MASK		VC4_MASK(7, 0)
101 # define DSI_TXPKT1H_BC_DT_SHIFT	0
102 
103 #define DSI0_RXPKT1H		0x0c /* AKA RX1_PKTH */
104 #define DSI1_RXPKT1H		0x14
105 # define DSI_RXPKT1H_CRC_ERR		BIT(31)
106 # define DSI_RXPKT1H_DET_ERR		BIT(30)
107 # define DSI_RXPKT1H_ECC_ERR		BIT(29)
108 # define DSI_RXPKT1H_COR_ERR		BIT(28)
109 # define DSI_RXPKT1H_INCOMP_PKT		BIT(25)
110 # define DSI_RXPKT1H_PKT_TYPE_LONG	BIT(24)
111 /* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
112 # define DSI_RXPKT1H_BC_PARAM_MASK	VC4_MASK(23, 8)
113 # define DSI_RXPKT1H_BC_PARAM_SHIFT	8
114 /* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
115 # define DSI_RXPKT1H_SHORT_1_MASK	VC4_MASK(23, 16)
116 # define DSI_RXPKT1H_SHORT_1_SHIFT	16
117 # define DSI_RXPKT1H_SHORT_0_MASK	VC4_MASK(15, 8)
118 # define DSI_RXPKT1H_SHORT_0_SHIFT	8
119 # define DSI_RXPKT1H_DT_LP_CMD_MASK	VC4_MASK(7, 0)
120 # define DSI_RXPKT1H_DT_LP_CMD_SHIFT	0
121 
122 #define DSI0_RXPKT2H		0x10 /* AKA RX2_PKTH */
123 #define DSI1_RXPKT2H		0x18
124 # define DSI_RXPKT1H_DET_ERR		BIT(30)
125 # define DSI_RXPKT1H_ECC_ERR		BIT(29)
126 # define DSI_RXPKT1H_COR_ERR		BIT(28)
127 # define DSI_RXPKT1H_INCOMP_PKT		BIT(25)
128 # define DSI_RXPKT1H_BC_PARAM_MASK	VC4_MASK(23, 8)
129 # define DSI_RXPKT1H_BC_PARAM_SHIFT	8
130 # define DSI_RXPKT1H_DT_MASK		VC4_MASK(7, 0)
131 # define DSI_RXPKT1H_DT_SHIFT		0
132 
133 #define DSI0_TXPKT_CMD_FIFO	0x14 /* AKA CMD_DATAF */
134 #define DSI1_TXPKT_CMD_FIFO	0x1c
135 
136 #define DSI0_DISP0_CTRL		0x18
137 # define DSI_DISP0_PIX_CLK_DIV_MASK	VC4_MASK(21, 13)
138 # define DSI_DISP0_PIX_CLK_DIV_SHIFT	13
139 # define DSI_DISP0_LP_STOP_CTRL_MASK	VC4_MASK(12, 11)
140 # define DSI_DISP0_LP_STOP_CTRL_SHIFT	11
141 # define DSI_DISP0_LP_STOP_DISABLE	0
142 # define DSI_DISP0_LP_STOP_PERLINE	1
143 # define DSI_DISP0_LP_STOP_PERFRAME	2
144 
145 /* Transmit RGB pixels and null packets only during HACTIVE, instead
146  * of going to LP-STOP.
147  */
148 # define DSI_DISP_HACTIVE_NULL		BIT(10)
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
150 # define DSI_DISP_VBLP_CTRL		BIT(9)
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
152 # define DSI_DISP_HFP_CTRL		BIT(8)
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
154 # define DSI_DISP_HBP_CTRL		BIT(7)
155 # define DSI_DISP0_CHANNEL_MASK		VC4_MASK(6, 5)
156 # define DSI_DISP0_CHANNEL_SHIFT	5
157 /* Enables end events for HSYNC/VSYNC, not just start events. */
158 # define DSI_DISP0_ST_END		BIT(4)
159 # define DSI_DISP0_PFORMAT_MASK		VC4_MASK(3, 2)
160 # define DSI_DISP0_PFORMAT_SHIFT	2
161 # define DSI_PFORMAT_RGB565		0
162 # define DSI_PFORMAT_RGB666_PACKED	1
163 # define DSI_PFORMAT_RGB666		2
164 # define DSI_PFORMAT_RGB888		3
165 /* Default is VIDEO mode. */
166 # define DSI_DISP0_COMMAND_MODE		BIT(1)
167 # define DSI_DISP0_ENABLE		BIT(0)
168 
169 #define DSI0_DISP1_CTRL		0x1c
170 #define DSI1_DISP1_CTRL		0x2c
171 /* Format of the data written to TXPKT_PIX_FIFO. */
172 # define DSI_DISP1_PFORMAT_MASK		VC4_MASK(2, 1)
173 # define DSI_DISP1_PFORMAT_SHIFT	1
174 # define DSI_DISP1_PFORMAT_16BIT	0
175 # define DSI_DISP1_PFORMAT_24BIT	1
176 # define DSI_DISP1_PFORMAT_32BIT_LE	2
177 # define DSI_DISP1_PFORMAT_32BIT_BE	3
178 
179 /* DISP1 is always command mode. */
180 # define DSI_DISP1_ENABLE		BIT(0)
181 
182 #define DSI0_TXPKT_PIX_FIFO		0x20 /* AKA PIX_FIFO */
183 
184 #define DSI0_INT_STAT			0x24
185 #define DSI0_INT_EN			0x28
186 # define DSI0_INT_FIFO_ERR		BIT(25)
187 # define DSI0_INT_CMDC_DONE_MASK	VC4_MASK(24, 23)
188 # define DSI0_INT_CMDC_DONE_SHIFT	23
189 #  define DSI0_INT_CMDC_DONE_NO_REPEAT		1
190 #  define DSI0_INT_CMDC_DONE_REPEAT		3
191 # define DSI0_INT_PHY_DIR_RTF		BIT(22)
192 # define DSI0_INT_PHY_D1_ULPS		BIT(21)
193 # define DSI0_INT_PHY_D1_STOP		BIT(20)
194 # define DSI0_INT_PHY_RXLPDT		BIT(19)
195 # define DSI0_INT_PHY_RXTRIG		BIT(18)
196 # define DSI0_INT_PHY_D0_ULPS		BIT(17)
197 # define DSI0_INT_PHY_D0_LPDT		BIT(16)
198 # define DSI0_INT_PHY_D0_FTR		BIT(15)
199 # define DSI0_INT_PHY_D0_STOP		BIT(14)
200 /* Signaled when the clock lane enters the given state. */
201 # define DSI0_INT_PHY_CLK_ULPS		BIT(13)
202 # define DSI0_INT_PHY_CLK_HS		BIT(12)
203 # define DSI0_INT_PHY_CLK_FTR		BIT(11)
204 /* Signaled on timeouts */
205 # define DSI0_INT_PR_TO			BIT(10)
206 # define DSI0_INT_TA_TO			BIT(9)
207 # define DSI0_INT_LPRX_TO		BIT(8)
208 # define DSI0_INT_HSTX_TO		BIT(7)
209 /* Contention on a line when trying to drive the line low */
210 # define DSI0_INT_ERR_CONT_LP1		BIT(6)
211 # define DSI0_INT_ERR_CONT_LP0		BIT(5)
212 /* Control error: incorrect line state sequence on data lane 0. */
213 # define DSI0_INT_ERR_CONTROL		BIT(4)
214 # define DSI0_INT_ERR_SYNC_ESC		BIT(3)
215 # define DSI0_INT_RX2_PKT		BIT(2)
216 # define DSI0_INT_RX1_PKT		BIT(1)
217 # define DSI0_INT_CMD_PKT		BIT(0)
218 
219 #define DSI0_INTERRUPTS_ALWAYS_ENABLED	(DSI0_INT_ERR_SYNC_ESC | \
220 					 DSI0_INT_ERR_CONTROL |	 \
221 					 DSI0_INT_ERR_CONT_LP0 | \
222 					 DSI0_INT_ERR_CONT_LP1 | \
223 					 DSI0_INT_HSTX_TO |	 \
224 					 DSI0_INT_LPRX_TO |	 \
225 					 DSI0_INT_TA_TO |	 \
226 					 DSI0_INT_PR_TO)
227 
228 # define DSI1_INT_PHY_D3_ULPS		BIT(30)
229 # define DSI1_INT_PHY_D3_STOP		BIT(29)
230 # define DSI1_INT_PHY_D2_ULPS		BIT(28)
231 # define DSI1_INT_PHY_D2_STOP		BIT(27)
232 # define DSI1_INT_PHY_D1_ULPS		BIT(26)
233 # define DSI1_INT_PHY_D1_STOP		BIT(25)
234 # define DSI1_INT_PHY_D0_ULPS		BIT(24)
235 # define DSI1_INT_PHY_D0_STOP		BIT(23)
236 # define DSI1_INT_FIFO_ERR		BIT(22)
237 # define DSI1_INT_PHY_DIR_RTF		BIT(21)
238 # define DSI1_INT_PHY_RXLPDT		BIT(20)
239 # define DSI1_INT_PHY_RXTRIG		BIT(19)
240 # define DSI1_INT_PHY_D0_LPDT		BIT(18)
241 # define DSI1_INT_PHY_DIR_FTR		BIT(17)
242 
243 /* Signaled when the clock lane enters the given state. */
244 # define DSI1_INT_PHY_CLOCK_ULPS	BIT(16)
245 # define DSI1_INT_PHY_CLOCK_HS		BIT(15)
246 # define DSI1_INT_PHY_CLOCK_STOP	BIT(14)
247 
248 /* Signaled on timeouts */
249 # define DSI1_INT_PR_TO			BIT(13)
250 # define DSI1_INT_TA_TO			BIT(12)
251 # define DSI1_INT_LPRX_TO		BIT(11)
252 # define DSI1_INT_HSTX_TO		BIT(10)
253 
254 /* Contention on a line when trying to drive the line low */
255 # define DSI1_INT_ERR_CONT_LP1		BIT(9)
256 # define DSI1_INT_ERR_CONT_LP0		BIT(8)
257 
258 /* Control error: incorrect line state sequence on data lane 0. */
259 # define DSI1_INT_ERR_CONTROL		BIT(7)
260 /* LPDT synchronization error (bits received not a multiple of 8. */
261 
262 # define DSI1_INT_ERR_SYNC_ESC		BIT(6)
263 /* Signaled after receiving an error packet from the display in
264  * response to a read.
265  */
266 # define DSI1_INT_RXPKT2		BIT(5)
267 /* Signaled after receiving a packet.  The header and optional short
268  * response will be in RXPKT1H, and a long response will be in the
269  * RXPKT_FIFO.
270  */
271 # define DSI1_INT_RXPKT1		BIT(4)
272 # define DSI1_INT_TXPKT2_DONE		BIT(3)
273 # define DSI1_INT_TXPKT2_END		BIT(2)
274 /* Signaled after all repeats of TXPKT1 are transferred. */
275 # define DSI1_INT_TXPKT1_DONE		BIT(1)
276 /* Signaled after each TXPKT1 repeat is scheduled. */
277 # define DSI1_INT_TXPKT1_END		BIT(0)
278 
279 #define DSI1_INTERRUPTS_ALWAYS_ENABLED	(DSI1_INT_ERR_SYNC_ESC | \
280 					 DSI1_INT_ERR_CONTROL |	 \
281 					 DSI1_INT_ERR_CONT_LP0 | \
282 					 DSI1_INT_ERR_CONT_LP1 | \
283 					 DSI1_INT_HSTX_TO |	 \
284 					 DSI1_INT_LPRX_TO |	 \
285 					 DSI1_INT_TA_TO |	 \
286 					 DSI1_INT_PR_TO)
287 
288 #define DSI0_STAT		0x2c
289 #define DSI0_HSTX_TO_CNT	0x30
290 #define DSI0_LPRX_TO_CNT	0x34
291 #define DSI0_TA_TO_CNT		0x38
292 #define DSI0_PR_TO_CNT		0x3c
293 #define DSI0_PHYC		0x40
294 # define DSI1_PHYC_ESC_CLK_LPDT_MASK	VC4_MASK(25, 20)
295 # define DSI1_PHYC_ESC_CLK_LPDT_SHIFT	20
296 # define DSI1_PHYC_HS_CLK_CONTINUOUS	BIT(18)
297 # define DSI0_PHYC_ESC_CLK_LPDT_MASK	VC4_MASK(17, 12)
298 # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT	12
299 # define DSI1_PHYC_CLANE_ULPS		BIT(17)
300 # define DSI1_PHYC_CLANE_ENABLE		BIT(16)
301 # define DSI_PHYC_DLANE3_ULPS		BIT(13)
302 # define DSI_PHYC_DLANE3_ENABLE		BIT(12)
303 # define DSI0_PHYC_HS_CLK_CONTINUOUS	BIT(10)
304 # define DSI0_PHYC_CLANE_ULPS		BIT(9)
305 # define DSI_PHYC_DLANE2_ULPS		BIT(9)
306 # define DSI0_PHYC_CLANE_ENABLE		BIT(8)
307 # define DSI_PHYC_DLANE2_ENABLE		BIT(8)
308 # define DSI_PHYC_DLANE1_ULPS		BIT(5)
309 # define DSI_PHYC_DLANE1_ENABLE		BIT(4)
310 # define DSI_PHYC_DLANE0_FORCE_STOP	BIT(2)
311 # define DSI_PHYC_DLANE0_ULPS		BIT(1)
312 # define DSI_PHYC_DLANE0_ENABLE		BIT(0)
313 
314 #define DSI0_HS_CLT0		0x44
315 #define DSI0_HS_CLT1		0x48
316 #define DSI0_HS_CLT2		0x4c
317 #define DSI0_HS_DLT3		0x50
318 #define DSI0_HS_DLT4		0x54
319 #define DSI0_HS_DLT5		0x58
320 #define DSI0_HS_DLT6		0x5c
321 #define DSI0_HS_DLT7		0x60
322 
323 #define DSI0_PHY_AFEC0		0x64
324 # define DSI0_PHY_AFEC0_DDR2CLK_EN		BIT(26)
325 # define DSI0_PHY_AFEC0_DDRCLK_EN		BIT(25)
326 # define DSI0_PHY_AFEC0_LATCH_ULPS		BIT(24)
327 # define DSI1_PHY_AFEC0_IDR_DLANE3_MASK		VC4_MASK(31, 29)
328 # define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT	29
329 # define DSI1_PHY_AFEC0_IDR_DLANE2_MASK		VC4_MASK(28, 26)
330 # define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT	26
331 # define DSI1_PHY_AFEC0_IDR_DLANE1_MASK		VC4_MASK(27, 23)
332 # define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT	23
333 # define DSI1_PHY_AFEC0_IDR_DLANE0_MASK		VC4_MASK(22, 20)
334 # define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT	20
335 # define DSI1_PHY_AFEC0_IDR_CLANE_MASK		VC4_MASK(19, 17)
336 # define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT		17
337 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK	VC4_MASK(23, 20)
338 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT	20
339 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK	VC4_MASK(19, 16)
340 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT	16
341 # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK	VC4_MASK(15, 12)
342 # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT	12
343 # define DSI1_PHY_AFEC0_DDR2CLK_EN		BIT(16)
344 # define DSI1_PHY_AFEC0_DDRCLK_EN		BIT(15)
345 # define DSI1_PHY_AFEC0_LATCH_ULPS		BIT(14)
346 # define DSI1_PHY_AFEC0_RESET			BIT(13)
347 # define DSI1_PHY_AFEC0_PD			BIT(12)
348 # define DSI0_PHY_AFEC0_RESET			BIT(11)
349 # define DSI1_PHY_AFEC0_PD_BG			BIT(11)
350 # define DSI0_PHY_AFEC0_PD			BIT(10)
351 # define DSI1_PHY_AFEC0_PD_DLANE1		BIT(10)
352 # define DSI0_PHY_AFEC0_PD_BG			BIT(9)
353 # define DSI1_PHY_AFEC0_PD_DLANE2		BIT(9)
354 # define DSI0_PHY_AFEC0_PD_DLANE1		BIT(8)
355 # define DSI1_PHY_AFEC0_PD_DLANE3		BIT(8)
356 # define DSI_PHY_AFEC0_PTATADJ_MASK		VC4_MASK(7, 4)
357 # define DSI_PHY_AFEC0_PTATADJ_SHIFT		4
358 # define DSI_PHY_AFEC0_CTATADJ_MASK		VC4_MASK(3, 0)
359 # define DSI_PHY_AFEC0_CTATADJ_SHIFT		0
360 
361 #define DSI0_PHY_AFEC1		0x68
362 # define DSI0_PHY_AFEC1_IDR_DLANE1_MASK		VC4_MASK(10, 8)
363 # define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT	8
364 # define DSI0_PHY_AFEC1_IDR_DLANE0_MASK		VC4_MASK(6, 4)
365 # define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT	4
366 # define DSI0_PHY_AFEC1_IDR_CLANE_MASK		VC4_MASK(2, 0)
367 # define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT		0
368 
369 #define DSI0_TST_SEL		0x6c
370 #define DSI0_TST_MON		0x70
371 #define DSI0_ID			0x74
372 # define DSI_ID_VALUE		0x00647369
373 
374 #define DSI1_CTRL		0x00
375 # define DSI_CTRL_HS_CLKC_MASK		VC4_MASK(15, 14)
376 # define DSI_CTRL_HS_CLKC_SHIFT		14
377 # define DSI_CTRL_HS_CLKC_BYTE		0
378 # define DSI_CTRL_HS_CLKC_DDR2		1
379 # define DSI_CTRL_HS_CLKC_DDR		2
380 
381 # define DSI_CTRL_RX_LPDT_EOT_DISABLE	BIT(13)
382 # define DSI_CTRL_LPDT_EOT_DISABLE	BIT(12)
383 # define DSI_CTRL_HSDT_EOT_DISABLE	BIT(11)
384 # define DSI_CTRL_SOFT_RESET_CFG	BIT(10)
385 # define DSI_CTRL_CAL_BYTE		BIT(9)
386 # define DSI_CTRL_INV_BYTE		BIT(8)
387 # define DSI_CTRL_CLR_LDF		BIT(7)
388 # define DSI0_CTRL_CLR_PBCF		BIT(6)
389 # define DSI1_CTRL_CLR_RXF		BIT(6)
390 # define DSI0_CTRL_CLR_CPBCF		BIT(5)
391 # define DSI1_CTRL_CLR_PDF		BIT(5)
392 # define DSI0_CTRL_CLR_PDF		BIT(4)
393 # define DSI1_CTRL_CLR_CDF		BIT(4)
394 # define DSI0_CTRL_CLR_CDF		BIT(3)
395 # define DSI0_CTRL_CTRL2		BIT(2)
396 # define DSI1_CTRL_DISABLE_DISP_CRCC	BIT(2)
397 # define DSI0_CTRL_CTRL1		BIT(1)
398 # define DSI1_CTRL_DISABLE_DISP_ECCC	BIT(1)
399 # define DSI0_CTRL_CTRL0		BIT(0)
400 # define DSI1_CTRL_EN			BIT(0)
401 # define DSI0_CTRL_RESET_FIFOS		(DSI_CTRL_CLR_LDF | \
402 					 DSI0_CTRL_CLR_PBCF | \
403 					 DSI0_CTRL_CLR_CPBCF |	\
404 					 DSI0_CTRL_CLR_PDF | \
405 					 DSI0_CTRL_CLR_CDF)
406 # define DSI1_CTRL_RESET_FIFOS		(DSI_CTRL_CLR_LDF | \
407 					 DSI1_CTRL_CLR_RXF | \
408 					 DSI1_CTRL_CLR_PDF | \
409 					 DSI1_CTRL_CLR_CDF)
410 
411 #define DSI1_TXPKT2C		0x0c
412 #define DSI1_TXPKT2H		0x10
413 #define DSI1_TXPKT_PIX_FIFO	0x20
414 #define DSI1_RXPKT_FIFO		0x24
415 #define DSI1_DISP0_CTRL		0x28
416 #define DSI1_INT_STAT		0x30
417 #define DSI1_INT_EN		0x34
418 /* State reporting bits.  These mostly behave like INT_STAT, where
419  * writing a 1 clears the bit.
420  */
421 #define DSI1_STAT		0x38
422 # define DSI1_STAT_PHY_D3_ULPS		BIT(31)
423 # define DSI1_STAT_PHY_D3_STOP		BIT(30)
424 # define DSI1_STAT_PHY_D2_ULPS		BIT(29)
425 # define DSI1_STAT_PHY_D2_STOP		BIT(28)
426 # define DSI1_STAT_PHY_D1_ULPS		BIT(27)
427 # define DSI1_STAT_PHY_D1_STOP		BIT(26)
428 # define DSI1_STAT_PHY_D0_ULPS		BIT(25)
429 # define DSI1_STAT_PHY_D0_STOP		BIT(24)
430 # define DSI1_STAT_FIFO_ERR		BIT(23)
431 # define DSI1_STAT_PHY_RXLPDT		BIT(22)
432 # define DSI1_STAT_PHY_RXTRIG		BIT(21)
433 # define DSI1_STAT_PHY_D0_LPDT		BIT(20)
434 /* Set when in forward direction */
435 # define DSI1_STAT_PHY_DIR		BIT(19)
436 # define DSI1_STAT_PHY_CLOCK_ULPS	BIT(18)
437 # define DSI1_STAT_PHY_CLOCK_HS		BIT(17)
438 # define DSI1_STAT_PHY_CLOCK_STOP	BIT(16)
439 # define DSI1_STAT_PR_TO		BIT(15)
440 # define DSI1_STAT_TA_TO		BIT(14)
441 # define DSI1_STAT_LPRX_TO		BIT(13)
442 # define DSI1_STAT_HSTX_TO		BIT(12)
443 # define DSI1_STAT_ERR_CONT_LP1		BIT(11)
444 # define DSI1_STAT_ERR_CONT_LP0		BIT(10)
445 # define DSI1_STAT_ERR_CONTROL		BIT(9)
446 # define DSI1_STAT_ERR_SYNC_ESC		BIT(8)
447 # define DSI1_STAT_RXPKT2		BIT(7)
448 # define DSI1_STAT_RXPKT1		BIT(6)
449 # define DSI1_STAT_TXPKT2_BUSY		BIT(5)
450 # define DSI1_STAT_TXPKT2_DONE		BIT(4)
451 # define DSI1_STAT_TXPKT2_END		BIT(3)
452 # define DSI1_STAT_TXPKT1_BUSY		BIT(2)
453 # define DSI1_STAT_TXPKT1_DONE		BIT(1)
454 # define DSI1_STAT_TXPKT1_END		BIT(0)
455 
456 #define DSI1_HSTX_TO_CNT	0x3c
457 #define DSI1_LPRX_TO_CNT	0x40
458 #define DSI1_TA_TO_CNT		0x44
459 #define DSI1_PR_TO_CNT		0x48
460 #define DSI1_PHYC		0x4c
461 
462 #define DSI1_HS_CLT0		0x50
463 # define DSI_HS_CLT0_CZERO_MASK		VC4_MASK(26, 18)
464 # define DSI_HS_CLT0_CZERO_SHIFT	18
465 # define DSI_HS_CLT0_CPRE_MASK		VC4_MASK(17, 9)
466 # define DSI_HS_CLT0_CPRE_SHIFT		9
467 # define DSI_HS_CLT0_CPREP_MASK		VC4_MASK(8, 0)
468 # define DSI_HS_CLT0_CPREP_SHIFT	0
469 
470 #define DSI1_HS_CLT1		0x54
471 # define DSI_HS_CLT1_CTRAIL_MASK	VC4_MASK(17, 9)
472 # define DSI_HS_CLT1_CTRAIL_SHIFT	9
473 # define DSI_HS_CLT1_CPOST_MASK		VC4_MASK(8, 0)
474 # define DSI_HS_CLT1_CPOST_SHIFT	0
475 
476 #define DSI1_HS_CLT2		0x58
477 # define DSI_HS_CLT2_WUP_MASK		VC4_MASK(23, 0)
478 # define DSI_HS_CLT2_WUP_SHIFT		0
479 
480 #define DSI1_HS_DLT3		0x5c
481 # define DSI_HS_DLT3_EXIT_MASK		VC4_MASK(26, 18)
482 # define DSI_HS_DLT3_EXIT_SHIFT		18
483 # define DSI_HS_DLT3_ZERO_MASK		VC4_MASK(17, 9)
484 # define DSI_HS_DLT3_ZERO_SHIFT		9
485 # define DSI_HS_DLT3_PRE_MASK		VC4_MASK(8, 0)
486 # define DSI_HS_DLT3_PRE_SHIFT		0
487 
488 #define DSI1_HS_DLT4		0x60
489 # define DSI_HS_DLT4_ANLAT_MASK		VC4_MASK(22, 18)
490 # define DSI_HS_DLT4_ANLAT_SHIFT	18
491 # define DSI_HS_DLT4_TRAIL_MASK		VC4_MASK(17, 9)
492 # define DSI_HS_DLT4_TRAIL_SHIFT	9
493 # define DSI_HS_DLT4_LPX_MASK		VC4_MASK(8, 0)
494 # define DSI_HS_DLT4_LPX_SHIFT		0
495 
496 #define DSI1_HS_DLT5		0x64
497 # define DSI_HS_DLT5_INIT_MASK		VC4_MASK(23, 0)
498 # define DSI_HS_DLT5_INIT_SHIFT		0
499 
500 #define DSI1_HS_DLT6		0x68
501 # define DSI_HS_DLT6_TA_GET_MASK	VC4_MASK(31, 24)
502 # define DSI_HS_DLT6_TA_GET_SHIFT	24
503 # define DSI_HS_DLT6_TA_SURE_MASK	VC4_MASK(23, 16)
504 # define DSI_HS_DLT6_TA_SURE_SHIFT	16
505 # define DSI_HS_DLT6_TA_GO_MASK		VC4_MASK(15, 8)
506 # define DSI_HS_DLT6_TA_GO_SHIFT	8
507 # define DSI_HS_DLT6_LP_LPX_MASK	VC4_MASK(7, 0)
508 # define DSI_HS_DLT6_LP_LPX_SHIFT	0
509 
510 #define DSI1_HS_DLT7		0x6c
511 # define DSI_HS_DLT7_LP_WUP_MASK	VC4_MASK(23, 0)
512 # define DSI_HS_DLT7_LP_WUP_SHIFT	0
513 
514 #define DSI1_PHY_AFEC0		0x70
515 
516 #define DSI1_PHY_AFEC1		0x74
517 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK	VC4_MASK(19, 16)
518 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT	16
519 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK	VC4_MASK(15, 12)
520 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT	12
521 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK	VC4_MASK(11, 8)
522 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT	8
523 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK	VC4_MASK(7, 4)
524 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT	4
525 # define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK	VC4_MASK(3, 0)
526 # define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT	0
527 
528 #define DSI1_TST_SEL		0x78
529 #define DSI1_TST_MON		0x7c
530 #define DSI1_PHY_TST1		0x80
531 #define DSI1_PHY_TST2		0x84
532 #define DSI1_PHY_FIFO_STAT	0x88
533 /* Actually, all registers in the range that aren't otherwise claimed
534  * will return the ID.
535  */
536 #define DSI1_ID			0x8c
537 
538 struct vc4_dsi_variant {
539 	/* Whether we're on bcm2835's DSI0 or DSI1. */
540 	unsigned int port;
541 
542 	bool broken_axi_workaround;
543 
544 	const char *debugfs_name;
545 	const struct debugfs_reg32 *regs;
546 	size_t nregs;
547 
548 };
549 
550 /* General DSI hardware state. */
551 struct vc4_dsi {
552 	struct vc4_encoder encoder;
553 	struct mipi_dsi_host dsi_host;
554 
555 	struct kref kref;
556 
557 	struct platform_device *pdev;
558 
559 	struct drm_bridge *bridge;
560 	struct list_head bridge_chain;
561 
562 	void __iomem *regs;
563 
564 	struct dma_chan *reg_dma_chan;
565 	dma_addr_t reg_dma_paddr;
566 	u32 *reg_dma_mem;
567 	dma_addr_t reg_paddr;
568 
569 	const struct vc4_dsi_variant *variant;
570 
571 	/* DSI channel for the panel we're connected to. */
572 	u32 channel;
573 	u32 lanes;
574 	u32 format;
575 	u32 divider;
576 	u32 mode_flags;
577 
578 	/* Input clock from CPRMAN to the digital PHY, for the DSI
579 	 * escape clock.
580 	 */
581 	struct clk *escape_clock;
582 
583 	/* Input clock to the analog PHY, used to generate the DSI bit
584 	 * clock.
585 	 */
586 	struct clk *pll_phy_clock;
587 
588 	/* HS Clocks generated within the DSI analog PHY. */
589 	struct clk_fixed_factor phy_clocks[3];
590 
591 	struct clk_hw_onecell_data *clk_onecell;
592 
593 	/* Pixel clock output to the pixelvalve, generated from the HS
594 	 * clock.
595 	 */
596 	struct clk *pixel_clock;
597 
598 	struct completion xfer_completion;
599 	int xfer_result;
600 
601 	struct debugfs_regset32 regset;
602 };
603 
604 #define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
605 
606 static inline struct vc4_dsi *
to_vc4_dsi(struct drm_encoder * encoder)607 to_vc4_dsi(struct drm_encoder *encoder)
608 {
609 	return container_of(encoder, struct vc4_dsi, encoder.base);
610 }
611 
612 static inline void
dsi_dma_workaround_write(struct vc4_dsi * dsi,u32 offset,u32 val)613 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
614 {
615 	struct dma_chan *chan = dsi->reg_dma_chan;
616 	struct dma_async_tx_descriptor *tx;
617 	dma_cookie_t cookie;
618 	int ret;
619 
620 	/* DSI0 should be able to write normally. */
621 	if (!chan) {
622 		writel(val, dsi->regs + offset);
623 		return;
624 	}
625 
626 	*dsi->reg_dma_mem = val;
627 
628 	tx = chan->device->device_prep_dma_memcpy(chan,
629 						  dsi->reg_paddr + offset,
630 						  dsi->reg_dma_paddr,
631 						  4, 0);
632 	if (!tx) {
633 		DRM_ERROR("Failed to set up DMA register write\n");
634 		return;
635 	}
636 
637 	cookie = tx->tx_submit(tx);
638 	ret = dma_submit_error(cookie);
639 	if (ret) {
640 		DRM_ERROR("Failed to submit DMA: %d\n", ret);
641 		return;
642 	}
643 	ret = dma_sync_wait(chan, cookie);
644 	if (ret)
645 		DRM_ERROR("Failed to wait for DMA: %d\n", ret);
646 }
647 
648 #define DSI_READ(offset) readl(dsi->regs + (offset))
649 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
650 #define DSI_PORT_READ(offset) \
651 	DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
652 #define DSI_PORT_WRITE(offset, val) \
653 	DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
654 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
655 
656 static const struct debugfs_reg32 dsi0_regs[] = {
657 	VC4_REG32(DSI0_CTRL),
658 	VC4_REG32(DSI0_STAT),
659 	VC4_REG32(DSI0_HSTX_TO_CNT),
660 	VC4_REG32(DSI0_LPRX_TO_CNT),
661 	VC4_REG32(DSI0_TA_TO_CNT),
662 	VC4_REG32(DSI0_PR_TO_CNT),
663 	VC4_REG32(DSI0_DISP0_CTRL),
664 	VC4_REG32(DSI0_DISP1_CTRL),
665 	VC4_REG32(DSI0_INT_STAT),
666 	VC4_REG32(DSI0_INT_EN),
667 	VC4_REG32(DSI0_PHYC),
668 	VC4_REG32(DSI0_HS_CLT0),
669 	VC4_REG32(DSI0_HS_CLT1),
670 	VC4_REG32(DSI0_HS_CLT2),
671 	VC4_REG32(DSI0_HS_DLT3),
672 	VC4_REG32(DSI0_HS_DLT4),
673 	VC4_REG32(DSI0_HS_DLT5),
674 	VC4_REG32(DSI0_HS_DLT6),
675 	VC4_REG32(DSI0_HS_DLT7),
676 	VC4_REG32(DSI0_PHY_AFEC0),
677 	VC4_REG32(DSI0_PHY_AFEC1),
678 	VC4_REG32(DSI0_ID),
679 };
680 
681 static const struct debugfs_reg32 dsi1_regs[] = {
682 	VC4_REG32(DSI1_CTRL),
683 	VC4_REG32(DSI1_STAT),
684 	VC4_REG32(DSI1_HSTX_TO_CNT),
685 	VC4_REG32(DSI1_LPRX_TO_CNT),
686 	VC4_REG32(DSI1_TA_TO_CNT),
687 	VC4_REG32(DSI1_PR_TO_CNT),
688 	VC4_REG32(DSI1_DISP0_CTRL),
689 	VC4_REG32(DSI1_DISP1_CTRL),
690 	VC4_REG32(DSI1_INT_STAT),
691 	VC4_REG32(DSI1_INT_EN),
692 	VC4_REG32(DSI1_PHYC),
693 	VC4_REG32(DSI1_HS_CLT0),
694 	VC4_REG32(DSI1_HS_CLT1),
695 	VC4_REG32(DSI1_HS_CLT2),
696 	VC4_REG32(DSI1_HS_DLT3),
697 	VC4_REG32(DSI1_HS_DLT4),
698 	VC4_REG32(DSI1_HS_DLT5),
699 	VC4_REG32(DSI1_HS_DLT6),
700 	VC4_REG32(DSI1_HS_DLT7),
701 	VC4_REG32(DSI1_PHY_AFEC0),
702 	VC4_REG32(DSI1_PHY_AFEC1),
703 	VC4_REG32(DSI1_ID),
704 };
705 
vc4_dsi_latch_ulps(struct vc4_dsi * dsi,bool latch)706 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
707 {
708 	u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
709 
710 	if (latch)
711 		afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
712 	else
713 		afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
714 
715 	DSI_PORT_WRITE(PHY_AFEC0, afec0);
716 }
717 
718 /* Enters or exits Ultra Low Power State. */
vc4_dsi_ulps(struct vc4_dsi * dsi,bool ulps)719 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
720 {
721 	bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
722 	u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |
723 			 DSI_PHYC_DLANE0_ULPS |
724 			 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
725 			 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
726 			 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
727 	u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) |
728 			 DSI1_STAT_PHY_D0_ULPS |
729 			 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
730 			 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
731 			 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
732 	u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) |
733 			 DSI1_STAT_PHY_D0_STOP |
734 			 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
735 			 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
736 			 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
737 	int ret;
738 	bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) &
739 				       DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));
740 
741 	if (ulps == ulps_currently_enabled)
742 		return;
743 
744 	DSI_PORT_WRITE(STAT, stat_ulps);
745 	DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
746 	ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
747 	if (ret) {
748 		dev_warn(&dsi->pdev->dev,
749 			 "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
750 			 DSI_PORT_READ(STAT));
751 		DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
752 		vc4_dsi_latch_ulps(dsi, false);
753 		return;
754 	}
755 
756 	/* The DSI module can't be disabled while the module is
757 	 * generating ULPS state.  So, to be able to disable the
758 	 * module, we have the AFE latch the ULPS state and continue
759 	 * on to having the module enter STOP.
760 	 */
761 	vc4_dsi_latch_ulps(dsi, ulps);
762 
763 	DSI_PORT_WRITE(STAT, stat_stop);
764 	DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
765 	ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
766 	if (ret) {
767 		dev_warn(&dsi->pdev->dev,
768 			 "Timeout waiting for DSI STOP entry: STAT 0x%08x",
769 			 DSI_PORT_READ(STAT));
770 		DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
771 		return;
772 	}
773 }
774 
775 static u32
dsi_hs_timing(u32 ui_ns,u32 ns,u32 ui)776 dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
777 {
778 	/* The HS timings have to be rounded up to a multiple of 8
779 	 * because we're using the byte clock.
780 	 */
781 	return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
782 }
783 
784 /* ESC always runs at 100Mhz. */
785 #define ESC_TIME_NS 10
786 
787 static u32
dsi_esc_timing(u32 ns)788 dsi_esc_timing(u32 ns)
789 {
790 	return DIV_ROUND_UP(ns, ESC_TIME_NS);
791 }
792 
vc4_dsi_encoder_disable(struct drm_encoder * encoder)793 static void vc4_dsi_encoder_disable(struct drm_encoder *encoder)
794 {
795 	struct vc4_dsi *dsi = to_vc4_dsi(encoder);
796 	struct device *dev = &dsi->pdev->dev;
797 	struct drm_bridge *iter;
798 
799 	list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {
800 		if (iter->funcs->disable)
801 			iter->funcs->disable(iter);
802 
803 		if (iter == dsi->bridge)
804 			break;
805 	}
806 
807 	vc4_dsi_ulps(dsi, true);
808 
809 	list_for_each_entry_from(iter, &dsi->bridge_chain, chain_node) {
810 		if (iter->funcs->post_disable)
811 			iter->funcs->post_disable(iter);
812 	}
813 
814 	clk_disable_unprepare(dsi->pll_phy_clock);
815 	clk_disable_unprepare(dsi->escape_clock);
816 	clk_disable_unprepare(dsi->pixel_clock);
817 
818 	pm_runtime_put(dev);
819 }
820 
821 /* Extends the mode's blank intervals to handle BCM2835's integer-only
822  * DSI PLL divider.
823  *
824  * On 2835, PLLD is set to 2Ghz, and may not be changed by the display
825  * driver since most peripherals are hanging off of the PLLD_PER
826  * divider.  PLLD_DSI1, which drives our DSI bit clock (and therefore
827  * the pixel clock), only has an integer divider off of DSI.
828  *
829  * To get our panel mode to refresh at the expected 60Hz, we need to
830  * extend the horizontal blank time.  This means we drive a
831  * higher-than-expected clock rate to the panel, but that's what the
832  * firmware does too.
833  */
vc4_dsi_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)834 static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
835 				       const struct drm_display_mode *mode,
836 				       struct drm_display_mode *adjusted_mode)
837 {
838 	struct vc4_dsi *dsi = to_vc4_dsi(encoder);
839 	struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
840 	unsigned long parent_rate = clk_get_rate(phy_parent);
841 	unsigned long pixel_clock_hz = mode->clock * 1000;
842 	unsigned long pll_clock = pixel_clock_hz * dsi->divider;
843 	int divider;
844 
845 	/* Find what divider gets us a faster clock than the requested
846 	 * pixel clock.
847 	 */
848 	for (divider = 1; divider < 255; divider++) {
849 		if (parent_rate / (divider + 1) < pll_clock)
850 			break;
851 	}
852 
853 	/* Now that we've picked a PLL divider, calculate back to its
854 	 * pixel clock.
855 	 */
856 	pll_clock = parent_rate / divider;
857 	pixel_clock_hz = pll_clock / dsi->divider;
858 
859 	adjusted_mode->clock = pixel_clock_hz / 1000;
860 
861 	/* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
862 	adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
863 				mode->clock;
864 	adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
865 	adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
866 
867 	return true;
868 }
869 
vc4_dsi_encoder_enable(struct drm_encoder * encoder)870 static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
871 {
872 	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
873 	struct vc4_dsi *dsi = to_vc4_dsi(encoder);
874 	struct device *dev = &dsi->pdev->dev;
875 	bool debug_dump_regs = false;
876 	struct drm_bridge *iter;
877 	unsigned long hs_clock;
878 	u32 ui_ns;
879 	/* Minimum LP state duration in escape clock cycles. */
880 	u32 lpx = dsi_esc_timing(60);
881 	unsigned long pixel_clock_hz = mode->clock * 1000;
882 	unsigned long dsip_clock;
883 	unsigned long phy_clock;
884 	int ret;
885 
886 	ret = pm_runtime_resume_and_get(dev);
887 	if (ret) {
888 		DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
889 		return;
890 	}
891 
892 	if (debug_dump_regs) {
893 		struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
894 		dev_info(&dsi->pdev->dev, "DSI regs before:\n");
895 		drm_print_regset32(&p, &dsi->regset);
896 	}
897 
898 	/* Round up the clk_set_rate() request slightly, since
899 	 * PLLD_DSI1 is an integer divider and its rate selection will
900 	 * never round up.
901 	 */
902 	phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
903 	ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
904 	if (ret) {
905 		dev_err(&dsi->pdev->dev,
906 			"Failed to set phy clock to %ld: %d\n", phy_clock, ret);
907 	}
908 
909 	/* Reset the DSI and all its fifos. */
910 	DSI_PORT_WRITE(CTRL,
911 		       DSI_CTRL_SOFT_RESET_CFG |
912 		       DSI_PORT_BIT(CTRL_RESET_FIFOS));
913 
914 	DSI_PORT_WRITE(CTRL,
915 		       DSI_CTRL_HSDT_EOT_DISABLE |
916 		       DSI_CTRL_RX_LPDT_EOT_DISABLE);
917 
918 	/* Clear all stat bits so we see what has happened during enable. */
919 	DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));
920 
921 	/* Set AFE CTR00/CTR1 to release powerdown of analog. */
922 	if (dsi->variant->port == 0) {
923 		u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
924 			     VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
925 
926 		if (dsi->lanes < 2)
927 			afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
928 
929 		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
930 			afec0 |= DSI0_PHY_AFEC0_RESET;
931 
932 		DSI_PORT_WRITE(PHY_AFEC0, afec0);
933 
934 		/* AFEC reset hold time */
935 		mdelay(1);
936 
937 		DSI_PORT_WRITE(PHY_AFEC1,
938 			       VC4_SET_FIELD(6,  DSI0_PHY_AFEC1_IDR_DLANE1) |
939 			       VC4_SET_FIELD(6,  DSI0_PHY_AFEC1_IDR_DLANE0) |
940 			       VC4_SET_FIELD(6,  DSI0_PHY_AFEC1_IDR_CLANE));
941 	} else {
942 		u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
943 			     VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
944 			     VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
945 			     VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
946 			     VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
947 			     VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
948 			     VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
949 
950 		if (dsi->lanes < 4)
951 			afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
952 		if (dsi->lanes < 3)
953 			afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
954 		if (dsi->lanes < 2)
955 			afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
956 
957 		afec0 |= DSI1_PHY_AFEC0_RESET;
958 
959 		DSI_PORT_WRITE(PHY_AFEC0, afec0);
960 
961 		DSI_PORT_WRITE(PHY_AFEC1, 0);
962 
963 		/* AFEC reset hold time */
964 		mdelay(1);
965 	}
966 
967 	ret = clk_prepare_enable(dsi->escape_clock);
968 	if (ret) {
969 		DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
970 		return;
971 	}
972 
973 	ret = clk_prepare_enable(dsi->pll_phy_clock);
974 	if (ret) {
975 		DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
976 		return;
977 	}
978 
979 	hs_clock = clk_get_rate(dsi->pll_phy_clock);
980 
981 	/* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
982 	 * not the pixel clock rate.  DSIxP take from the APHY's byte,
983 	 * DDR2, or DDR4 clock (we use byte) and feed into the PV at
984 	 * that rate.  Separately, a value derived from PIX_CLK_DIV
985 	 * and HS_CLKC is fed into the PV to divide down to the actual
986 	 * pixel clock for pushing pixels into DSI.
987 	 */
988 	dsip_clock = phy_clock / 8;
989 	ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
990 	if (ret) {
991 		dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n",
992 			dsip_clock, ret);
993 	}
994 
995 	ret = clk_prepare_enable(dsi->pixel_clock);
996 	if (ret) {
997 		DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
998 		return;
999 	}
1000 
1001 	/* How many ns one DSI unit interval is.  Note that the clock
1002 	 * is DDR, so there's an extra divide by 2.
1003 	 */
1004 	ui_ns = DIV_ROUND_UP(500000000, hs_clock);
1005 
1006 	DSI_PORT_WRITE(HS_CLT0,
1007 		       VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
1008 				     DSI_HS_CLT0_CZERO) |
1009 		       VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
1010 				     DSI_HS_CLT0_CPRE) |
1011 		       VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
1012 				     DSI_HS_CLT0_CPREP));
1013 
1014 	DSI_PORT_WRITE(HS_CLT1,
1015 		       VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
1016 				     DSI_HS_CLT1_CTRAIL) |
1017 		       VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
1018 				     DSI_HS_CLT1_CPOST));
1019 
1020 	DSI_PORT_WRITE(HS_CLT2,
1021 		       VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
1022 				     DSI_HS_CLT2_WUP));
1023 
1024 	DSI_PORT_WRITE(HS_DLT3,
1025 		       VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
1026 				     DSI_HS_DLT3_EXIT) |
1027 		       VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
1028 				     DSI_HS_DLT3_ZERO) |
1029 		       VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
1030 				     DSI_HS_DLT3_PRE));
1031 
1032 	DSI_PORT_WRITE(HS_DLT4,
1033 		       VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
1034 				     DSI_HS_DLT4_LPX) |
1035 		       VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
1036 					 dsi_hs_timing(ui_ns, 60, 4)),
1037 				     DSI_HS_DLT4_TRAIL) |
1038 		       VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
1039 
1040 	/* T_INIT is how long STOP is driven after power-up to
1041 	 * indicate to the slave (also coming out of power-up) that
1042 	 * master init is complete, and should be greater than the
1043 	 * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE.  The
1044 	 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
1045 	 * T_INIT,SLAVE, while allowing protocols on top of it to give
1046 	 * greater minimums.  The vc4 firmware uses an extremely
1047 	 * conservative 5ms, and we maintain that here.
1048 	 */
1049 	DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
1050 							    5 * 1000 * 1000, 0),
1051 					      DSI_HS_DLT5_INIT));
1052 
1053 	DSI_PORT_WRITE(HS_DLT6,
1054 		       VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1055 		       VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1056 		       VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1057 		       VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1058 
1059 	DSI_PORT_WRITE(HS_DLT7,
1060 		       VC4_SET_FIELD(dsi_esc_timing(1000000),
1061 				     DSI_HS_DLT7_LP_WUP));
1062 
1063 	DSI_PORT_WRITE(PHYC,
1064 		       DSI_PHYC_DLANE0_ENABLE |
1065 		       (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1066 		       (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1067 		       (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1068 		       DSI_PORT_BIT(PHYC_CLANE_ENABLE) |
1069 		       ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1070 			0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |
1071 		       (dsi->variant->port == 0 ?
1072 			VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1073 			VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1074 
1075 	DSI_PORT_WRITE(CTRL,
1076 		       DSI_PORT_READ(CTRL) |
1077 		       DSI_CTRL_CAL_BYTE);
1078 
1079 	/* HS timeout in HS clock cycles: disabled. */
1080 	DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1081 	/* LP receive timeout in HS clocks. */
1082 	DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1083 	/* Bus turnaround timeout */
1084 	DSI_PORT_WRITE(TA_TO_CNT, 100000);
1085 	/* Display reset sequence timeout */
1086 	DSI_PORT_WRITE(PR_TO_CNT, 100000);
1087 
1088 	/* Set up DISP1 for transferring long command payloads through
1089 	 * the pixfifo.
1090 	 */
1091 	DSI_PORT_WRITE(DISP1_CTRL,
1092 		       VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1093 				     DSI_DISP1_PFORMAT) |
1094 		       DSI_DISP1_ENABLE);
1095 
1096 	/* Ungate the block. */
1097 	if (dsi->variant->port == 0)
1098 		DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1099 	else
1100 		DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1101 
1102 	/* Bring AFE out of reset. */
1103 	DSI_PORT_WRITE(PHY_AFEC0,
1104 		       DSI_PORT_READ(PHY_AFEC0) &
1105 		       ~DSI_PORT_BIT(PHY_AFEC0_RESET));
1106 
1107 	vc4_dsi_ulps(dsi, false);
1108 
1109 	list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {
1110 		if (iter->funcs->pre_enable)
1111 			iter->funcs->pre_enable(iter);
1112 	}
1113 
1114 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1115 		DSI_PORT_WRITE(DISP0_CTRL,
1116 			       VC4_SET_FIELD(dsi->divider,
1117 					     DSI_DISP0_PIX_CLK_DIV) |
1118 			       VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1119 			       VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1120 					     DSI_DISP0_LP_STOP_CTRL) |
1121 			       DSI_DISP0_ST_END |
1122 			       DSI_DISP0_ENABLE);
1123 	} else {
1124 		DSI_PORT_WRITE(DISP0_CTRL,
1125 			       DSI_DISP0_COMMAND_MODE |
1126 			       DSI_DISP0_ENABLE);
1127 	}
1128 
1129 	list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
1130 		if (iter->funcs->enable)
1131 			iter->funcs->enable(iter);
1132 	}
1133 
1134 	if (debug_dump_regs) {
1135 		struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
1136 		dev_info(&dsi->pdev->dev, "DSI regs after:\n");
1137 		drm_print_regset32(&p, &dsi->regset);
1138 	}
1139 }
1140 
vc4_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1141 static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1142 				     const struct mipi_dsi_msg *msg)
1143 {
1144 	struct vc4_dsi *dsi = host_to_dsi(host);
1145 	struct mipi_dsi_packet packet;
1146 	u32 pkth = 0, pktc = 0;
1147 	int i, ret;
1148 	bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1149 	u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1150 
1151 	mipi_dsi_create_packet(&packet, msg);
1152 
1153 	pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1154 	pkth |= VC4_SET_FIELD(packet.header[1] |
1155 			      (packet.header[2] << 8),
1156 			      DSI_TXPKT1H_BC_PARAM);
1157 	if (is_long) {
1158 		/* Divide data across the various FIFOs we have available.
1159 		 * The command FIFO takes byte-oriented data, but is of
1160 		 * limited size. The pixel FIFO (never actually used for
1161 		 * pixel data in reality) is word oriented, and substantially
1162 		 * larger. So, we use the pixel FIFO for most of the data,
1163 		 * sending the residual bytes in the command FIFO at the start.
1164 		 *
1165 		 * With this arrangement, the command FIFO will never get full.
1166 		 */
1167 		if (packet.payload_length <= 16) {
1168 			cmd_fifo_len = packet.payload_length;
1169 			pix_fifo_len = 0;
1170 		} else {
1171 			cmd_fifo_len = (packet.payload_length %
1172 					DSI_PIX_FIFO_WIDTH);
1173 			pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1174 					DSI_PIX_FIFO_WIDTH);
1175 		}
1176 
1177 		WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1178 
1179 		pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1180 	}
1181 
1182 	if (msg->rx_len) {
1183 		pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1184 				      DSI_TXPKT1C_CMD_CTRL);
1185 	} else {
1186 		pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1187 				      DSI_TXPKT1C_CMD_CTRL);
1188 	}
1189 
1190 	for (i = 0; i < cmd_fifo_len; i++)
1191 		DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1192 	for (i = 0; i < pix_fifo_len; i++) {
1193 		const u8 *pix = packet.payload + cmd_fifo_len + i * 4;
1194 
1195 		DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1196 			       pix[0] |
1197 			       pix[1] << 8 |
1198 			       pix[2] << 16 |
1199 			       pix[3] << 24);
1200 	}
1201 
1202 	if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1203 		pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1204 	if (is_long)
1205 		pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1206 
1207 	/* Send one copy of the packet.  Larger repeats are used for pixel
1208 	 * data in command mode.
1209 	 */
1210 	pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1211 
1212 	pktc |= DSI_TXPKT1C_CMD_EN;
1213 	if (pix_fifo_len) {
1214 		pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1215 				      DSI_TXPKT1C_DISPLAY_NO);
1216 	} else {
1217 		pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1218 				      DSI_TXPKT1C_DISPLAY_NO);
1219 	}
1220 
1221 	/* Enable the appropriate interrupt for the transfer completion. */
1222 	dsi->xfer_result = 0;
1223 	reinit_completion(&dsi->xfer_completion);
1224 	if (dsi->variant->port == 0) {
1225 		DSI_PORT_WRITE(INT_STAT,
1226 			       DSI0_INT_CMDC_DONE_MASK | DSI1_INT_PHY_DIR_RTF);
1227 		if (msg->rx_len) {
1228 			DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED |
1229 						DSI0_INT_PHY_DIR_RTF));
1230 		} else {
1231 			DSI_PORT_WRITE(INT_EN,
1232 				       (DSI0_INTERRUPTS_ALWAYS_ENABLED |
1233 					VC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT,
1234 						      DSI0_INT_CMDC_DONE)));
1235 		}
1236 	} else {
1237 		DSI_PORT_WRITE(INT_STAT,
1238 			       DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1239 		if (msg->rx_len) {
1240 			DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1241 						DSI1_INT_PHY_DIR_RTF));
1242 		} else {
1243 			DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1244 						DSI1_INT_TXPKT1_DONE));
1245 		}
1246 	}
1247 
1248 	/* Send the packet. */
1249 	DSI_PORT_WRITE(TXPKT1H, pkth);
1250 	DSI_PORT_WRITE(TXPKT1C, pktc);
1251 
1252 	if (!wait_for_completion_timeout(&dsi->xfer_completion,
1253 					 msecs_to_jiffies(1000))) {
1254 		dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1255 		dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1256 			DSI_PORT_READ(INT_STAT));
1257 		ret = -ETIMEDOUT;
1258 	} else {
1259 		ret = dsi->xfer_result;
1260 	}
1261 
1262 	DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
1263 
1264 	if (ret)
1265 		goto reset_fifo_and_return;
1266 
1267 	if (ret == 0 && msg->rx_len) {
1268 		u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1269 		u8 *msg_rx = msg->rx_buf;
1270 
1271 		if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1272 			u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1273 						  DSI_RXPKT1H_BC_PARAM);
1274 
1275 			if (rxlen != msg->rx_len) {
1276 				DRM_ERROR("DSI returned %db, expecting %db\n",
1277 					  rxlen, (int)msg->rx_len);
1278 				ret = -ENXIO;
1279 				goto reset_fifo_and_return;
1280 			}
1281 
1282 			for (i = 0; i < msg->rx_len; i++)
1283 				msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1284 		} else {
1285 			/* FINISHME: Handle AWER */
1286 
1287 			msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1288 						  DSI_RXPKT1H_SHORT_0);
1289 			if (msg->rx_len > 1) {
1290 				msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1291 							  DSI_RXPKT1H_SHORT_1);
1292 			}
1293 		}
1294 	}
1295 
1296 	return ret;
1297 
1298 reset_fifo_and_return:
1299 	DRM_ERROR("DSI transfer failed, resetting: %d\n", ret);
1300 
1301 	DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1302 	udelay(1);
1303 	DSI_PORT_WRITE(CTRL,
1304 		       DSI_PORT_READ(CTRL) |
1305 		       DSI_PORT_BIT(CTRL_RESET_FIFOS));
1306 
1307 	DSI_PORT_WRITE(TXPKT1C, 0);
1308 	DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
1309 	return ret;
1310 }
1311 
1312 static const struct component_ops vc4_dsi_ops;
vc4_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1313 static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1314 			       struct mipi_dsi_device *device)
1315 {
1316 	struct vc4_dsi *dsi = host_to_dsi(host);
1317 
1318 	dsi->lanes = device->lanes;
1319 	dsi->channel = device->channel;
1320 	dsi->mode_flags = device->mode_flags;
1321 
1322 	switch (device->format) {
1323 	case MIPI_DSI_FMT_RGB888:
1324 		dsi->format = DSI_PFORMAT_RGB888;
1325 		dsi->divider = 24 / dsi->lanes;
1326 		break;
1327 	case MIPI_DSI_FMT_RGB666:
1328 		dsi->format = DSI_PFORMAT_RGB666;
1329 		dsi->divider = 24 / dsi->lanes;
1330 		break;
1331 	case MIPI_DSI_FMT_RGB666_PACKED:
1332 		dsi->format = DSI_PFORMAT_RGB666_PACKED;
1333 		dsi->divider = 18 / dsi->lanes;
1334 		break;
1335 	case MIPI_DSI_FMT_RGB565:
1336 		dsi->format = DSI_PFORMAT_RGB565;
1337 		dsi->divider = 16 / dsi->lanes;
1338 		break;
1339 	default:
1340 		dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1341 			dsi->format);
1342 		return 0;
1343 	}
1344 
1345 	if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1346 		dev_err(&dsi->pdev->dev,
1347 			"Only VIDEO mode panels supported currently.\n");
1348 		return 0;
1349 	}
1350 
1351 	return component_add(&dsi->pdev->dev, &vc4_dsi_ops);
1352 }
1353 
vc4_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1354 static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1355 			       struct mipi_dsi_device *device)
1356 {
1357 	struct vc4_dsi *dsi = host_to_dsi(host);
1358 
1359 	component_del(&dsi->pdev->dev, &vc4_dsi_ops);
1360 	return 0;
1361 }
1362 
1363 static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1364 	.attach = vc4_dsi_host_attach,
1365 	.detach = vc4_dsi_host_detach,
1366 	.transfer = vc4_dsi_host_transfer,
1367 };
1368 
1369 static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs = {
1370 	.disable = vc4_dsi_encoder_disable,
1371 	.enable = vc4_dsi_encoder_enable,
1372 	.mode_fixup = vc4_dsi_encoder_mode_fixup,
1373 };
1374 
vc4_dsi_late_register(struct drm_encoder * encoder)1375 static int vc4_dsi_late_register(struct drm_encoder *encoder)
1376 {
1377 	struct drm_device *drm = encoder->dev;
1378 	struct vc4_dsi *dsi = to_vc4_dsi(encoder);
1379 	int ret;
1380 
1381 	ret = vc4_debugfs_add_regset32(drm->primary, dsi->variant->debugfs_name,
1382 				       &dsi->regset);
1383 	if (ret)
1384 		return ret;
1385 
1386 	return 0;
1387 }
1388 
1389 static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = {
1390 	.late_register = vc4_dsi_late_register,
1391 };
1392 
1393 static const struct vc4_dsi_variant bcm2711_dsi1_variant = {
1394 	.port			= 1,
1395 	.debugfs_name		= "dsi1_regs",
1396 	.regs			= dsi1_regs,
1397 	.nregs			= ARRAY_SIZE(dsi1_regs),
1398 };
1399 
1400 static const struct vc4_dsi_variant bcm2835_dsi0_variant = {
1401 	.port			= 0,
1402 	.debugfs_name		= "dsi0_regs",
1403 	.regs			= dsi0_regs,
1404 	.nregs			= ARRAY_SIZE(dsi0_regs),
1405 };
1406 
1407 static const struct vc4_dsi_variant bcm2835_dsi1_variant = {
1408 	.port			= 1,
1409 	.broken_axi_workaround	= true,
1410 	.debugfs_name		= "dsi1_regs",
1411 	.regs			= dsi1_regs,
1412 	.nregs			= ARRAY_SIZE(dsi1_regs),
1413 };
1414 
1415 static const struct of_device_id vc4_dsi_dt_match[] = {
1416 	{ .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1417 	{ .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1418 	{ .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1419 	{}
1420 };
1421 
dsi_handle_error(struct vc4_dsi * dsi,irqreturn_t * ret,u32 stat,u32 bit,const char * type)1422 static void dsi_handle_error(struct vc4_dsi *dsi,
1423 			     irqreturn_t *ret, u32 stat, u32 bit,
1424 			     const char *type)
1425 {
1426 	if (!(stat & bit))
1427 		return;
1428 
1429 	DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type);
1430 	*ret = IRQ_HANDLED;
1431 }
1432 
1433 /*
1434  * Initial handler for port 1 where we need the reg_dma workaround.
1435  * The register DMA writes sleep, so we can't do it in the top half.
1436  * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
1437  * parent interrupt contrller until our interrupt thread is done.
1438  */
vc4_dsi_irq_defer_to_thread_handler(int irq,void * data)1439 static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data)
1440 {
1441 	struct vc4_dsi *dsi = data;
1442 	u32 stat = DSI_PORT_READ(INT_STAT);
1443 
1444 	if (!stat)
1445 		return IRQ_NONE;
1446 
1447 	return IRQ_WAKE_THREAD;
1448 }
1449 
1450 /*
1451  * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1452  * 1 where we need the reg_dma workaround.
1453  */
vc4_dsi_irq_handler(int irq,void * data)1454 static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1455 {
1456 	struct vc4_dsi *dsi = data;
1457 	u32 stat = DSI_PORT_READ(INT_STAT);
1458 	irqreturn_t ret = IRQ_NONE;
1459 
1460 	DSI_PORT_WRITE(INT_STAT, stat);
1461 
1462 	dsi_handle_error(dsi, &ret, stat,
1463 			 DSI_PORT_BIT(INT_ERR_SYNC_ESC), "LPDT sync");
1464 	dsi_handle_error(dsi, &ret, stat,
1465 			 DSI_PORT_BIT(INT_ERR_CONTROL), "data lane 0 sequence");
1466 	dsi_handle_error(dsi, &ret, stat,
1467 			 DSI_PORT_BIT(INT_ERR_CONT_LP0), "LP0 contention");
1468 	dsi_handle_error(dsi, &ret, stat,
1469 			 DSI_PORT_BIT(INT_ERR_CONT_LP1), "LP1 contention");
1470 	dsi_handle_error(dsi, &ret, stat,
1471 			 DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout");
1472 	dsi_handle_error(dsi, &ret, stat,
1473 			 DSI_PORT_BIT(INT_LPRX_TO), "LPRX timeout");
1474 	dsi_handle_error(dsi, &ret, stat,
1475 			 DSI_PORT_BIT(INT_TA_TO), "turnaround timeout");
1476 	dsi_handle_error(dsi, &ret, stat,
1477 			 DSI_PORT_BIT(INT_PR_TO), "peripheral reset timeout");
1478 
1479 	if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :
1480 					  DSI0_INT_CMDC_DONE_MASK) |
1481 		    DSI_PORT_BIT(INT_PHY_DIR_RTF))) {
1482 		complete(&dsi->xfer_completion);
1483 		ret = IRQ_HANDLED;
1484 	} else if (stat & DSI_PORT_BIT(INT_HSTX_TO)) {
1485 		complete(&dsi->xfer_completion);
1486 		dsi->xfer_result = -ETIMEDOUT;
1487 		ret = IRQ_HANDLED;
1488 	}
1489 
1490 	return ret;
1491 }
1492 
1493 /**
1494  * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1495  * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1496  * @dsi: DSI encoder
1497  */
1498 static int
vc4_dsi_init_phy_clocks(struct vc4_dsi * dsi)1499 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1500 {
1501 	struct device *dev = &dsi->pdev->dev;
1502 	const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1503 	static const struct {
1504 		const char *name;
1505 		int div;
1506 	} phy_clocks[] = {
1507 		{ "byte", 8 },
1508 		{ "ddr2", 4 },
1509 		{ "ddr", 2 },
1510 	};
1511 	int i;
1512 
1513 	dsi->clk_onecell = devm_kzalloc(dev,
1514 					sizeof(*dsi->clk_onecell) +
1515 					ARRAY_SIZE(phy_clocks) *
1516 					sizeof(struct clk_hw *),
1517 					GFP_KERNEL);
1518 	if (!dsi->clk_onecell)
1519 		return -ENOMEM;
1520 	dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1521 
1522 	for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
1523 		struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1524 		struct clk_init_data init;
1525 		char clk_name[16];
1526 		int ret;
1527 
1528 		snprintf(clk_name, sizeof(clk_name),
1529 			 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name);
1530 
1531 		/* We just use core fixed factor clock ops for the PHY
1532 		 * clocks.  The clocks are actually gated by the
1533 		 * PHY_AFEC0_DDRCLK_EN bits, which we should be
1534 		 * setting if we use the DDR/DDR2 clocks.  However,
1535 		 * vc4_dsi_encoder_enable() is setting up both AFEC0,
1536 		 * setting both our parent DSI PLL's rate and this
1537 		 * clock's rate, so it knows if DDR/DDR2 are going to
1538 		 * be used and could enable the gates itself.
1539 		 */
1540 		fix->mult = 1;
1541 		fix->div = phy_clocks[i].div;
1542 		fix->hw.init = &init;
1543 
1544 		memset(&init, 0, sizeof(init));
1545 		init.parent_names = &parent_name;
1546 		init.num_parents = 1;
1547 		init.name = clk_name;
1548 		init.ops = &clk_fixed_factor_ops;
1549 
1550 		ret = devm_clk_hw_register(dev, &fix->hw);
1551 		if (ret)
1552 			return ret;
1553 
1554 		dsi->clk_onecell->hws[i] = &fix->hw;
1555 	}
1556 
1557 	return of_clk_add_hw_provider(dev->of_node,
1558 				      of_clk_hw_onecell_get,
1559 				      dsi->clk_onecell);
1560 }
1561 
vc4_dsi_dma_mem_release(void * ptr)1562 static void vc4_dsi_dma_mem_release(void *ptr)
1563 {
1564 	struct vc4_dsi *dsi = ptr;
1565 	struct device *dev = &dsi->pdev->dev;
1566 
1567 	dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr);
1568 	dsi->reg_dma_mem = NULL;
1569 }
1570 
vc4_dsi_dma_chan_release(void * ptr)1571 static void vc4_dsi_dma_chan_release(void *ptr)
1572 {
1573 	struct vc4_dsi *dsi = ptr;
1574 
1575 	dma_release_channel(dsi->reg_dma_chan);
1576 	dsi->reg_dma_chan = NULL;
1577 }
1578 
vc4_dsi_release(struct kref * kref)1579 static void vc4_dsi_release(struct kref *kref)
1580 {
1581 	struct vc4_dsi *dsi =
1582 		container_of(kref, struct vc4_dsi, kref);
1583 
1584 	kfree(dsi);
1585 }
1586 
vc4_dsi_get(struct vc4_dsi * dsi)1587 static void vc4_dsi_get(struct vc4_dsi *dsi)
1588 {
1589 	kref_get(&dsi->kref);
1590 }
1591 
vc4_dsi_put(struct vc4_dsi * dsi)1592 static void vc4_dsi_put(struct vc4_dsi *dsi)
1593 {
1594 	kref_put(&dsi->kref, &vc4_dsi_release);
1595 }
1596 
vc4_dsi_release_action(struct drm_device * drm,void * ptr)1597 static void vc4_dsi_release_action(struct drm_device *drm, void *ptr)
1598 {
1599 	struct vc4_dsi *dsi = ptr;
1600 
1601 	vc4_dsi_put(dsi);
1602 }
1603 
vc4_dsi_bind(struct device * dev,struct device * master,void * data)1604 static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1605 {
1606 	struct platform_device *pdev = to_platform_device(dev);
1607 	struct drm_device *drm = dev_get_drvdata(master);
1608 	struct vc4_dsi *dsi = dev_get_drvdata(dev);
1609 	struct drm_encoder *encoder = &dsi->encoder.base;
1610 	int ret;
1611 
1612 	vc4_dsi_get(dsi);
1613 
1614 	ret = drmm_add_action_or_reset(drm, vc4_dsi_release_action, dsi);
1615 	if (ret)
1616 		return ret;
1617 
1618 	dsi->variant = of_device_get_match_data(dev);
1619 
1620 	INIT_LIST_HEAD(&dsi->bridge_chain);
1621 	dsi->encoder.type = dsi->variant->port ?
1622 		VC4_ENCODER_TYPE_DSI1 : VC4_ENCODER_TYPE_DSI0;
1623 
1624 	dsi->regs = vc4_ioremap_regs(pdev, 0);
1625 	if (IS_ERR(dsi->regs))
1626 		return PTR_ERR(dsi->regs);
1627 
1628 	dsi->regset.base = dsi->regs;
1629 	dsi->regset.regs = dsi->variant->regs;
1630 	dsi->regset.nregs = dsi->variant->nregs;
1631 
1632 	if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1633 		dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1634 			DSI_PORT_READ(ID), DSI_ID_VALUE);
1635 		return -ENODEV;
1636 	}
1637 
1638 	/* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to
1639 	 * writes from the ARM.  It does handle writes from the DMA engine,
1640 	 * so set up a channel for talking to it.
1641 	 */
1642 	if (dsi->variant->broken_axi_workaround) {
1643 		dma_cap_mask_t dma_mask;
1644 
1645 		dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1646 						      &dsi->reg_dma_paddr,
1647 						      GFP_KERNEL);
1648 		if (!dsi->reg_dma_mem) {
1649 			DRM_ERROR("Failed to get DMA memory\n");
1650 			return -ENOMEM;
1651 		}
1652 
1653 		ret = devm_add_action_or_reset(dev, vc4_dsi_dma_mem_release, dsi);
1654 		if (ret)
1655 			return ret;
1656 
1657 		dma_cap_zero(dma_mask);
1658 		dma_cap_set(DMA_MEMCPY, dma_mask);
1659 
1660 		dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1661 		if (IS_ERR(dsi->reg_dma_chan)) {
1662 			ret = PTR_ERR(dsi->reg_dma_chan);
1663 			if (ret != -EPROBE_DEFER)
1664 				DRM_ERROR("Failed to get DMA channel: %d\n",
1665 					  ret);
1666 			return ret;
1667 		}
1668 
1669 		ret = devm_add_action_or_reset(dev, vc4_dsi_dma_chan_release, dsi);
1670 		if (ret)
1671 			return ret;
1672 
1673 		/* Get the physical address of the device's registers.  The
1674 		 * struct resource for the regs gives us the bus address
1675 		 * instead.
1676 		 */
1677 		dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1678 							     0, NULL, NULL));
1679 	}
1680 
1681 	init_completion(&dsi->xfer_completion);
1682 	/* At startup enable error-reporting interrupts and nothing else. */
1683 	DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1684 	/* Clear any existing interrupt state. */
1685 	DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1686 
1687 	if (dsi->reg_dma_mem)
1688 		ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1689 						vc4_dsi_irq_defer_to_thread_handler,
1690 						vc4_dsi_irq_handler,
1691 						IRQF_ONESHOT,
1692 						"vc4 dsi", dsi);
1693 	else
1694 		ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1695 				       vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1696 	if (ret) {
1697 		if (ret != -EPROBE_DEFER)
1698 			dev_err(dev, "Failed to get interrupt: %d\n", ret);
1699 		return ret;
1700 	}
1701 
1702 	dsi->escape_clock = devm_clk_get(dev, "escape");
1703 	if (IS_ERR(dsi->escape_clock)) {
1704 		ret = PTR_ERR(dsi->escape_clock);
1705 		if (ret != -EPROBE_DEFER)
1706 			dev_err(dev, "Failed to get escape clock: %d\n", ret);
1707 		return ret;
1708 	}
1709 
1710 	dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1711 	if (IS_ERR(dsi->pll_phy_clock)) {
1712 		ret = PTR_ERR(dsi->pll_phy_clock);
1713 		if (ret != -EPROBE_DEFER)
1714 			dev_err(dev, "Failed to get phy clock: %d\n", ret);
1715 		return ret;
1716 	}
1717 
1718 	dsi->pixel_clock = devm_clk_get(dev, "pixel");
1719 	if (IS_ERR(dsi->pixel_clock)) {
1720 		ret = PTR_ERR(dsi->pixel_clock);
1721 		if (ret != -EPROBE_DEFER)
1722 			dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1723 		return ret;
1724 	}
1725 
1726 	dsi->bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0);
1727 	if (IS_ERR(dsi->bridge))
1728 		return PTR_ERR(dsi->bridge);
1729 
1730 	/* The esc clock rate is supposed to always be 100Mhz. */
1731 	ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1732 	if (ret) {
1733 		dev_err(dev, "Failed to set esc clock: %d\n", ret);
1734 		return ret;
1735 	}
1736 
1737 	ret = vc4_dsi_init_phy_clocks(dsi);
1738 	if (ret)
1739 		return ret;
1740 
1741 	ret = drmm_encoder_init(drm, encoder,
1742 				&vc4_dsi_encoder_funcs,
1743 				DRM_MODE_ENCODER_DSI,
1744 				NULL);
1745 	if (ret)
1746 		return ret;
1747 
1748 	drm_encoder_helper_add(encoder, &vc4_dsi_encoder_helper_funcs);
1749 
1750 	ret = devm_pm_runtime_enable(dev);
1751 	if (ret)
1752 		return ret;
1753 
1754 	ret = drm_bridge_attach(encoder, dsi->bridge, NULL, 0);
1755 	if (ret)
1756 		return ret;
1757 	/* Disable the atomic helper calls into the bridge.  We
1758 	 * manually call the bridge pre_enable / enable / etc. calls
1759 	 * from our driver, since we need to sequence them within the
1760 	 * encoder's enable/disable paths.
1761 	 */
1762 	list_splice_init(&encoder->bridge_chain, &dsi->bridge_chain);
1763 
1764 	return 0;
1765 }
1766 
vc4_dsi_unbind(struct device * dev,struct device * master,void * data)1767 static void vc4_dsi_unbind(struct device *dev, struct device *master,
1768 			   void *data)
1769 {
1770 	struct vc4_dsi *dsi = dev_get_drvdata(dev);
1771 	struct drm_encoder *encoder = &dsi->encoder.base;
1772 
1773 	/*
1774 	 * Restore the bridge_chain so the bridge detach procedure can happen
1775 	 * normally.
1776 	 */
1777 	list_splice_init(&dsi->bridge_chain, &encoder->bridge_chain);
1778 }
1779 
1780 static const struct component_ops vc4_dsi_ops = {
1781 	.bind   = vc4_dsi_bind,
1782 	.unbind = vc4_dsi_unbind,
1783 };
1784 
vc4_dsi_dev_probe(struct platform_device * pdev)1785 static int vc4_dsi_dev_probe(struct platform_device *pdev)
1786 {
1787 	struct device *dev = &pdev->dev;
1788 	struct vc4_dsi *dsi;
1789 
1790 	dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1791 	if (!dsi)
1792 		return -ENOMEM;
1793 	dev_set_drvdata(dev, dsi);
1794 
1795 	kref_init(&dsi->kref);
1796 	dsi->pdev = pdev;
1797 	dsi->dsi_host.ops = &vc4_dsi_host_ops;
1798 	dsi->dsi_host.dev = dev;
1799 	mipi_dsi_host_register(&dsi->dsi_host);
1800 
1801 	return 0;
1802 }
1803 
vc4_dsi_dev_remove(struct platform_device * pdev)1804 static int vc4_dsi_dev_remove(struct platform_device *pdev)
1805 {
1806 	struct device *dev = &pdev->dev;
1807 	struct vc4_dsi *dsi = dev_get_drvdata(dev);
1808 
1809 	mipi_dsi_host_unregister(&dsi->dsi_host);
1810 	vc4_dsi_put(dsi);
1811 
1812 	return 0;
1813 }
1814 
1815 struct platform_driver vc4_dsi_driver = {
1816 	.probe = vc4_dsi_dev_probe,
1817 	.remove = vc4_dsi_dev_remove,
1818 	.driver = {
1819 		.name = "vc4_dsi",
1820 		.of_match_table = vc4_dsi_dt_match,
1821 	},
1822 };
1823