1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 
6 #include "i915_drv.h"
7 #include "i915_reg.h"
8 #include "intel_gt.h"
9 #include "intel_gt_clock_utils.h"
10 #include "intel_gt_regs.h"
11 
read_reference_ts_freq(struct intel_uncore * uncore)12 static u32 read_reference_ts_freq(struct intel_uncore *uncore)
13 {
14 	u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE);
15 	u32 base_freq, frac_freq;
16 
17 	base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
18 		     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
19 	base_freq *= 1000000;
20 
21 	frac_freq = ((ts_override &
22 		      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
23 		     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
24 	frac_freq = 1000000 / (frac_freq + 1);
25 
26 	return base_freq + frac_freq;
27 }
28 
gen11_get_crystal_clock_freq(struct intel_uncore * uncore,u32 rpm_config_reg)29 static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,
30 					u32 rpm_config_reg)
31 {
32 	u32 f19_2_mhz = 19200000;
33 	u32 f24_mhz = 24000000;
34 	u32 f25_mhz = 25000000;
35 	u32 f38_4_mhz = 38400000;
36 	u32 crystal_clock =
37 		(rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
38 		GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
39 
40 	switch (crystal_clock) {
41 	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
42 		return f24_mhz;
43 	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
44 		return f19_2_mhz;
45 	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
46 		return f38_4_mhz;
47 	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
48 		return f25_mhz;
49 	default:
50 		MISSING_CASE(crystal_clock);
51 		return 0;
52 	}
53 }
54 
gen11_read_clock_frequency(struct intel_uncore * uncore)55 static u32 gen11_read_clock_frequency(struct intel_uncore *uncore)
56 {
57 	u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
58 	u32 freq = 0;
59 
60 	/*
61 	 * Note that on gen11+, the clock frequency may be reconfigured.
62 	 * We do not, and we assume nobody else does.
63 	 *
64 	 * First figure out the reference frequency. There are 2 ways
65 	 * we can compute the frequency, either through the
66 	 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
67 	 * tells us which one we should use.
68 	 */
69 	if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
70 		freq = read_reference_ts_freq(uncore);
71 	} else {
72 		u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
73 
74 		freq = gen11_get_crystal_clock_freq(uncore, c0);
75 
76 		/*
77 		 * Now figure out how the command stream's timestamp
78 		 * register increments from this frequency (it might
79 		 * increment only every few clock cycle).
80 		 */
81 		freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
82 			      GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
83 	}
84 
85 	return freq;
86 }
87 
gen9_read_clock_frequency(struct intel_uncore * uncore)88 static u32 gen9_read_clock_frequency(struct intel_uncore *uncore)
89 {
90 	u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
91 	u32 freq = 0;
92 
93 	if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
94 		freq = read_reference_ts_freq(uncore);
95 	} else {
96 		freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000;
97 
98 		/*
99 		 * Now figure out how the command stream's timestamp
100 		 * register increments from this frequency (it might
101 		 * increment only every few clock cycle).
102 		 */
103 		freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
104 			      CTC_SHIFT_PARAMETER_SHIFT);
105 	}
106 
107 	return freq;
108 }
109 
gen5_read_clock_frequency(struct intel_uncore * uncore)110 static u32 gen5_read_clock_frequency(struct intel_uncore *uncore)
111 {
112 	/*
113 	 * PRMs say:
114 	 *
115 	 *     "The PCU TSC counts 10ns increments; this timestamp
116 	 *      reflects bits 38:3 of the TSC (i.e. 80ns granularity,
117 	 *      rolling over every 1.5 hours).
118 	 */
119 	return 12500000;
120 }
121 
gen2_read_clock_frequency(struct intel_uncore * uncore)122 static u32 gen2_read_clock_frequency(struct intel_uncore *uncore)
123 {
124 	/*
125 	 * PRMs say:
126 	 *
127 	 *     "The value in this register increments once every 16
128 	 *      hclks." (through the “Clocking Configuration”
129 	 *      (“CLKCFG”) MCHBAR register)
130 	 */
131 	return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
132 }
133 
read_clock_frequency(struct intel_uncore * uncore)134 static u32 read_clock_frequency(struct intel_uncore *uncore)
135 {
136 	if (GRAPHICS_VER(uncore->i915) >= 11)
137 		return gen11_read_clock_frequency(uncore);
138 	else if (GRAPHICS_VER(uncore->i915) >= 9)
139 		return gen9_read_clock_frequency(uncore);
140 	else if (GRAPHICS_VER(uncore->i915) >= 5)
141 		return gen5_read_clock_frequency(uncore);
142 	else
143 		return gen2_read_clock_frequency(uncore);
144 }
145 
intel_gt_init_clock_frequency(struct intel_gt * gt)146 void intel_gt_init_clock_frequency(struct intel_gt *gt)
147 {
148 	gt->clock_frequency = read_clock_frequency(gt->uncore);
149 
150 	/* Icelake appears to use another fixed frequency for CTX_TIMESTAMP */
151 	if (GRAPHICS_VER(gt->i915) == 11)
152 		gt->clock_period_ns = NSEC_PER_SEC / 13750000;
153 	else if (gt->clock_frequency)
154 		gt->clock_period_ns = intel_gt_clock_interval_to_ns(gt, 1);
155 
156 	GT_TRACE(gt,
157 		 "Using clock frequency: %dkHz, period: %dns, wrap: %lldms\n",
158 		 gt->clock_frequency / 1000,
159 		 gt->clock_period_ns,
160 		 div_u64(mul_u32_u32(gt->clock_period_ns, S32_MAX),
161 			 USEC_PER_SEC));
162 }
163 
164 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
intel_gt_check_clock_frequency(const struct intel_gt * gt)165 void intel_gt_check_clock_frequency(const struct intel_gt *gt)
166 {
167 	if (gt->clock_frequency != read_clock_frequency(gt->uncore)) {
168 		dev_err(gt->i915->drm.dev,
169 			"GT clock frequency changed, was %uHz, now %uHz!\n",
170 			gt->clock_frequency,
171 			read_clock_frequency(gt->uncore));
172 	}
173 }
174 #endif
175 
div_u64_roundup(u64 nom,u32 den)176 static u64 div_u64_roundup(u64 nom, u32 den)
177 {
178 	return div_u64(nom + den - 1, den);
179 }
180 
intel_gt_clock_interval_to_ns(const struct intel_gt * gt,u64 count)181 u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count)
182 {
183 	return div_u64_roundup(count * NSEC_PER_SEC, gt->clock_frequency);
184 }
185 
intel_gt_pm_interval_to_ns(const struct intel_gt * gt,u64 count)186 u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count)
187 {
188 	return intel_gt_clock_interval_to_ns(gt, 16 * count);
189 }
190 
intel_gt_ns_to_clock_interval(const struct intel_gt * gt,u64 ns)191 u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns)
192 {
193 	return div_u64_roundup(gt->clock_frequency * ns, NSEC_PER_SEC);
194 }
195 
intel_gt_ns_to_pm_interval(const struct intel_gt * gt,u64 ns)196 u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)
197 {
198 	u64 val;
199 
200 	/*
201 	 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
202 	 * 8300) freezing up around GPU hangs. Looks as if even
203 	 * scheduling/timer interrupts start misbehaving if the RPS
204 	 * EI/thresholds are "bad", leading to a very sluggish or even
205 	 * frozen machine.
206 	 */
207 	val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16);
208 	if (GRAPHICS_VER(gt->i915) == 6)
209 		val = div_u64_roundup(val, 25) * 25;
210 
211 	return val;
212 }
213