1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2015-2018 Etnaviv Project
4 */
5
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/delay.h>
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/thermal.h>
17
18 #include "etnaviv_cmdbuf.h"
19 #include "etnaviv_dump.h"
20 #include "etnaviv_gpu.h"
21 #include "etnaviv_gem.h"
22 #include "etnaviv_mmu.h"
23 #include "etnaviv_perfmon.h"
24 #include "etnaviv_sched.h"
25 #include "common.xml.h"
26 #include "state.xml.h"
27 #include "state_hi.xml.h"
28 #include "cmdstream.xml.h"
29
30 static const struct platform_device_id gpu_ids[] = {
31 { .name = "etnaviv-gpu,2d" },
32 { },
33 };
34
35 /*
36 * Driver functions:
37 */
38
etnaviv_gpu_get_param(struct etnaviv_gpu * gpu,u32 param,u64 * value)39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
40 {
41 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
42
43 switch (param) {
44 case ETNAVIV_PARAM_GPU_MODEL:
45 *value = gpu->identity.model;
46 break;
47
48 case ETNAVIV_PARAM_GPU_REVISION:
49 *value = gpu->identity.revision;
50 break;
51
52 case ETNAVIV_PARAM_GPU_FEATURES_0:
53 *value = gpu->identity.features;
54 break;
55
56 case ETNAVIV_PARAM_GPU_FEATURES_1:
57 *value = gpu->identity.minor_features0;
58 break;
59
60 case ETNAVIV_PARAM_GPU_FEATURES_2:
61 *value = gpu->identity.minor_features1;
62 break;
63
64 case ETNAVIV_PARAM_GPU_FEATURES_3:
65 *value = gpu->identity.minor_features2;
66 break;
67
68 case ETNAVIV_PARAM_GPU_FEATURES_4:
69 *value = gpu->identity.minor_features3;
70 break;
71
72 case ETNAVIV_PARAM_GPU_FEATURES_5:
73 *value = gpu->identity.minor_features4;
74 break;
75
76 case ETNAVIV_PARAM_GPU_FEATURES_6:
77 *value = gpu->identity.minor_features5;
78 break;
79
80 case ETNAVIV_PARAM_GPU_FEATURES_7:
81 *value = gpu->identity.minor_features6;
82 break;
83
84 case ETNAVIV_PARAM_GPU_FEATURES_8:
85 *value = gpu->identity.minor_features7;
86 break;
87
88 case ETNAVIV_PARAM_GPU_FEATURES_9:
89 *value = gpu->identity.minor_features8;
90 break;
91
92 case ETNAVIV_PARAM_GPU_FEATURES_10:
93 *value = gpu->identity.minor_features9;
94 break;
95
96 case ETNAVIV_PARAM_GPU_FEATURES_11:
97 *value = gpu->identity.minor_features10;
98 break;
99
100 case ETNAVIV_PARAM_GPU_FEATURES_12:
101 *value = gpu->identity.minor_features11;
102 break;
103
104 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
105 *value = gpu->identity.stream_count;
106 break;
107
108 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
109 *value = gpu->identity.register_max;
110 break;
111
112 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
113 *value = gpu->identity.thread_count;
114 break;
115
116 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
117 *value = gpu->identity.vertex_cache_size;
118 break;
119
120 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
121 *value = gpu->identity.shader_core_count;
122 break;
123
124 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
125 *value = gpu->identity.pixel_pipes;
126 break;
127
128 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
129 *value = gpu->identity.vertex_output_buffer_size;
130 break;
131
132 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
133 *value = gpu->identity.buffer_size;
134 break;
135
136 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
137 *value = gpu->identity.instruction_count;
138 break;
139
140 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
141 *value = gpu->identity.num_constants;
142 break;
143
144 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
145 *value = gpu->identity.varyings_count;
146 break;
147
148 case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
149 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
150 *value = ETNAVIV_SOFTPIN_START_ADDRESS;
151 else
152 *value = ~0ULL;
153 break;
154
155 case ETNAVIV_PARAM_GPU_PRODUCT_ID:
156 *value = gpu->identity.product_id;
157 break;
158
159 case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
160 *value = gpu->identity.customer_id;
161 break;
162
163 case ETNAVIV_PARAM_GPU_ECO_ID:
164 *value = gpu->identity.eco_id;
165 break;
166
167 default:
168 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
169 return -EINVAL;
170 }
171
172 return 0;
173 }
174
175
176 #define etnaviv_is_model_rev(gpu, mod, rev) \
177 ((gpu)->identity.model == chipModel_##mod && \
178 (gpu)->identity.revision == rev)
179 #define etnaviv_field(val, field) \
180 (((val) & field##__MASK) >> field##__SHIFT)
181
etnaviv_hw_specs(struct etnaviv_gpu * gpu)182 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
183 {
184 if (gpu->identity.minor_features0 &
185 chipMinorFeatures0_MORE_MINOR_FEATURES) {
186 u32 specs[4];
187 unsigned int streams;
188
189 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
190 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
191 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
192 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
193
194 gpu->identity.stream_count = etnaviv_field(specs[0],
195 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
196 gpu->identity.register_max = etnaviv_field(specs[0],
197 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
198 gpu->identity.thread_count = etnaviv_field(specs[0],
199 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
200 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
201 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
202 gpu->identity.shader_core_count = etnaviv_field(specs[0],
203 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
204 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
205 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
206 gpu->identity.vertex_output_buffer_size =
207 etnaviv_field(specs[0],
208 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
209
210 gpu->identity.buffer_size = etnaviv_field(specs[1],
211 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
212 gpu->identity.instruction_count = etnaviv_field(specs[1],
213 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
214 gpu->identity.num_constants = etnaviv_field(specs[1],
215 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
216
217 gpu->identity.varyings_count = etnaviv_field(specs[2],
218 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
219
220 /* This overrides the value from older register if non-zero */
221 streams = etnaviv_field(specs[3],
222 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
223 if (streams)
224 gpu->identity.stream_count = streams;
225 }
226
227 /* Fill in the stream count if not specified */
228 if (gpu->identity.stream_count == 0) {
229 if (gpu->identity.model >= 0x1000)
230 gpu->identity.stream_count = 4;
231 else
232 gpu->identity.stream_count = 1;
233 }
234
235 /* Convert the register max value */
236 if (gpu->identity.register_max)
237 gpu->identity.register_max = 1 << gpu->identity.register_max;
238 else if (gpu->identity.model == chipModel_GC400)
239 gpu->identity.register_max = 32;
240 else
241 gpu->identity.register_max = 64;
242
243 /* Convert thread count */
244 if (gpu->identity.thread_count)
245 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
246 else if (gpu->identity.model == chipModel_GC400)
247 gpu->identity.thread_count = 64;
248 else if (gpu->identity.model == chipModel_GC500 ||
249 gpu->identity.model == chipModel_GC530)
250 gpu->identity.thread_count = 128;
251 else
252 gpu->identity.thread_count = 256;
253
254 if (gpu->identity.vertex_cache_size == 0)
255 gpu->identity.vertex_cache_size = 8;
256
257 if (gpu->identity.shader_core_count == 0) {
258 if (gpu->identity.model >= 0x1000)
259 gpu->identity.shader_core_count = 2;
260 else
261 gpu->identity.shader_core_count = 1;
262 }
263
264 if (gpu->identity.pixel_pipes == 0)
265 gpu->identity.pixel_pipes = 1;
266
267 /* Convert virtex buffer size */
268 if (gpu->identity.vertex_output_buffer_size) {
269 gpu->identity.vertex_output_buffer_size =
270 1 << gpu->identity.vertex_output_buffer_size;
271 } else if (gpu->identity.model == chipModel_GC400) {
272 if (gpu->identity.revision < 0x4000)
273 gpu->identity.vertex_output_buffer_size = 512;
274 else if (gpu->identity.revision < 0x4200)
275 gpu->identity.vertex_output_buffer_size = 256;
276 else
277 gpu->identity.vertex_output_buffer_size = 128;
278 } else {
279 gpu->identity.vertex_output_buffer_size = 512;
280 }
281
282 switch (gpu->identity.instruction_count) {
283 case 0:
284 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
285 gpu->identity.model == chipModel_GC880)
286 gpu->identity.instruction_count = 512;
287 else
288 gpu->identity.instruction_count = 256;
289 break;
290
291 case 1:
292 gpu->identity.instruction_count = 1024;
293 break;
294
295 case 2:
296 gpu->identity.instruction_count = 2048;
297 break;
298
299 default:
300 gpu->identity.instruction_count = 256;
301 break;
302 }
303
304 if (gpu->identity.num_constants == 0)
305 gpu->identity.num_constants = 168;
306
307 if (gpu->identity.varyings_count == 0) {
308 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
309 gpu->identity.varyings_count = 12;
310 else
311 gpu->identity.varyings_count = 8;
312 }
313
314 /*
315 * For some cores, two varyings are consumed for position, so the
316 * maximum varying count needs to be reduced by one.
317 */
318 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
319 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
320 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
321 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
322 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
323 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
324 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
325 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
326 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
327 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
328 etnaviv_is_model_rev(gpu, GC880, 0x5106))
329 gpu->identity.varyings_count -= 1;
330 }
331
etnaviv_hw_identify(struct etnaviv_gpu * gpu)332 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
333 {
334 u32 chipIdentity;
335
336 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
337
338 /* Special case for older graphic cores. */
339 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
340 gpu->identity.model = chipModel_GC500;
341 gpu->identity.revision = etnaviv_field(chipIdentity,
342 VIVS_HI_CHIP_IDENTITY_REVISION);
343 } else {
344 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
345
346 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
347 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
348 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
349
350 /*
351 * Reading these two registers on GC600 rev 0x19 result in a
352 * unhandled fault: external abort on non-linefetch
353 */
354 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
355 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
356 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
357 }
358
359 /*
360 * !!!! HACK ALERT !!!!
361 * Because people change device IDs without letting software
362 * know about it - here is the hack to make it all look the
363 * same. Only for GC400 family.
364 */
365 if ((gpu->identity.model & 0xff00) == 0x0400 &&
366 gpu->identity.model != chipModel_GC420) {
367 gpu->identity.model = gpu->identity.model & 0x0400;
368 }
369
370 /* Another special case */
371 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
372 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
373
374 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
375 /*
376 * This IP has an ECO; put the correct
377 * revision in it.
378 */
379 gpu->identity.revision = 0x1051;
380 }
381 }
382
383 /*
384 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
385 * reality it's just a re-branded GC3000. We can identify this
386 * core by the upper half of the revision register being all 1.
387 * Fix model/rev here, so all other places can refer to this
388 * core by its real identity.
389 */
390 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
391 gpu->identity.model = chipModel_GC3000;
392 gpu->identity.revision &= 0xffff;
393 }
394
395 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
396 gpu->identity.eco_id = 1;
397
398 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
399 gpu->identity.eco_id = 1;
400 }
401
402 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
403 gpu->identity.model, gpu->identity.revision);
404
405 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
406 /*
407 * If there is a match in the HWDB, we aren't interested in the
408 * remaining register values, as they might be wrong.
409 */
410 if (etnaviv_fill_identity_from_hwdb(gpu))
411 return;
412
413 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
414
415 /* Disable fast clear on GC700. */
416 if (gpu->identity.model == chipModel_GC700)
417 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
418
419 /* These models/revisions don't have the 2D pipe bit */
420 if ((gpu->identity.model == chipModel_GC500 &&
421 gpu->identity.revision <= 2) ||
422 gpu->identity.model == chipModel_GC300)
423 gpu->identity.features |= chipFeatures_PIPE_2D;
424
425 if ((gpu->identity.model == chipModel_GC500 &&
426 gpu->identity.revision < 2) ||
427 (gpu->identity.model == chipModel_GC300 &&
428 gpu->identity.revision < 0x2000)) {
429
430 /*
431 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
432 * registers.
433 */
434 gpu->identity.minor_features0 = 0;
435 gpu->identity.minor_features1 = 0;
436 gpu->identity.minor_features2 = 0;
437 gpu->identity.minor_features3 = 0;
438 gpu->identity.minor_features4 = 0;
439 gpu->identity.minor_features5 = 0;
440 } else
441 gpu->identity.minor_features0 =
442 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
443
444 if (gpu->identity.minor_features0 &
445 chipMinorFeatures0_MORE_MINOR_FEATURES) {
446 gpu->identity.minor_features1 =
447 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
448 gpu->identity.minor_features2 =
449 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
450 gpu->identity.minor_features3 =
451 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
452 gpu->identity.minor_features4 =
453 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
454 gpu->identity.minor_features5 =
455 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
456 }
457
458 /* GC600/300 idle register reports zero bits where modules aren't present */
459 if (gpu->identity.model == chipModel_GC600 ||
460 gpu->identity.model == chipModel_GC300)
461 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
462 VIVS_HI_IDLE_STATE_RA |
463 VIVS_HI_IDLE_STATE_SE |
464 VIVS_HI_IDLE_STATE_PA |
465 VIVS_HI_IDLE_STATE_SH |
466 VIVS_HI_IDLE_STATE_PE |
467 VIVS_HI_IDLE_STATE_DE |
468 VIVS_HI_IDLE_STATE_FE;
469
470 etnaviv_hw_specs(gpu);
471 }
472
etnaviv_gpu_load_clock(struct etnaviv_gpu * gpu,u32 clock)473 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
474 {
475 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
476 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
478 }
479
etnaviv_gpu_update_clock(struct etnaviv_gpu * gpu)480 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
481 {
482 if (gpu->identity.minor_features2 &
483 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
484 clk_set_rate(gpu->clk_core,
485 gpu->base_rate_core >> gpu->freq_scale);
486 clk_set_rate(gpu->clk_shader,
487 gpu->base_rate_shader >> gpu->freq_scale);
488 } else {
489 unsigned int fscale = 1 << (6 - gpu->freq_scale);
490 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
491
492 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
493 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
494 etnaviv_gpu_load_clock(gpu, clock);
495 }
496 }
497
etnaviv_hw_reset(struct etnaviv_gpu * gpu)498 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
499 {
500 u32 control, idle;
501 unsigned long timeout;
502 bool failed = true;
503
504 /* We hope that the GPU resets in under one second */
505 timeout = jiffies + msecs_to_jiffies(1000);
506
507 while (time_is_after_jiffies(timeout)) {
508 /* enable clock */
509 unsigned int fscale = 1 << (6 - gpu->freq_scale);
510 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
511 etnaviv_gpu_load_clock(gpu, control);
512
513 /* isolate the GPU. */
514 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
515 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
516
517 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
518 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
519 VIVS_MMUv2_AHB_CONTROL_RESET);
520 } else {
521 /* set soft reset. */
522 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
523 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
524 }
525
526 /* wait for reset. */
527 usleep_range(10, 20);
528
529 /* reset soft reset bit. */
530 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
531 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
532
533 /* reset GPU isolation. */
534 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
535 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
536
537 /* read idle register. */
538 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
539
540 /* try resetting again if FE is not idle */
541 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
542 dev_dbg(gpu->dev, "FE is not idle\n");
543 continue;
544 }
545
546 /* read reset register. */
547 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
548
549 /* is the GPU idle? */
550 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
551 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
552 dev_dbg(gpu->dev, "GPU is not idle\n");
553 continue;
554 }
555
556 /* disable debug registers, as they are not normally needed */
557 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
558 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
559
560 failed = false;
561 break;
562 }
563
564 if (failed) {
565 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
566 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
567
568 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
569 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
570 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
571 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
572
573 return -EBUSY;
574 }
575
576 /* We rely on the GPU running, so program the clock */
577 etnaviv_gpu_update_clock(gpu);
578
579 gpu->fe_running = false;
580 gpu->exec_state = -1;
581 if (gpu->mmu_context)
582 etnaviv_iommu_context_put(gpu->mmu_context);
583 gpu->mmu_context = NULL;
584
585 return 0;
586 }
587
etnaviv_gpu_enable_mlcg(struct etnaviv_gpu * gpu)588 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
589 {
590 u32 pmc, ppc;
591
592 /* enable clock gating */
593 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
594 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
595
596 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
597 if (gpu->identity.revision == 0x4301 ||
598 gpu->identity.revision == 0x4302)
599 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
600
601 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
602
603 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
604
605 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
606 if (gpu->identity.model >= chipModel_GC400 &&
607 gpu->identity.model != chipModel_GC420 &&
608 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
609 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
610
611 /*
612 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
613 * present without a bug fix.
614 */
615 if (gpu->identity.revision < 0x5000 &&
616 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
617 !(gpu->identity.minor_features1 &
618 chipMinorFeatures1_DISABLE_PE_GATING))
619 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
620
621 if (gpu->identity.revision < 0x5422)
622 pmc |= BIT(15); /* Unknown bit */
623
624 /* Disable TX clock gating on affected core revisions. */
625 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
626 etnaviv_is_model_rev(gpu, GC2000, 0x5108))
627 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
628
629 /* Disable SE, RA and TX clock gating on affected core revisions. */
630 if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
631 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
632 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA |
633 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
634
635 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
636 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
637
638 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
639 }
640
etnaviv_gpu_start_fe(struct etnaviv_gpu * gpu,u32 address,u16 prefetch)641 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
642 {
643 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
644 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
645 VIVS_FE_COMMAND_CONTROL_ENABLE |
646 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
647
648 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
649 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
650 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
651 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
652 }
653
654 gpu->fe_running = true;
655 }
656
etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu * gpu,struct etnaviv_iommu_context * context)657 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
658 struct etnaviv_iommu_context *context)
659 {
660 u16 prefetch;
661 u32 address;
662
663 /* setup the MMU */
664 etnaviv_iommu_restore(gpu, context);
665
666 /* Start command processor */
667 prefetch = etnaviv_buffer_init(gpu);
668 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
669 &gpu->mmu_context->cmdbuf_mapping);
670
671 etnaviv_gpu_start_fe(gpu, address, prefetch);
672 }
673
etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu * gpu)674 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
675 {
676 /*
677 * Base value for VIVS_PM_PULSE_EATER register on models where it
678 * cannot be read, extracted from vivante kernel driver.
679 */
680 u32 pulse_eater = 0x01590880;
681
682 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
683 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
684 pulse_eater |= BIT(23);
685
686 }
687
688 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
689 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
690 pulse_eater &= ~BIT(16);
691 pulse_eater |= BIT(17);
692 }
693
694 if ((gpu->identity.revision > 0x5420) &&
695 (gpu->identity.features & chipFeatures_PIPE_3D))
696 {
697 /* Performance fix: disable internal DFS */
698 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
699 pulse_eater |= BIT(18);
700 }
701
702 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
703 }
704
etnaviv_gpu_hw_init(struct etnaviv_gpu * gpu)705 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
706 {
707 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
708 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
709 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
710 u32 mc_memory_debug;
711
712 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
713
714 if (gpu->identity.revision == 0x5007)
715 mc_memory_debug |= 0x0c;
716 else
717 mc_memory_debug |= 0x08;
718
719 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
720 }
721
722 /* enable module-level clock gating */
723 etnaviv_gpu_enable_mlcg(gpu);
724
725 /*
726 * Update GPU AXI cache atttribute to "cacheable, no allocate".
727 * This is necessary to prevent the iMX6 SoC locking up.
728 */
729 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
730 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
731 VIVS_HI_AXI_CONFIG_ARCACHE(2));
732
733 /* GC2000 rev 5108 needs a special bus config */
734 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
735 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
736 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
737 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
738 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
739 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
740 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
741 }
742
743 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
744 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
745 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
746 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
747 }
748
749 /* setup the pulse eater */
750 etnaviv_gpu_setup_pulse_eater(gpu);
751
752 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
753 }
754
etnaviv_gpu_init(struct etnaviv_gpu * gpu)755 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
756 {
757 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
758 dma_addr_t cmdbuf_paddr;
759 int ret, i;
760
761 ret = pm_runtime_get_sync(gpu->dev);
762 if (ret < 0) {
763 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
764 goto pm_put;
765 }
766
767 etnaviv_hw_identify(gpu);
768
769 if (gpu->identity.model == 0) {
770 dev_err(gpu->dev, "Unknown GPU model\n");
771 ret = -ENXIO;
772 goto fail;
773 }
774
775 /* Exclude VG cores with FE2.0 */
776 if (gpu->identity.features & chipFeatures_PIPE_VG &&
777 gpu->identity.features & chipFeatures_FE20) {
778 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
779 ret = -ENXIO;
780 goto fail;
781 }
782
783 /*
784 * On cores with security features supported, we claim control over the
785 * security states.
786 */
787 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
788 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
789 gpu->sec_mode = ETNA_SEC_KERNEL;
790
791 ret = etnaviv_hw_reset(gpu);
792 if (ret) {
793 dev_err(gpu->dev, "GPU reset failed\n");
794 goto fail;
795 }
796
797 ret = etnaviv_iommu_global_init(gpu);
798 if (ret)
799 goto fail;
800
801 /*
802 * If the GPU is part of a system with DMA addressing limitations,
803 * request pages for our SHM backend buffers from the DMA32 zone to
804 * hopefully avoid performance killing SWIOTLB bounce buffering.
805 */
806 if (dma_addressing_limited(gpu->dev))
807 priv->shm_gfp_mask |= GFP_DMA32;
808
809 /* Create buffer: */
810 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
811 PAGE_SIZE);
812 if (ret) {
813 dev_err(gpu->dev, "could not create command buffer\n");
814 goto fail;
815 }
816
817 /*
818 * Set the GPU linear window to cover the cmdbuf region, as the GPU
819 * won't be able to start execution otherwise. The alignment to 128M is
820 * chosen arbitrarily but helps in debugging, as the MMU offset
821 * calculations are much more straight forward this way.
822 *
823 * On MC1.0 cores the linear window offset is ignored by the TS engine,
824 * leading to inconsistent memory views. Avoid using the offset on those
825 * cores if possible, otherwise disable the TS feature.
826 */
827 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
828
829 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
830 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
831 if (cmdbuf_paddr >= SZ_2G)
832 priv->mmu_global->memory_base = SZ_2G;
833 else
834 priv->mmu_global->memory_base = cmdbuf_paddr;
835 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
836 dev_info(gpu->dev,
837 "Need to move linear window on MC1.0, disabling TS\n");
838 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
839 priv->mmu_global->memory_base = SZ_2G;
840 }
841
842 /* Setup event management */
843 spin_lock_init(&gpu->event_spinlock);
844 init_completion(&gpu->event_free);
845 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
846 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
847 complete(&gpu->event_free);
848
849 /* Now program the hardware */
850 mutex_lock(&gpu->lock);
851 etnaviv_gpu_hw_init(gpu);
852 mutex_unlock(&gpu->lock);
853
854 pm_runtime_mark_last_busy(gpu->dev);
855 pm_runtime_put_autosuspend(gpu->dev);
856
857 gpu->initialized = true;
858
859 return 0;
860
861 fail:
862 pm_runtime_mark_last_busy(gpu->dev);
863 pm_put:
864 pm_runtime_put_autosuspend(gpu->dev);
865
866 return ret;
867 }
868
869 #ifdef CONFIG_DEBUG_FS
870 struct dma_debug {
871 u32 address[2];
872 u32 state[2];
873 };
874
verify_dma(struct etnaviv_gpu * gpu,struct dma_debug * debug)875 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
876 {
877 u32 i;
878
879 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
880 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
881
882 for (i = 0; i < 500; i++) {
883 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
884 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
885
886 if (debug->address[0] != debug->address[1])
887 break;
888
889 if (debug->state[0] != debug->state[1])
890 break;
891 }
892 }
893
etnaviv_gpu_debugfs(struct etnaviv_gpu * gpu,struct seq_file * m)894 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
895 {
896 struct dma_debug debug;
897 u32 dma_lo, dma_hi, axi, idle;
898 int ret;
899
900 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
901
902 ret = pm_runtime_get_sync(gpu->dev);
903 if (ret < 0)
904 goto pm_put;
905
906 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
907 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
908 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
909 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
910
911 verify_dma(gpu, &debug);
912
913 seq_puts(m, "\tidentity\n");
914 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
915 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
916 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
917 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
918 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
919
920 seq_puts(m, "\tfeatures\n");
921 seq_printf(m, "\t major_features: 0x%08x\n",
922 gpu->identity.features);
923 seq_printf(m, "\t minor_features0: 0x%08x\n",
924 gpu->identity.minor_features0);
925 seq_printf(m, "\t minor_features1: 0x%08x\n",
926 gpu->identity.minor_features1);
927 seq_printf(m, "\t minor_features2: 0x%08x\n",
928 gpu->identity.minor_features2);
929 seq_printf(m, "\t minor_features3: 0x%08x\n",
930 gpu->identity.minor_features3);
931 seq_printf(m, "\t minor_features4: 0x%08x\n",
932 gpu->identity.minor_features4);
933 seq_printf(m, "\t minor_features5: 0x%08x\n",
934 gpu->identity.minor_features5);
935 seq_printf(m, "\t minor_features6: 0x%08x\n",
936 gpu->identity.minor_features6);
937 seq_printf(m, "\t minor_features7: 0x%08x\n",
938 gpu->identity.minor_features7);
939 seq_printf(m, "\t minor_features8: 0x%08x\n",
940 gpu->identity.minor_features8);
941 seq_printf(m, "\t minor_features9: 0x%08x\n",
942 gpu->identity.minor_features9);
943 seq_printf(m, "\t minor_features10: 0x%08x\n",
944 gpu->identity.minor_features10);
945 seq_printf(m, "\t minor_features11: 0x%08x\n",
946 gpu->identity.minor_features11);
947
948 seq_puts(m, "\tspecs\n");
949 seq_printf(m, "\t stream_count: %d\n",
950 gpu->identity.stream_count);
951 seq_printf(m, "\t register_max: %d\n",
952 gpu->identity.register_max);
953 seq_printf(m, "\t thread_count: %d\n",
954 gpu->identity.thread_count);
955 seq_printf(m, "\t vertex_cache_size: %d\n",
956 gpu->identity.vertex_cache_size);
957 seq_printf(m, "\t shader_core_count: %d\n",
958 gpu->identity.shader_core_count);
959 seq_printf(m, "\t pixel_pipes: %d\n",
960 gpu->identity.pixel_pipes);
961 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
962 gpu->identity.vertex_output_buffer_size);
963 seq_printf(m, "\t buffer_size: %d\n",
964 gpu->identity.buffer_size);
965 seq_printf(m, "\t instruction_count: %d\n",
966 gpu->identity.instruction_count);
967 seq_printf(m, "\t num_constants: %d\n",
968 gpu->identity.num_constants);
969 seq_printf(m, "\t varyings_count: %d\n",
970 gpu->identity.varyings_count);
971
972 seq_printf(m, "\taxi: 0x%08x\n", axi);
973 seq_printf(m, "\tidle: 0x%08x\n", idle);
974 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
975 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
976 seq_puts(m, "\t FE is not idle\n");
977 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
978 seq_puts(m, "\t DE is not idle\n");
979 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
980 seq_puts(m, "\t PE is not idle\n");
981 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
982 seq_puts(m, "\t SH is not idle\n");
983 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
984 seq_puts(m, "\t PA is not idle\n");
985 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
986 seq_puts(m, "\t SE is not idle\n");
987 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
988 seq_puts(m, "\t RA is not idle\n");
989 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
990 seq_puts(m, "\t TX is not idle\n");
991 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
992 seq_puts(m, "\t VG is not idle\n");
993 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
994 seq_puts(m, "\t IM is not idle\n");
995 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
996 seq_puts(m, "\t FP is not idle\n");
997 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
998 seq_puts(m, "\t TS is not idle\n");
999 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
1000 seq_puts(m, "\t BL is not idle\n");
1001 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
1002 seq_puts(m, "\t ASYNCFE is not idle\n");
1003 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
1004 seq_puts(m, "\t MC is not idle\n");
1005 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
1006 seq_puts(m, "\t PPA is not idle\n");
1007 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
1008 seq_puts(m, "\t WD is not idle\n");
1009 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
1010 seq_puts(m, "\t NN is not idle\n");
1011 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
1012 seq_puts(m, "\t TP is not idle\n");
1013 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
1014 seq_puts(m, "\t AXI low power mode\n");
1015
1016 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
1017 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1018 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1019 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1020
1021 seq_puts(m, "\tMC\n");
1022 seq_printf(m, "\t read0: 0x%08x\n", read0);
1023 seq_printf(m, "\t read1: 0x%08x\n", read1);
1024 seq_printf(m, "\t write: 0x%08x\n", write);
1025 }
1026
1027 seq_puts(m, "\tDMA ");
1028
1029 if (debug.address[0] == debug.address[1] &&
1030 debug.state[0] == debug.state[1]) {
1031 seq_puts(m, "seems to be stuck\n");
1032 } else if (debug.address[0] == debug.address[1]) {
1033 seq_puts(m, "address is constant\n");
1034 } else {
1035 seq_puts(m, "is running\n");
1036 }
1037
1038 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1039 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1040 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1041 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1042 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1043 dma_lo, dma_hi);
1044
1045 ret = 0;
1046
1047 pm_runtime_mark_last_busy(gpu->dev);
1048 pm_put:
1049 pm_runtime_put_autosuspend(gpu->dev);
1050
1051 return ret;
1052 }
1053 #endif
1054
etnaviv_gpu_recover_hang(struct etnaviv_gpu * gpu)1055 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
1056 {
1057 unsigned int i;
1058
1059 dev_err(gpu->dev, "recover hung GPU!\n");
1060
1061 if (pm_runtime_get_sync(gpu->dev) < 0)
1062 goto pm_put;
1063
1064 mutex_lock(&gpu->lock);
1065
1066 etnaviv_hw_reset(gpu);
1067
1068 /* complete all events, the GPU won't do it after the reset */
1069 spin_lock(&gpu->event_spinlock);
1070 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1071 complete(&gpu->event_free);
1072 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
1073 spin_unlock(&gpu->event_spinlock);
1074
1075 etnaviv_gpu_hw_init(gpu);
1076
1077 mutex_unlock(&gpu->lock);
1078 pm_runtime_mark_last_busy(gpu->dev);
1079 pm_put:
1080 pm_runtime_put_autosuspend(gpu->dev);
1081 }
1082
1083 /* fence object management */
1084 struct etnaviv_fence {
1085 struct etnaviv_gpu *gpu;
1086 struct dma_fence base;
1087 };
1088
to_etnaviv_fence(struct dma_fence * fence)1089 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1090 {
1091 return container_of(fence, struct etnaviv_fence, base);
1092 }
1093
etnaviv_fence_get_driver_name(struct dma_fence * fence)1094 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1095 {
1096 return "etnaviv";
1097 }
1098
etnaviv_fence_get_timeline_name(struct dma_fence * fence)1099 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1100 {
1101 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1102
1103 return dev_name(f->gpu->dev);
1104 }
1105
etnaviv_fence_signaled(struct dma_fence * fence)1106 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1107 {
1108 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1109
1110 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1111 }
1112
etnaviv_fence_release(struct dma_fence * fence)1113 static void etnaviv_fence_release(struct dma_fence *fence)
1114 {
1115 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1116
1117 kfree_rcu(f, base.rcu);
1118 }
1119
1120 static const struct dma_fence_ops etnaviv_fence_ops = {
1121 .get_driver_name = etnaviv_fence_get_driver_name,
1122 .get_timeline_name = etnaviv_fence_get_timeline_name,
1123 .signaled = etnaviv_fence_signaled,
1124 .release = etnaviv_fence_release,
1125 };
1126
etnaviv_gpu_fence_alloc(struct etnaviv_gpu * gpu)1127 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1128 {
1129 struct etnaviv_fence *f;
1130
1131 /*
1132 * GPU lock must already be held, otherwise fence completion order might
1133 * not match the seqno order assigned here.
1134 */
1135 lockdep_assert_held(&gpu->lock);
1136
1137 f = kzalloc(sizeof(*f), GFP_KERNEL);
1138 if (!f)
1139 return NULL;
1140
1141 f->gpu = gpu;
1142
1143 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1144 gpu->fence_context, ++gpu->next_fence);
1145
1146 return &f->base;
1147 }
1148
1149 /* returns true if fence a comes after fence b */
fence_after(u32 a,u32 b)1150 static inline bool fence_after(u32 a, u32 b)
1151 {
1152 return (s32)(a - b) > 0;
1153 }
1154
1155 /*
1156 * event management:
1157 */
1158
event_alloc(struct etnaviv_gpu * gpu,unsigned nr_events,unsigned int * events)1159 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1160 unsigned int *events)
1161 {
1162 unsigned long timeout = msecs_to_jiffies(10 * 10000);
1163 unsigned i, acquired = 0;
1164
1165 for (i = 0; i < nr_events; i++) {
1166 unsigned long ret;
1167
1168 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1169
1170 if (!ret) {
1171 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1172 goto out;
1173 }
1174
1175 acquired++;
1176 timeout = ret;
1177 }
1178
1179 spin_lock(&gpu->event_spinlock);
1180
1181 for (i = 0; i < nr_events; i++) {
1182 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1183
1184 events[i] = event;
1185 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1186 set_bit(event, gpu->event_bitmap);
1187 }
1188
1189 spin_unlock(&gpu->event_spinlock);
1190
1191 return 0;
1192
1193 out:
1194 for (i = 0; i < acquired; i++)
1195 complete(&gpu->event_free);
1196
1197 return -EBUSY;
1198 }
1199
event_free(struct etnaviv_gpu * gpu,unsigned int event)1200 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1201 {
1202 if (!test_bit(event, gpu->event_bitmap)) {
1203 dev_warn(gpu->dev, "event %u is already marked as free",
1204 event);
1205 } else {
1206 clear_bit(event, gpu->event_bitmap);
1207 complete(&gpu->event_free);
1208 }
1209 }
1210
1211 /*
1212 * Cmdstream submission/retirement:
1213 */
etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu * gpu,u32 id,struct drm_etnaviv_timespec * timeout)1214 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1215 u32 id, struct drm_etnaviv_timespec *timeout)
1216 {
1217 struct dma_fence *fence;
1218 int ret;
1219
1220 /*
1221 * Look up the fence and take a reference. We might still find a fence
1222 * whose refcount has already dropped to zero. dma_fence_get_rcu
1223 * pretends we didn't find a fence in that case.
1224 */
1225 rcu_read_lock();
1226 fence = idr_find(&gpu->fence_idr, id);
1227 if (fence)
1228 fence = dma_fence_get_rcu(fence);
1229 rcu_read_unlock();
1230
1231 if (!fence)
1232 return 0;
1233
1234 if (!timeout) {
1235 /* No timeout was requested: just test for completion */
1236 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1237 } else {
1238 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1239
1240 ret = dma_fence_wait_timeout(fence, true, remaining);
1241 if (ret == 0)
1242 ret = -ETIMEDOUT;
1243 else if (ret != -ERESTARTSYS)
1244 ret = 0;
1245
1246 }
1247
1248 dma_fence_put(fence);
1249 return ret;
1250 }
1251
1252 /*
1253 * Wait for an object to become inactive. This, on it's own, is not race
1254 * free: the object is moved by the scheduler off the active list, and
1255 * then the iova is put. Moreover, the object could be re-submitted just
1256 * after we notice that it's become inactive.
1257 *
1258 * Although the retirement happens under the gpu lock, we don't want to hold
1259 * that lock in this function while waiting.
1260 */
etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu * gpu,struct etnaviv_gem_object * etnaviv_obj,struct drm_etnaviv_timespec * timeout)1261 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1262 struct etnaviv_gem_object *etnaviv_obj,
1263 struct drm_etnaviv_timespec *timeout)
1264 {
1265 unsigned long remaining;
1266 long ret;
1267
1268 if (!timeout)
1269 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1270
1271 remaining = etnaviv_timeout_to_jiffies(timeout);
1272
1273 ret = wait_event_interruptible_timeout(gpu->fence_event,
1274 !is_active(etnaviv_obj),
1275 remaining);
1276 if (ret > 0)
1277 return 0;
1278 else if (ret == -ERESTARTSYS)
1279 return -ERESTARTSYS;
1280 else
1281 return -ETIMEDOUT;
1282 }
1283
sync_point_perfmon_sample(struct etnaviv_gpu * gpu,struct etnaviv_event * event,unsigned int flags)1284 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1285 struct etnaviv_event *event, unsigned int flags)
1286 {
1287 const struct etnaviv_gem_submit *submit = event->submit;
1288 unsigned int i;
1289
1290 for (i = 0; i < submit->nr_pmrs; i++) {
1291 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1292
1293 if (pmr->flags == flags)
1294 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1295 }
1296 }
1297
sync_point_perfmon_sample_pre(struct etnaviv_gpu * gpu,struct etnaviv_event * event)1298 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1299 struct etnaviv_event *event)
1300 {
1301 u32 val;
1302
1303 /* disable clock gating */
1304 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1305 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1306 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1307
1308 /* enable debug register */
1309 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1310 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1311 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1312
1313 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1314 }
1315
sync_point_perfmon_sample_post(struct etnaviv_gpu * gpu,struct etnaviv_event * event)1316 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1317 struct etnaviv_event *event)
1318 {
1319 const struct etnaviv_gem_submit *submit = event->submit;
1320 unsigned int i;
1321 u32 val;
1322
1323 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1324
1325 for (i = 0; i < submit->nr_pmrs; i++) {
1326 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1327
1328 *pmr->bo_vma = pmr->sequence;
1329 }
1330
1331 /* disable debug register */
1332 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1333 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1334 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1335
1336 /* enable clock gating */
1337 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1338 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1339 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1340 }
1341
1342
1343 /* add bo's to gpu's ring, and kick gpu: */
etnaviv_gpu_submit(struct etnaviv_gem_submit * submit)1344 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1345 {
1346 struct etnaviv_gpu *gpu = submit->gpu;
1347 struct dma_fence *gpu_fence;
1348 unsigned int i, nr_events = 1, event[3];
1349 int ret;
1350
1351 if (!submit->runtime_resumed) {
1352 ret = pm_runtime_get_sync(gpu->dev);
1353 if (ret < 0) {
1354 pm_runtime_put_noidle(gpu->dev);
1355 return NULL;
1356 }
1357 submit->runtime_resumed = true;
1358 }
1359
1360 /*
1361 * if there are performance monitor requests we need to have
1362 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1363 * requests.
1364 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1365 * and update the sequence number for userspace.
1366 */
1367 if (submit->nr_pmrs)
1368 nr_events = 3;
1369
1370 ret = event_alloc(gpu, nr_events, event);
1371 if (ret) {
1372 DRM_ERROR("no free events\n");
1373 pm_runtime_put_noidle(gpu->dev);
1374 return NULL;
1375 }
1376
1377 mutex_lock(&gpu->lock);
1378
1379 gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1380 if (!gpu_fence) {
1381 for (i = 0; i < nr_events; i++)
1382 event_free(gpu, event[i]);
1383
1384 goto out_unlock;
1385 }
1386
1387 if (!gpu->fe_running)
1388 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1389
1390 if (submit->prev_mmu_context)
1391 etnaviv_iommu_context_put(submit->prev_mmu_context);
1392 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
1393
1394 if (submit->nr_pmrs) {
1395 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1396 kref_get(&submit->refcount);
1397 gpu->event[event[1]].submit = submit;
1398 etnaviv_sync_point_queue(gpu, event[1]);
1399 }
1400
1401 gpu->event[event[0]].fence = gpu_fence;
1402 submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1403 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1404 event[0], &submit->cmdbuf);
1405
1406 if (submit->nr_pmrs) {
1407 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1408 kref_get(&submit->refcount);
1409 gpu->event[event[2]].submit = submit;
1410 etnaviv_sync_point_queue(gpu, event[2]);
1411 }
1412
1413 out_unlock:
1414 mutex_unlock(&gpu->lock);
1415
1416 return gpu_fence;
1417 }
1418
sync_point_worker(struct work_struct * work)1419 static void sync_point_worker(struct work_struct *work)
1420 {
1421 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1422 sync_point_work);
1423 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1424 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1425
1426 event->sync_point(gpu, event);
1427 etnaviv_submit_put(event->submit);
1428 event_free(gpu, gpu->sync_point_event);
1429
1430 /* restart FE last to avoid GPU and IRQ racing against this worker */
1431 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1432 }
1433
dump_mmu_fault(struct etnaviv_gpu * gpu)1434 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1435 {
1436 u32 status_reg, status;
1437 int i;
1438
1439 if (gpu->sec_mode == ETNA_SEC_NONE)
1440 status_reg = VIVS_MMUv2_STATUS;
1441 else
1442 status_reg = VIVS_MMUv2_SEC_STATUS;
1443
1444 status = gpu_read(gpu, status_reg);
1445 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1446
1447 for (i = 0; i < 4; i++) {
1448 u32 address_reg;
1449
1450 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1451 continue;
1452
1453 if (gpu->sec_mode == ETNA_SEC_NONE)
1454 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1455 else
1456 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1457
1458 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1459 gpu_read(gpu, address_reg));
1460 }
1461 }
1462
irq_handler(int irq,void * data)1463 static irqreturn_t irq_handler(int irq, void *data)
1464 {
1465 struct etnaviv_gpu *gpu = data;
1466 irqreturn_t ret = IRQ_NONE;
1467
1468 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1469
1470 if (intr != 0) {
1471 int event;
1472
1473 pm_runtime_mark_last_busy(gpu->dev);
1474
1475 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1476
1477 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1478 dev_err(gpu->dev, "AXI bus error\n");
1479 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1480 }
1481
1482 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1483 dump_mmu_fault(gpu);
1484 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1485 }
1486
1487 while ((event = ffs(intr)) != 0) {
1488 struct dma_fence *fence;
1489
1490 event -= 1;
1491
1492 intr &= ~(1 << event);
1493
1494 dev_dbg(gpu->dev, "event %u\n", event);
1495
1496 if (gpu->event[event].sync_point) {
1497 gpu->sync_point_event = event;
1498 queue_work(gpu->wq, &gpu->sync_point_work);
1499 }
1500
1501 fence = gpu->event[event].fence;
1502 if (!fence)
1503 continue;
1504
1505 gpu->event[event].fence = NULL;
1506
1507 /*
1508 * Events can be processed out of order. Eg,
1509 * - allocate and queue event 0
1510 * - allocate event 1
1511 * - event 0 completes, we process it
1512 * - allocate and queue event 0
1513 * - event 1 and event 0 complete
1514 * we can end up processing event 0 first, then 1.
1515 */
1516 if (fence_after(fence->seqno, gpu->completed_fence))
1517 gpu->completed_fence = fence->seqno;
1518 dma_fence_signal(fence);
1519
1520 event_free(gpu, event);
1521 }
1522
1523 ret = IRQ_HANDLED;
1524 }
1525
1526 return ret;
1527 }
1528
etnaviv_gpu_clk_enable(struct etnaviv_gpu * gpu)1529 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1530 {
1531 int ret;
1532
1533 ret = clk_prepare_enable(gpu->clk_reg);
1534 if (ret)
1535 return ret;
1536
1537 ret = clk_prepare_enable(gpu->clk_bus);
1538 if (ret)
1539 goto disable_clk_reg;
1540
1541 ret = clk_prepare_enable(gpu->clk_core);
1542 if (ret)
1543 goto disable_clk_bus;
1544
1545 ret = clk_prepare_enable(gpu->clk_shader);
1546 if (ret)
1547 goto disable_clk_core;
1548
1549 return 0;
1550
1551 disable_clk_core:
1552 clk_disable_unprepare(gpu->clk_core);
1553 disable_clk_bus:
1554 clk_disable_unprepare(gpu->clk_bus);
1555 disable_clk_reg:
1556 clk_disable_unprepare(gpu->clk_reg);
1557
1558 return ret;
1559 }
1560
etnaviv_gpu_clk_disable(struct etnaviv_gpu * gpu)1561 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1562 {
1563 clk_disable_unprepare(gpu->clk_shader);
1564 clk_disable_unprepare(gpu->clk_core);
1565 clk_disable_unprepare(gpu->clk_bus);
1566 clk_disable_unprepare(gpu->clk_reg);
1567
1568 return 0;
1569 }
1570
etnaviv_gpu_wait_idle(struct etnaviv_gpu * gpu,unsigned int timeout_ms)1571 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1572 {
1573 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1574
1575 do {
1576 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1577
1578 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1579 return 0;
1580
1581 if (time_is_before_jiffies(timeout)) {
1582 dev_warn(gpu->dev,
1583 "timed out waiting for idle: idle=0x%x\n",
1584 idle);
1585 return -ETIMEDOUT;
1586 }
1587
1588 udelay(5);
1589 } while (1);
1590 }
1591
etnaviv_gpu_hw_suspend(struct etnaviv_gpu * gpu)1592 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1593 {
1594 if (gpu->initialized && gpu->fe_running) {
1595 /* Replace the last WAIT with END */
1596 mutex_lock(&gpu->lock);
1597 etnaviv_buffer_end(gpu);
1598 mutex_unlock(&gpu->lock);
1599
1600 /*
1601 * We know that only the FE is busy here, this should
1602 * happen quickly (as the WAIT is only 200 cycles). If
1603 * we fail, just warn and continue.
1604 */
1605 etnaviv_gpu_wait_idle(gpu, 100);
1606
1607 gpu->fe_running = false;
1608 }
1609
1610 gpu->exec_state = -1;
1611
1612 return etnaviv_gpu_clk_disable(gpu);
1613 }
1614
1615 #ifdef CONFIG_PM
etnaviv_gpu_hw_resume(struct etnaviv_gpu * gpu)1616 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1617 {
1618 int ret;
1619
1620 ret = mutex_lock_killable(&gpu->lock);
1621 if (ret)
1622 return ret;
1623
1624 etnaviv_gpu_update_clock(gpu);
1625 etnaviv_gpu_hw_init(gpu);
1626
1627 mutex_unlock(&gpu->lock);
1628
1629 return 0;
1630 }
1631 #endif
1632
1633 static int
etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device * cdev,unsigned long * state)1634 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1635 unsigned long *state)
1636 {
1637 *state = 6;
1638
1639 return 0;
1640 }
1641
1642 static int
etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device * cdev,unsigned long * state)1643 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1644 unsigned long *state)
1645 {
1646 struct etnaviv_gpu *gpu = cdev->devdata;
1647
1648 *state = gpu->freq_scale;
1649
1650 return 0;
1651 }
1652
1653 static int
etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device * cdev,unsigned long state)1654 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1655 unsigned long state)
1656 {
1657 struct etnaviv_gpu *gpu = cdev->devdata;
1658
1659 mutex_lock(&gpu->lock);
1660 gpu->freq_scale = state;
1661 if (!pm_runtime_suspended(gpu->dev))
1662 etnaviv_gpu_update_clock(gpu);
1663 mutex_unlock(&gpu->lock);
1664
1665 return 0;
1666 }
1667
1668 static const struct thermal_cooling_device_ops cooling_ops = {
1669 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1670 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1671 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1672 };
1673
etnaviv_gpu_bind(struct device * dev,struct device * master,void * data)1674 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1675 void *data)
1676 {
1677 struct drm_device *drm = data;
1678 struct etnaviv_drm_private *priv = drm->dev_private;
1679 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1680 int ret;
1681
1682 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1683 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1684 (char *)dev_name(dev), gpu, &cooling_ops);
1685 if (IS_ERR(gpu->cooling))
1686 return PTR_ERR(gpu->cooling);
1687 }
1688
1689 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1690 if (!gpu->wq) {
1691 ret = -ENOMEM;
1692 goto out_thermal;
1693 }
1694
1695 ret = etnaviv_sched_init(gpu);
1696 if (ret)
1697 goto out_workqueue;
1698
1699 #ifdef CONFIG_PM
1700 ret = pm_runtime_get_sync(gpu->dev);
1701 #else
1702 ret = etnaviv_gpu_clk_enable(gpu);
1703 #endif
1704 if (ret < 0)
1705 goto out_sched;
1706
1707
1708 gpu->drm = drm;
1709 gpu->fence_context = dma_fence_context_alloc(1);
1710 idr_init(&gpu->fence_idr);
1711 spin_lock_init(&gpu->fence_spinlock);
1712
1713 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1714 init_waitqueue_head(&gpu->fence_event);
1715
1716 priv->gpu[priv->num_gpus++] = gpu;
1717
1718 pm_runtime_mark_last_busy(gpu->dev);
1719 pm_runtime_put_autosuspend(gpu->dev);
1720
1721 return 0;
1722
1723 out_sched:
1724 etnaviv_sched_fini(gpu);
1725
1726 out_workqueue:
1727 destroy_workqueue(gpu->wq);
1728
1729 out_thermal:
1730 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1731 thermal_cooling_device_unregister(gpu->cooling);
1732
1733 return ret;
1734 }
1735
etnaviv_gpu_unbind(struct device * dev,struct device * master,void * data)1736 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1737 void *data)
1738 {
1739 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1740
1741 DBG("%s", dev_name(gpu->dev));
1742
1743 destroy_workqueue(gpu->wq);
1744
1745 etnaviv_sched_fini(gpu);
1746
1747 #ifdef CONFIG_PM
1748 pm_runtime_get_sync(gpu->dev);
1749 pm_runtime_put_sync_suspend(gpu->dev);
1750 #else
1751 etnaviv_gpu_hw_suspend(gpu);
1752 #endif
1753
1754 if (gpu->mmu_context)
1755 etnaviv_iommu_context_put(gpu->mmu_context);
1756
1757 if (gpu->initialized) {
1758 etnaviv_cmdbuf_free(&gpu->buffer);
1759 etnaviv_iommu_global_fini(gpu);
1760 gpu->initialized = false;
1761 }
1762
1763 gpu->drm = NULL;
1764 idr_destroy(&gpu->fence_idr);
1765
1766 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1767 thermal_cooling_device_unregister(gpu->cooling);
1768 gpu->cooling = NULL;
1769 }
1770
1771 static const struct component_ops gpu_ops = {
1772 .bind = etnaviv_gpu_bind,
1773 .unbind = etnaviv_gpu_unbind,
1774 };
1775
1776 static const struct of_device_id etnaviv_gpu_match[] = {
1777 {
1778 .compatible = "vivante,gc"
1779 },
1780 { /* sentinel */ }
1781 };
1782 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1783
etnaviv_gpu_platform_probe(struct platform_device * pdev)1784 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1785 {
1786 struct device *dev = &pdev->dev;
1787 struct etnaviv_gpu *gpu;
1788 int err;
1789
1790 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1791 if (!gpu)
1792 return -ENOMEM;
1793
1794 gpu->dev = &pdev->dev;
1795 mutex_init(&gpu->lock);
1796 mutex_init(&gpu->fence_lock);
1797
1798 /* Map registers: */
1799 gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1800 if (IS_ERR(gpu->mmio))
1801 return PTR_ERR(gpu->mmio);
1802
1803 /* Get Interrupt: */
1804 gpu->irq = platform_get_irq(pdev, 0);
1805 if (gpu->irq < 0)
1806 return gpu->irq;
1807
1808 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1809 dev_name(gpu->dev), gpu);
1810 if (err) {
1811 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1812 return err;
1813 }
1814
1815 /* Get Clocks: */
1816 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1817 DBG("clk_reg: %p", gpu->clk_reg);
1818 if (IS_ERR(gpu->clk_reg))
1819 return PTR_ERR(gpu->clk_reg);
1820
1821 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1822 DBG("clk_bus: %p", gpu->clk_bus);
1823 if (IS_ERR(gpu->clk_bus))
1824 return PTR_ERR(gpu->clk_bus);
1825
1826 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1827 DBG("clk_core: %p", gpu->clk_core);
1828 if (IS_ERR(gpu->clk_core))
1829 return PTR_ERR(gpu->clk_core);
1830 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1831
1832 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1833 DBG("clk_shader: %p", gpu->clk_shader);
1834 if (IS_ERR(gpu->clk_shader))
1835 return PTR_ERR(gpu->clk_shader);
1836 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1837
1838 /* TODO: figure out max mapped size */
1839 dev_set_drvdata(dev, gpu);
1840
1841 /*
1842 * We treat the device as initially suspended. The runtime PM
1843 * autosuspend delay is rather arbitary: no measurements have
1844 * yet been performed to determine an appropriate value.
1845 */
1846 pm_runtime_use_autosuspend(gpu->dev);
1847 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1848 pm_runtime_enable(gpu->dev);
1849
1850 err = component_add(&pdev->dev, &gpu_ops);
1851 if (err < 0) {
1852 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1853 return err;
1854 }
1855
1856 return 0;
1857 }
1858
etnaviv_gpu_platform_remove(struct platform_device * pdev)1859 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1860 {
1861 component_del(&pdev->dev, &gpu_ops);
1862 pm_runtime_disable(&pdev->dev);
1863 return 0;
1864 }
1865
1866 #ifdef CONFIG_PM
etnaviv_gpu_rpm_suspend(struct device * dev)1867 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1868 {
1869 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1870 u32 idle, mask;
1871
1872 /* If there are any jobs in the HW queue, we're not idle */
1873 if (atomic_read(&gpu->sched.hw_rq_count))
1874 return -EBUSY;
1875
1876 /* Check whether the hardware (except FE and MC) is idle */
1877 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1878 VIVS_HI_IDLE_STATE_MC);
1879 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1880 if (idle != mask) {
1881 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1882 idle);
1883 return -EBUSY;
1884 }
1885
1886 return etnaviv_gpu_hw_suspend(gpu);
1887 }
1888
etnaviv_gpu_rpm_resume(struct device * dev)1889 static int etnaviv_gpu_rpm_resume(struct device *dev)
1890 {
1891 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1892 int ret;
1893
1894 ret = etnaviv_gpu_clk_enable(gpu);
1895 if (ret)
1896 return ret;
1897
1898 /* Re-initialise the basic hardware state */
1899 if (gpu->drm && gpu->initialized) {
1900 ret = etnaviv_gpu_hw_resume(gpu);
1901 if (ret) {
1902 etnaviv_gpu_clk_disable(gpu);
1903 return ret;
1904 }
1905 }
1906
1907 return 0;
1908 }
1909 #endif
1910
1911 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1912 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1913 NULL)
1914 };
1915
1916 struct platform_driver etnaviv_gpu_driver = {
1917 .driver = {
1918 .name = "etnaviv-gpu",
1919 .owner = THIS_MODULE,
1920 .pm = &etnaviv_gpu_pm_ops,
1921 .of_match_table = etnaviv_gpu_match,
1922 },
1923 .probe = etnaviv_gpu_platform_probe,
1924 .remove = etnaviv_gpu_platform_remove,
1925 .id_table = gpu_ids,
1926 };
1927