1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "nbio_v4_3.h"
26
27 #include "nbio/nbio_4_3_0_offset.h"
28 #include "nbio/nbio_4_3_0_sh_mask.h"
29 #include <uapi/linux/kfd_ioctl.h>
30
nbio_v4_3_remap_hdp_registers(struct amdgpu_device * adev)31 static void nbio_v4_3_remap_hdp_registers(struct amdgpu_device *adev)
32 {
33 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
34 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
37 }
38
nbio_v4_3_get_rev_id(struct amdgpu_device * adev)39 static u32 nbio_v4_3_get_rev_id(struct amdgpu_device *adev)
40 {
41 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
42
43 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
44 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
45
46 return tmp;
47 }
48
nbio_v4_3_mc_access_enable(struct amdgpu_device * adev,bool enable)49 static void nbio_v4_3_mc_access_enable(struct amdgpu_device *adev, bool enable)
50 {
51 if (enable)
52 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
53 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
54 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
55 else
56 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
57 }
58
nbio_v4_3_get_memsize(struct amdgpu_device * adev)59 static u32 nbio_v4_3_get_memsize(struct amdgpu_device *adev)
60 {
61 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
62 }
63
nbio_v4_3_sdma_doorbell_range(struct amdgpu_device * adev,int instance,bool use_doorbell,int doorbell_index,int doorbell_size)64 static void nbio_v4_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
65 bool use_doorbell, int doorbell_index,
66 int doorbell_size)
67 {
68 if (instance == 0) {
69 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL);
70
71 if (use_doorbell) {
72 doorbell_range = REG_SET_FIELD(doorbell_range,
73 S2A_DOORBELL_ENTRY_2_CTRL,
74 S2A_DOORBELL_PORT2_ENABLE,
75 0x1);
76 doorbell_range = REG_SET_FIELD(doorbell_range,
77 S2A_DOORBELL_ENTRY_2_CTRL,
78 S2A_DOORBELL_PORT2_AWID,
79 0xe);
80 doorbell_range = REG_SET_FIELD(doorbell_range,
81 S2A_DOORBELL_ENTRY_2_CTRL,
82 S2A_DOORBELL_PORT2_RANGE_OFFSET,
83 doorbell_index);
84 doorbell_range = REG_SET_FIELD(doorbell_range,
85 S2A_DOORBELL_ENTRY_2_CTRL,
86 S2A_DOORBELL_PORT2_RANGE_SIZE,
87 doorbell_size);
88 doorbell_range = REG_SET_FIELD(doorbell_range,
89 S2A_DOORBELL_ENTRY_2_CTRL,
90 S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
91 0x3);
92 } else
93 doorbell_range = REG_SET_FIELD(doorbell_range,
94 S2A_DOORBELL_ENTRY_2_CTRL,
95 S2A_DOORBELL_PORT2_RANGE_SIZE,
96 0);
97
98 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL, doorbell_range);
99 }
100 }
101
nbio_v4_3_vcn_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index,int instance)102 static void nbio_v4_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
103 int doorbell_index, int instance)
104 {
105 u32 doorbell_range;
106
107 if (instance)
108 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL);
109 else
110 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL);
111
112 if (use_doorbell) {
113 doorbell_range = REG_SET_FIELD(doorbell_range,
114 S2A_DOORBELL_ENTRY_4_CTRL,
115 S2A_DOORBELL_PORT4_ENABLE,
116 0x1);
117 doorbell_range = REG_SET_FIELD(doorbell_range,
118 S2A_DOORBELL_ENTRY_4_CTRL,
119 S2A_DOORBELL_PORT4_AWID,
120 instance ? 0x7 : 0x4);
121 doorbell_range = REG_SET_FIELD(doorbell_range,
122 S2A_DOORBELL_ENTRY_4_CTRL,
123 S2A_DOORBELL_PORT4_RANGE_OFFSET,
124 doorbell_index);
125 doorbell_range = REG_SET_FIELD(doorbell_range,
126 S2A_DOORBELL_ENTRY_4_CTRL,
127 S2A_DOORBELL_PORT4_RANGE_SIZE,
128 8);
129 doorbell_range = REG_SET_FIELD(doorbell_range,
130 S2A_DOORBELL_ENTRY_4_CTRL,
131 S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE,
132 instance ? 0x7 : 0x4);
133 } else
134 doorbell_range = REG_SET_FIELD(doorbell_range,
135 S2A_DOORBELL_ENTRY_4_CTRL,
136 S2A_DOORBELL_PORT4_RANGE_SIZE,
137 0);
138
139 if (instance)
140 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
141 else
142 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
143 }
144
nbio_v4_3_gc_doorbell_init(struct amdgpu_device * adev)145 static void nbio_v4_3_gc_doorbell_init(struct amdgpu_device *adev)
146 {
147 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
148 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
149 }
150
nbio_v4_3_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)151 static void nbio_v4_3_enable_doorbell_aperture(struct amdgpu_device *adev,
152 bool enable)
153 {
154 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
155 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
156 }
157
nbio_v4_3_enable_doorbell_selfring_aperture(struct amdgpu_device * adev,bool enable)158 static void nbio_v4_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
159 bool enable)
160 {
161 u32 tmp = 0;
162
163 if (enable) {
164 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
165 DOORBELL_SELFRING_GPA_APER_EN, 1) |
166 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
167 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
168 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
169 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
170
171 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
172 lower_32_bits(adev->doorbell.base));
173 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
174 upper_32_bits(adev->doorbell.base));
175 }
176
177 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
178 tmp);
179 }
180
nbio_v4_3_ih_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index)181 static void nbio_v4_3_ih_doorbell_range(struct amdgpu_device *adev,
182 bool use_doorbell, int doorbell_index)
183 {
184 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL);
185
186 if (use_doorbell) {
187 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
188 S2A_DOORBELL_ENTRY_1_CTRL,
189 S2A_DOORBELL_PORT1_ENABLE,
190 0x1);
191 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
192 S2A_DOORBELL_ENTRY_1_CTRL,
193 S2A_DOORBELL_PORT1_AWID,
194 0x0);
195 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
196 S2A_DOORBELL_ENTRY_1_CTRL,
197 S2A_DOORBELL_PORT1_RANGE_OFFSET,
198 doorbell_index);
199 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
200 S2A_DOORBELL_ENTRY_1_CTRL,
201 S2A_DOORBELL_PORT1_RANGE_SIZE,
202 2);
203 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
204 S2A_DOORBELL_ENTRY_1_CTRL,
205 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
206 0x0);
207 } else
208 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
209 S2A_DOORBELL_ENTRY_1_CTRL,
210 S2A_DOORBELL_PORT1_RANGE_SIZE,
211 0);
212
213 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range);
214 }
215
nbio_v4_3_ih_control(struct amdgpu_device * adev)216 static void nbio_v4_3_ih_control(struct amdgpu_device *adev)
217 {
218 u32 interrupt_cntl;
219
220 /* setup interrupt control */
221 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
222
223 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
224 /*
225 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
226 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
227 */
228 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
229 IH_DUMMY_RD_OVERRIDE, 0);
230
231 /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
232 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
233 IH_REQ_NONSNOOP_EN, 0);
234
235 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
236 }
237
nbio_v4_3_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)238 static void nbio_v4_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
239 bool enable)
240 {
241 uint32_t def, data;
242
243 if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
244 return;
245
246 def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL);
247 if (enable) {
248 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
249 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
250 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
251 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
252 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
253 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
254 } else {
255 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
256 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
257 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
258 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
259 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
260 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
261 }
262
263 if (def != data)
264 WREG32_SOC15(NBIO, 0, regCPM_CONTROL, data);
265 }
266
nbio_v4_3_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)267 static void nbio_v4_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
268 bool enable)
269 {
270 uint32_t def, data;
271
272 if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
273 return;
274
275 /* TODO: need update in future */
276 def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2);
277 if (enable) {
278 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
279 } else {
280 data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
281 }
282
283 if (def != data)
284 WREG32_SOC15(NBIO, 0, regPCIE_CNTL2, data);
285 }
286
nbio_v4_3_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)287 static void nbio_v4_3_get_clockgating_state(struct amdgpu_device *adev,
288 u64 *flags)
289 {
290 int data;
291
292 /* AMD_CG_SUPPORT_BIF_MGCG */
293 data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL);
294 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
295 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
296
297 /* AMD_CG_SUPPORT_BIF_LS */
298 data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2);
299 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
300 *flags |= AMD_CG_SUPPORT_BIF_LS;
301 }
302
nbio_v4_3_get_hdp_flush_req_offset(struct amdgpu_device * adev)303 static u32 nbio_v4_3_get_hdp_flush_req_offset(struct amdgpu_device *adev)
304 {
305 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
306 }
307
nbio_v4_3_get_hdp_flush_done_offset(struct amdgpu_device * adev)308 static u32 nbio_v4_3_get_hdp_flush_done_offset(struct amdgpu_device *adev)
309 {
310 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
311 }
312
nbio_v4_3_get_pcie_index_offset(struct amdgpu_device * adev)313 static u32 nbio_v4_3_get_pcie_index_offset(struct amdgpu_device *adev)
314 {
315 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
316 }
317
nbio_v4_3_get_pcie_data_offset(struct amdgpu_device * adev)318 static u32 nbio_v4_3_get_pcie_data_offset(struct amdgpu_device *adev)
319 {
320 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
321 }
322
323 const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg = {
324 .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
325 .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,
326 .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,
327 .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK,
328 .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK,
329 .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK,
330 .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK,
331 .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK,
332 .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK,
333 .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK,
334 .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
335 .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
336 };
337
nbio_v4_3_init_registers(struct amdgpu_device * adev)338 static void nbio_v4_3_init_registers(struct amdgpu_device *adev)
339 {
340 return;
341 }
342
nbio_v4_3_get_rom_offset(struct amdgpu_device * adev)343 static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)
344 {
345 u32 data, rom_offset;
346
347 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL);
348 rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET);
349
350 return rom_offset;
351 }
352
353 #ifdef CONFIG_PCIEASPM
nbio_v4_3_program_ltr(struct amdgpu_device * adev)354 static void nbio_v4_3_program_ltr(struct amdgpu_device *adev)
355 {
356 uint32_t def, data;
357
358 def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
359 data = 0x35EB;
360 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
361 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK;
362 if (def != data)
363 WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
364
365 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2);
366 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
367 if (def != data)
368 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data);
369
370 def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
371 if (adev->pdev->ltr_path)
372 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
373 else
374 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
375 if (def != data)
376 WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
377 }
378 #endif
379
nbio_v4_3_program_aspm(struct amdgpu_device * adev)380 static void nbio_v4_3_program_aspm(struct amdgpu_device *adev)
381 {
382 #ifdef CONFIG_PCIEASPM
383 uint32_t def, data;
384
385 if (!(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 4, 0)) &&
386 !(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 6, 0)))
387 return;
388
389 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);
390 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
391 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
392 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
393 if (def != data)
394 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data);
395
396 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7);
397 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
398 if (def != data)
399 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7, data);
400
401 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);
402 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
403 if (def != data)
404 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data);
405
406 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);
407 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
408 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
409 if (def != data)
410 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data);
411
412 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);
413 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
414 if (def != data)
415 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
416
417 def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
418 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
419 if (def != data)
420 WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
421
422 WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
423
424 def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2);
425 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
426 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
427 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
428 if (def != data)
429 WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data);
430
431 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4);
432 data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK;
433 if (def != data)
434 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4, data);
435
436 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL);
437 data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK;
438 if (def != data)
439 WREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data);
440
441 nbio_v4_3_program_ltr(adev);
442
443 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);
444 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
445 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
446 if (def != data)
447 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data);
448
449 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);
450 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
451 if (def != data)
452 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
453
454 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);
455 data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
456 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
457 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
458 if (def != data)
459 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data);
460
461 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);
462 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
463 if (def != data)
464 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data);
465 #endif
466 }
467
468 const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
469 .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
470 .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
471 .get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset,
472 .get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset,
473 .get_rev_id = nbio_v4_3_get_rev_id,
474 .mc_access_enable = nbio_v4_3_mc_access_enable,
475 .get_memsize = nbio_v4_3_get_memsize,
476 .sdma_doorbell_range = nbio_v4_3_sdma_doorbell_range,
477 .vcn_doorbell_range = nbio_v4_3_vcn_doorbell_range,
478 .gc_doorbell_init = nbio_v4_3_gc_doorbell_init,
479 .enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture,
480 .enable_doorbell_selfring_aperture = nbio_v4_3_enable_doorbell_selfring_aperture,
481 .ih_doorbell_range = nbio_v4_3_ih_doorbell_range,
482 .update_medium_grain_clock_gating = nbio_v4_3_update_medium_grain_clock_gating,
483 .update_medium_grain_light_sleep = nbio_v4_3_update_medium_grain_light_sleep,
484 .get_clockgating_state = nbio_v4_3_get_clockgating_state,
485 .ih_control = nbio_v4_3_ih_control,
486 .init_registers = nbio_v4_3_init_registers,
487 .remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
488 .get_rom_offset = nbio_v4_3_get_rom_offset,
489 .program_aspm = nbio_v4_3_program_aspm,
490 };
491
492
nbio_v4_3_sriov_ih_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index)493 static void nbio_v4_3_sriov_ih_doorbell_range(struct amdgpu_device *adev,
494 bool use_doorbell, int doorbell_index)
495 {
496 }
497
nbio_v4_3_sriov_sdma_doorbell_range(struct amdgpu_device * adev,int instance,bool use_doorbell,int doorbell_index,int doorbell_size)498 static void nbio_v4_3_sriov_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
499 bool use_doorbell, int doorbell_index,
500 int doorbell_size)
501 {
502 }
503
nbio_v4_3_sriov_vcn_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index,int instance)504 static void nbio_v4_3_sriov_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
505 int doorbell_index, int instance)
506 {
507 }
508
nbio_v4_3_sriov_gc_doorbell_init(struct amdgpu_device * adev)509 static void nbio_v4_3_sriov_gc_doorbell_init(struct amdgpu_device *adev)
510 {
511 }
512
513 const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs = {
514 .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
515 .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
516 .get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset,
517 .get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset,
518 .get_rev_id = nbio_v4_3_get_rev_id,
519 .mc_access_enable = nbio_v4_3_mc_access_enable,
520 .get_memsize = nbio_v4_3_get_memsize,
521 .sdma_doorbell_range = nbio_v4_3_sriov_sdma_doorbell_range,
522 .vcn_doorbell_range = nbio_v4_3_sriov_vcn_doorbell_range,
523 .gc_doorbell_init = nbio_v4_3_sriov_gc_doorbell_init,
524 .enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture,
525 .enable_doorbell_selfring_aperture = nbio_v4_3_enable_doorbell_selfring_aperture,
526 .ih_doorbell_range = nbio_v4_3_sriov_ih_doorbell_range,
527 .update_medium_grain_clock_gating = nbio_v4_3_update_medium_grain_clock_gating,
528 .update_medium_grain_light_sleep = nbio_v4_3_update_medium_grain_light_sleep,
529 .get_clockgating_state = nbio_v4_3_get_clockgating_state,
530 .ih_control = nbio_v4_3_ih_control,
531 .init_registers = nbio_v4_3_init_registers,
532 .remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
533 .get_rom_offset = nbio_v4_3_get_rom_offset,
534 };
535