1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 //
6 // Based on code from Freescale Semiconductor,
7 // Authors: Daniel Mack, Juergen Beisert.
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9 
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/syscore_ops.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/bug.h>
27 
28 /* device type dependent stuff */
29 struct mxc_gpio_hwdata {
30 	unsigned dr_reg;
31 	unsigned gdir_reg;
32 	unsigned psr_reg;
33 	unsigned icr1_reg;
34 	unsigned icr2_reg;
35 	unsigned imr_reg;
36 	unsigned isr_reg;
37 	int edge_sel_reg;
38 	unsigned low_level;
39 	unsigned high_level;
40 	unsigned rise_edge;
41 	unsigned fall_edge;
42 };
43 
44 struct mxc_gpio_reg_saved {
45 	u32 icr1;
46 	u32 icr2;
47 	u32 imr;
48 	u32 gdir;
49 	u32 edge_sel;
50 	u32 dr;
51 };
52 
53 struct mxc_gpio_port {
54 	struct list_head node;
55 	void __iomem *base;
56 	struct clk *clk;
57 	int irq;
58 	int irq_high;
59 	struct irq_domain *domain;
60 	struct gpio_chip gc;
61 	struct device *dev;
62 	u32 both_edges;
63 	struct mxc_gpio_reg_saved gpio_saved_reg;
64 	bool power_off;
65 	const struct mxc_gpio_hwdata *hwdata;
66 };
67 
68 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
69 	.dr_reg		= 0x1c,
70 	.gdir_reg	= 0x00,
71 	.psr_reg	= 0x24,
72 	.icr1_reg	= 0x28,
73 	.icr2_reg	= 0x2c,
74 	.imr_reg	= 0x30,
75 	.isr_reg	= 0x34,
76 	.edge_sel_reg	= -EINVAL,
77 	.low_level	= 0x03,
78 	.high_level	= 0x02,
79 	.rise_edge	= 0x00,
80 	.fall_edge	= 0x01,
81 };
82 
83 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
84 	.dr_reg		= 0x00,
85 	.gdir_reg	= 0x04,
86 	.psr_reg	= 0x08,
87 	.icr1_reg	= 0x0c,
88 	.icr2_reg	= 0x10,
89 	.imr_reg	= 0x14,
90 	.isr_reg	= 0x18,
91 	.edge_sel_reg	= -EINVAL,
92 	.low_level	= 0x00,
93 	.high_level	= 0x01,
94 	.rise_edge	= 0x02,
95 	.fall_edge	= 0x03,
96 };
97 
98 static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
99 	.dr_reg		= 0x00,
100 	.gdir_reg	= 0x04,
101 	.psr_reg	= 0x08,
102 	.icr1_reg	= 0x0c,
103 	.icr2_reg	= 0x10,
104 	.imr_reg	= 0x14,
105 	.isr_reg	= 0x18,
106 	.edge_sel_reg	= 0x1c,
107 	.low_level	= 0x00,
108 	.high_level	= 0x01,
109 	.rise_edge	= 0x02,
110 	.fall_edge	= 0x03,
111 };
112 
113 #define GPIO_DR			(port->hwdata->dr_reg)
114 #define GPIO_GDIR		(port->hwdata->gdir_reg)
115 #define GPIO_PSR		(port->hwdata->psr_reg)
116 #define GPIO_ICR1		(port->hwdata->icr1_reg)
117 #define GPIO_ICR2		(port->hwdata->icr2_reg)
118 #define GPIO_IMR		(port->hwdata->imr_reg)
119 #define GPIO_ISR		(port->hwdata->isr_reg)
120 #define GPIO_EDGE_SEL		(port->hwdata->edge_sel_reg)
121 
122 #define GPIO_INT_LOW_LEV	(port->hwdata->low_level)
123 #define GPIO_INT_HIGH_LEV	(port->hwdata->high_level)
124 #define GPIO_INT_RISE_EDGE	(port->hwdata->rise_edge)
125 #define GPIO_INT_FALL_EDGE	(port->hwdata->fall_edge)
126 #define GPIO_INT_BOTH_EDGES	0x4
127 
128 static const struct of_device_id mxc_gpio_dt_ids[] = {
129 	{ .compatible = "fsl,imx1-gpio", .data =  &imx1_imx21_gpio_hwdata },
130 	{ .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
131 	{ .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
132 	{ .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
133 	{ .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
134 	{ /* sentinel */ }
135 };
136 MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
137 
138 /*
139  * MX2 has one interrupt *for all* gpio ports. The list is used
140  * to save the references to all ports, so that mx2_gpio_irq_handler
141  * can walk through all interrupt status registers.
142  */
143 static LIST_HEAD(mxc_gpio_ports);
144 
145 /* Note: This driver assumes 32 GPIOs are handled in one register */
146 
gpio_set_irq_type(struct irq_data * d,u32 type)147 static int gpio_set_irq_type(struct irq_data *d, u32 type)
148 {
149 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
150 	struct mxc_gpio_port *port = gc->private;
151 	unsigned long flags;
152 	u32 bit, val;
153 	u32 gpio_idx = d->hwirq;
154 	int edge;
155 	void __iomem *reg = port->base;
156 
157 	port->both_edges &= ~(1 << gpio_idx);
158 	switch (type) {
159 	case IRQ_TYPE_EDGE_RISING:
160 		edge = GPIO_INT_RISE_EDGE;
161 		break;
162 	case IRQ_TYPE_EDGE_FALLING:
163 		edge = GPIO_INT_FALL_EDGE;
164 		break;
165 	case IRQ_TYPE_EDGE_BOTH:
166 		if (GPIO_EDGE_SEL >= 0) {
167 			edge = GPIO_INT_BOTH_EDGES;
168 		} else {
169 			val = port->gc.get(&port->gc, gpio_idx);
170 			if (val) {
171 				edge = GPIO_INT_LOW_LEV;
172 				pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
173 			} else {
174 				edge = GPIO_INT_HIGH_LEV;
175 				pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
176 			}
177 			port->both_edges |= 1 << gpio_idx;
178 		}
179 		break;
180 	case IRQ_TYPE_LEVEL_LOW:
181 		edge = GPIO_INT_LOW_LEV;
182 		break;
183 	case IRQ_TYPE_LEVEL_HIGH:
184 		edge = GPIO_INT_HIGH_LEV;
185 		break;
186 	default:
187 		return -EINVAL;
188 	}
189 
190 	raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
191 
192 	if (GPIO_EDGE_SEL >= 0) {
193 		val = readl(port->base + GPIO_EDGE_SEL);
194 		if (edge == GPIO_INT_BOTH_EDGES)
195 			writel(val | (1 << gpio_idx),
196 				port->base + GPIO_EDGE_SEL);
197 		else
198 			writel(val & ~(1 << gpio_idx),
199 				port->base + GPIO_EDGE_SEL);
200 	}
201 
202 	if (edge != GPIO_INT_BOTH_EDGES) {
203 		reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
204 		bit = gpio_idx & 0xf;
205 		val = readl(reg) & ~(0x3 << (bit << 1));
206 		writel(val | (edge << (bit << 1)), reg);
207 	}
208 
209 	writel(1 << gpio_idx, port->base + GPIO_ISR);
210 
211 	raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
212 
213 	return port->gc.direction_input(&port->gc, gpio_idx);
214 }
215 
mxc_flip_edge(struct mxc_gpio_port * port,u32 gpio)216 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
217 {
218 	void __iomem *reg = port->base;
219 	unsigned long flags;
220 	u32 bit, val;
221 	int edge;
222 
223 	raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
224 
225 	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
226 	bit = gpio & 0xf;
227 	val = readl(reg);
228 	edge = (val >> (bit << 1)) & 3;
229 	val &= ~(0x3 << (bit << 1));
230 	if (edge == GPIO_INT_HIGH_LEV) {
231 		edge = GPIO_INT_LOW_LEV;
232 		pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
233 	} else if (edge == GPIO_INT_LOW_LEV) {
234 		edge = GPIO_INT_HIGH_LEV;
235 		pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
236 	} else {
237 		pr_err("mxc: invalid configuration for GPIO %d: %x\n",
238 		       gpio, edge);
239 		goto unlock;
240 	}
241 	writel(val | (edge << (bit << 1)), reg);
242 
243 unlock:
244 	raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
245 }
246 
247 /* handle 32 interrupts in one status register */
mxc_gpio_irq_handler(struct mxc_gpio_port * port,u32 irq_stat)248 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
249 {
250 	while (irq_stat != 0) {
251 		int irqoffset = fls(irq_stat) - 1;
252 
253 		if (port->both_edges & (1 << irqoffset))
254 			mxc_flip_edge(port, irqoffset);
255 
256 		generic_handle_domain_irq(port->domain, irqoffset);
257 
258 		irq_stat &= ~(1 << irqoffset);
259 	}
260 }
261 
262 /* MX1 and MX3 has one interrupt *per* gpio port */
mx3_gpio_irq_handler(struct irq_desc * desc)263 static void mx3_gpio_irq_handler(struct irq_desc *desc)
264 {
265 	u32 irq_stat;
266 	struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
267 	struct irq_chip *chip = irq_desc_get_chip(desc);
268 
269 	chained_irq_enter(chip, desc);
270 
271 	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
272 
273 	mxc_gpio_irq_handler(port, irq_stat);
274 
275 	chained_irq_exit(chip, desc);
276 }
277 
278 /* MX2 has one interrupt *for all* gpio ports */
mx2_gpio_irq_handler(struct irq_desc * desc)279 static void mx2_gpio_irq_handler(struct irq_desc *desc)
280 {
281 	u32 irq_msk, irq_stat;
282 	struct mxc_gpio_port *port;
283 	struct irq_chip *chip = irq_desc_get_chip(desc);
284 
285 	chained_irq_enter(chip, desc);
286 
287 	/* walk through all interrupt status registers */
288 	list_for_each_entry(port, &mxc_gpio_ports, node) {
289 		irq_msk = readl(port->base + GPIO_IMR);
290 		if (!irq_msk)
291 			continue;
292 
293 		irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
294 		if (irq_stat)
295 			mxc_gpio_irq_handler(port, irq_stat);
296 	}
297 	chained_irq_exit(chip, desc);
298 }
299 
300 /*
301  * Set interrupt number "irq" in the GPIO as a wake-up source.
302  * While system is running, all registered GPIO interrupts need to have
303  * wake-up enabled. When system is suspended, only selected GPIO interrupts
304  * need to have wake-up enabled.
305  * @param  irq          interrupt source number
306  * @param  enable       enable as wake-up if equal to non-zero
307  * @return       This function returns 0 on success.
308  */
gpio_set_wake_irq(struct irq_data * d,u32 enable)309 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
310 {
311 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
312 	struct mxc_gpio_port *port = gc->private;
313 	u32 gpio_idx = d->hwirq;
314 	int ret;
315 
316 	if (enable) {
317 		if (port->irq_high && (gpio_idx >= 16))
318 			ret = enable_irq_wake(port->irq_high);
319 		else
320 			ret = enable_irq_wake(port->irq);
321 	} else {
322 		if (port->irq_high && (gpio_idx >= 16))
323 			ret = disable_irq_wake(port->irq_high);
324 		else
325 			ret = disable_irq_wake(port->irq);
326 	}
327 
328 	return ret;
329 }
330 
mxc_gpio_init_gc(struct mxc_gpio_port * port,int irq_base)331 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
332 {
333 	struct irq_chip_generic *gc;
334 	struct irq_chip_type *ct;
335 	int rv;
336 
337 	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
338 					 port->base, handle_level_irq);
339 	if (!gc)
340 		return -ENOMEM;
341 	gc->private = port;
342 
343 	ct = gc->chip_types;
344 	ct->chip.irq_ack = irq_gc_ack_set_bit;
345 	ct->chip.irq_mask = irq_gc_mask_clr_bit;
346 	ct->chip.irq_unmask = irq_gc_mask_set_bit;
347 	ct->chip.irq_set_type = gpio_set_irq_type;
348 	ct->chip.irq_set_wake = gpio_set_wake_irq;
349 	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
350 	ct->regs.ack = GPIO_ISR;
351 	ct->regs.mask = GPIO_IMR;
352 
353 	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
354 					 IRQ_GC_INIT_NESTED_LOCK,
355 					 IRQ_NOREQUEST, 0);
356 
357 	return rv;
358 }
359 
mxc_gpio_to_irq(struct gpio_chip * gc,unsigned offset)360 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
361 {
362 	struct mxc_gpio_port *port = gpiochip_get_data(gc);
363 
364 	return irq_find_mapping(port->domain, offset);
365 }
366 
mxc_gpio_probe(struct platform_device * pdev)367 static int mxc_gpio_probe(struct platform_device *pdev)
368 {
369 	struct device_node *np = pdev->dev.of_node;
370 	struct mxc_gpio_port *port;
371 	int irq_count;
372 	int irq_base;
373 	int err;
374 
375 	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
376 	if (!port)
377 		return -ENOMEM;
378 
379 	port->dev = &pdev->dev;
380 
381 	port->hwdata = device_get_match_data(&pdev->dev);
382 
383 	port->base = devm_platform_ioremap_resource(pdev, 0);
384 	if (IS_ERR(port->base))
385 		return PTR_ERR(port->base);
386 
387 	irq_count = platform_irq_count(pdev);
388 	if (irq_count < 0)
389 		return irq_count;
390 
391 	if (irq_count > 1) {
392 		port->irq_high = platform_get_irq(pdev, 1);
393 		if (port->irq_high < 0)
394 			port->irq_high = 0;
395 	}
396 
397 	port->irq = platform_get_irq(pdev, 0);
398 	if (port->irq < 0)
399 		return port->irq;
400 
401 	/* the controller clock is optional */
402 	port->clk = devm_clk_get_optional(&pdev->dev, NULL);
403 	if (IS_ERR(port->clk))
404 		return PTR_ERR(port->clk);
405 
406 	err = clk_prepare_enable(port->clk);
407 	if (err) {
408 		dev_err(&pdev->dev, "Unable to enable clock.\n");
409 		return err;
410 	}
411 
412 	if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
413 		port->power_off = true;
414 
415 	/* disable the interrupt and clear the status */
416 	writel(0, port->base + GPIO_IMR);
417 	writel(~0, port->base + GPIO_ISR);
418 
419 	if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
420 		/*
421 		 * Setup one handler for all GPIO interrupts. Actually setting
422 		 * the handler is needed only once, but doing it for every port
423 		 * is more robust and easier.
424 		 */
425 		irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
426 	} else {
427 		/* setup one handler for each entry */
428 		irq_set_chained_handler_and_data(port->irq,
429 						 mx3_gpio_irq_handler, port);
430 		if (port->irq_high > 0)
431 			/* setup handler for GPIO 16 to 31 */
432 			irq_set_chained_handler_and_data(port->irq_high,
433 							 mx3_gpio_irq_handler,
434 							 port);
435 	}
436 
437 	err = bgpio_init(&port->gc, &pdev->dev, 4,
438 			 port->base + GPIO_PSR,
439 			 port->base + GPIO_DR, NULL,
440 			 port->base + GPIO_GDIR, NULL,
441 			 BGPIOF_READ_OUTPUT_REG_SET);
442 	if (err)
443 		goto out_bgio;
444 
445 	port->gc.request = gpiochip_generic_request;
446 	port->gc.free = gpiochip_generic_free;
447 	port->gc.to_irq = mxc_gpio_to_irq;
448 	port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
449 					     pdev->id * 32;
450 
451 	err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
452 	if (err)
453 		goto out_bgio;
454 
455 	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
456 	if (irq_base < 0) {
457 		err = irq_base;
458 		goto out_bgio;
459 	}
460 
461 	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
462 					     &irq_domain_simple_ops, NULL);
463 	if (!port->domain) {
464 		err = -ENODEV;
465 		goto out_bgio;
466 	}
467 
468 	/* gpio-mxc can be a generic irq chip */
469 	err = mxc_gpio_init_gc(port, irq_base);
470 	if (err < 0)
471 		goto out_irqdomain_remove;
472 
473 	list_add_tail(&port->node, &mxc_gpio_ports);
474 
475 	platform_set_drvdata(pdev, port);
476 
477 	return 0;
478 
479 out_irqdomain_remove:
480 	irq_domain_remove(port->domain);
481 out_bgio:
482 	clk_disable_unprepare(port->clk);
483 	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
484 	return err;
485 }
486 
mxc_gpio_save_regs(struct mxc_gpio_port * port)487 static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
488 {
489 	if (!port->power_off)
490 		return;
491 
492 	port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
493 	port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
494 	port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
495 	port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
496 	port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
497 	port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
498 }
499 
mxc_gpio_restore_regs(struct mxc_gpio_port * port)500 static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
501 {
502 	if (!port->power_off)
503 		return;
504 
505 	writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
506 	writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
507 	writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
508 	writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
509 	writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
510 	writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
511 }
512 
mxc_gpio_syscore_suspend(void)513 static int mxc_gpio_syscore_suspend(void)
514 {
515 	struct mxc_gpio_port *port;
516 
517 	/* walk through all ports */
518 	list_for_each_entry(port, &mxc_gpio_ports, node) {
519 		mxc_gpio_save_regs(port);
520 		clk_disable_unprepare(port->clk);
521 	}
522 
523 	return 0;
524 }
525 
mxc_gpio_syscore_resume(void)526 static void mxc_gpio_syscore_resume(void)
527 {
528 	struct mxc_gpio_port *port;
529 	int ret;
530 
531 	/* walk through all ports */
532 	list_for_each_entry(port, &mxc_gpio_ports, node) {
533 		ret = clk_prepare_enable(port->clk);
534 		if (ret) {
535 			pr_err("mxc: failed to enable gpio clock %d\n", ret);
536 			return;
537 		}
538 		mxc_gpio_restore_regs(port);
539 	}
540 }
541 
542 static struct syscore_ops mxc_gpio_syscore_ops = {
543 	.suspend = mxc_gpio_syscore_suspend,
544 	.resume = mxc_gpio_syscore_resume,
545 };
546 
547 static struct platform_driver mxc_gpio_driver = {
548 	.driver		= {
549 		.name	= "gpio-mxc",
550 		.of_match_table = mxc_gpio_dt_ids,
551 		.suppress_bind_attrs = true,
552 	},
553 	.probe		= mxc_gpio_probe,
554 };
555 
gpio_mxc_init(void)556 static int __init gpio_mxc_init(void)
557 {
558 	register_syscore_ops(&mxc_gpio_syscore_ops);
559 
560 	return platform_driver_register(&mxc_gpio_driver);
561 }
562 subsys_initcall(gpio_mxc_init);
563 
564 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
565 MODULE_DESCRIPTION("i.MX GPIO Driver");
566 MODULE_LICENSE("GPL");
567