1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R-Car MSTP clocks
4  *
5  * Copyright (C) 2013 Ideas On Board SPRL
6  * Copyright (C) 2015 Glider bvba
7  *
8  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
9  */
10 
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk/renesas.h>
15 #include <linux/device.h>
16 #include <linux/io.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/pm_clock.h>
20 #include <linux/pm_domain.h>
21 #include <linux/spinlock.h>
22 
23 /*
24  * MSTP clocks. We can't use standard gate clocks as we need to poll on the
25  * status register when enabling the clock.
26  */
27 
28 #define MSTP_MAX_CLOCKS		32
29 
30 /**
31  * struct mstp_clock_group - MSTP gating clocks group
32  *
33  * @data: clock specifier translation for clocks in this group
34  * @smstpcr: module stop control register
35  * @mstpsr: module stop status register (optional)
36  * @lock: protects writes to SMSTPCR
37  * @width_8bit: registers are 8-bit, not 32-bit
38  * @clks: clocks in this group
39  */
40 struct mstp_clock_group {
41 	struct clk_onecell_data data;
42 	void __iomem *smstpcr;
43 	void __iomem *mstpsr;
44 	spinlock_t lock;
45 	bool width_8bit;
46 	struct clk *clks[];
47 };
48 
49 /**
50  * struct mstp_clock - MSTP gating clock
51  * @hw: handle between common and hardware-specific interfaces
52  * @bit_index: control bit index
53  * @group: MSTP clocks group
54  */
55 struct mstp_clock {
56 	struct clk_hw hw;
57 	u32 bit_index;
58 	struct mstp_clock_group *group;
59 };
60 
61 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
62 
cpg_mstp_read(struct mstp_clock_group * group,u32 __iomem * reg)63 static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
64 				u32 __iomem *reg)
65 {
66 	return group->width_8bit ? readb(reg) : readl(reg);
67 }
68 
cpg_mstp_write(struct mstp_clock_group * group,u32 val,u32 __iomem * reg)69 static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
70 				  u32 __iomem *reg)
71 {
72 	group->width_8bit ? writeb(val, reg) : writel(val, reg);
73 }
74 
cpg_mstp_clock_endisable(struct clk_hw * hw,bool enable)75 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
76 {
77 	struct mstp_clock *clock = to_mstp_clock(hw);
78 	struct mstp_clock_group *group = clock->group;
79 	u32 bitmask = BIT(clock->bit_index);
80 	unsigned long flags;
81 	unsigned int i;
82 	u32 value;
83 
84 	spin_lock_irqsave(&group->lock, flags);
85 
86 	value = cpg_mstp_read(group, group->smstpcr);
87 	if (enable)
88 		value &= ~bitmask;
89 	else
90 		value |= bitmask;
91 	cpg_mstp_write(group, value, group->smstpcr);
92 
93 	if (!group->mstpsr) {
94 		/* dummy read to ensure write has completed */
95 		cpg_mstp_read(group, group->smstpcr);
96 		barrier_data(group->smstpcr);
97 	}
98 
99 	spin_unlock_irqrestore(&group->lock, flags);
100 
101 	if (!enable || !group->mstpsr)
102 		return 0;
103 
104 	for (i = 1000; i > 0; --i) {
105 		if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
106 			break;
107 		cpu_relax();
108 	}
109 
110 	if (!i) {
111 		pr_err("%s: failed to enable %p[%d]\n", __func__,
112 		       group->smstpcr, clock->bit_index);
113 		return -ETIMEDOUT;
114 	}
115 
116 	return 0;
117 }
118 
cpg_mstp_clock_enable(struct clk_hw * hw)119 static int cpg_mstp_clock_enable(struct clk_hw *hw)
120 {
121 	return cpg_mstp_clock_endisable(hw, true);
122 }
123 
cpg_mstp_clock_disable(struct clk_hw * hw)124 static void cpg_mstp_clock_disable(struct clk_hw *hw)
125 {
126 	cpg_mstp_clock_endisable(hw, false);
127 }
128 
cpg_mstp_clock_is_enabled(struct clk_hw * hw)129 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
130 {
131 	struct mstp_clock *clock = to_mstp_clock(hw);
132 	struct mstp_clock_group *group = clock->group;
133 	u32 value;
134 
135 	if (group->mstpsr)
136 		value = cpg_mstp_read(group, group->mstpsr);
137 	else
138 		value = cpg_mstp_read(group, group->smstpcr);
139 
140 	return !(value & BIT(clock->bit_index));
141 }
142 
143 static const struct clk_ops cpg_mstp_clock_ops = {
144 	.enable = cpg_mstp_clock_enable,
145 	.disable = cpg_mstp_clock_disable,
146 	.is_enabled = cpg_mstp_clock_is_enabled,
147 };
148 
cpg_mstp_clock_register(const char * name,const char * parent_name,unsigned int index,struct mstp_clock_group * group)149 static struct clk * __init cpg_mstp_clock_register(const char *name,
150 	const char *parent_name, unsigned int index,
151 	struct mstp_clock_group *group)
152 {
153 	struct clk_init_data init = {};
154 	struct mstp_clock *clock;
155 	struct clk *clk;
156 
157 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
158 	if (!clock)
159 		return ERR_PTR(-ENOMEM);
160 
161 	init.name = name;
162 	init.ops = &cpg_mstp_clock_ops;
163 	init.flags = CLK_SET_RATE_PARENT;
164 	/* INTC-SYS is the module clock of the GIC, and must not be disabled */
165 	if (!strcmp(name, "intc-sys")) {
166 		pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
167 		init.flags |= CLK_IS_CRITICAL;
168 	}
169 	init.parent_names = &parent_name;
170 	init.num_parents = 1;
171 
172 	clock->bit_index = index;
173 	clock->group = group;
174 	clock->hw.init = &init;
175 
176 	clk = clk_register(NULL, &clock->hw);
177 
178 	if (IS_ERR(clk))
179 		kfree(clock);
180 
181 	return clk;
182 }
183 
cpg_mstp_clocks_init(struct device_node * np)184 static void __init cpg_mstp_clocks_init(struct device_node *np)
185 {
186 	struct mstp_clock_group *group;
187 	const char *idxname;
188 	struct clk **clks;
189 	unsigned int i;
190 
191 	group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);
192 	if (!group)
193 		return;
194 
195 	clks = group->clks;
196 	spin_lock_init(&group->lock);
197 	group->data.clks = clks;
198 
199 	group->smstpcr = of_iomap(np, 0);
200 	group->mstpsr = of_iomap(np, 1);
201 
202 	if (group->smstpcr == NULL) {
203 		pr_err("%s: failed to remap SMSTPCR\n", __func__);
204 		kfree(group);
205 		return;
206 	}
207 
208 	if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
209 		group->width_8bit = true;
210 
211 	for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
212 		clks[i] = ERR_PTR(-ENOENT);
213 
214 	if (of_find_property(np, "clock-indices", &i))
215 		idxname = "clock-indices";
216 	else
217 		idxname = "renesas,clock-indices";
218 
219 	for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
220 		const char *parent_name;
221 		const char *name;
222 		u32 clkidx;
223 		int ret;
224 
225 		/* Skip clocks with no name. */
226 		ret = of_property_read_string_index(np, "clock-output-names",
227 						    i, &name);
228 		if (ret < 0 || strlen(name) == 0)
229 			continue;
230 
231 		parent_name = of_clk_get_parent_name(np, i);
232 		ret = of_property_read_u32_index(np, idxname, i, &clkidx);
233 		if (parent_name == NULL || ret < 0)
234 			break;
235 
236 		if (clkidx >= MSTP_MAX_CLOCKS) {
237 			pr_err("%s: invalid clock %pOFn %s index %u\n",
238 			       __func__, np, name, clkidx);
239 			continue;
240 		}
241 
242 		clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
243 						       clkidx, group);
244 		if (!IS_ERR(clks[clkidx])) {
245 			group->data.clk_num = max(group->data.clk_num,
246 						  clkidx + 1);
247 			/*
248 			 * Register a clkdev to let board code retrieve the
249 			 * clock by name and register aliases for non-DT
250 			 * devices.
251 			 *
252 			 * FIXME: Remove this when all devices that require a
253 			 * clock will be instantiated from DT.
254 			 */
255 			clk_register_clkdev(clks[clkidx], name, NULL);
256 		} else {
257 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
258 			       __func__, np, name, PTR_ERR(clks[clkidx]));
259 		}
260 	}
261 
262 	of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
263 }
264 CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
265 
cpg_mstp_attach_dev(struct generic_pm_domain * unused,struct device * dev)266 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
267 {
268 	struct device_node *np = dev->of_node;
269 	struct of_phandle_args clkspec;
270 	struct clk *clk;
271 	int i = 0;
272 	int error;
273 
274 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
275 					   &clkspec)) {
276 		if (of_device_is_compatible(clkspec.np,
277 					    "renesas,cpg-mstp-clocks"))
278 			goto found;
279 
280 		/* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
281 		if (of_node_name_eq(clkspec.np, "zb_clk"))
282 			goto found;
283 
284 		of_node_put(clkspec.np);
285 		i++;
286 	}
287 
288 	return 0;
289 
290 found:
291 	clk = of_clk_get_from_provider(&clkspec);
292 	of_node_put(clkspec.np);
293 
294 	if (IS_ERR(clk))
295 		return PTR_ERR(clk);
296 
297 	error = pm_clk_create(dev);
298 	if (error)
299 		goto fail_put;
300 
301 	error = pm_clk_add_clk(dev, clk);
302 	if (error)
303 		goto fail_destroy;
304 
305 	return 0;
306 
307 fail_destroy:
308 	pm_clk_destroy(dev);
309 fail_put:
310 	clk_put(clk);
311 	return error;
312 }
313 
cpg_mstp_detach_dev(struct generic_pm_domain * unused,struct device * dev)314 void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
315 {
316 	if (!pm_clk_no_clocks(dev))
317 		pm_clk_destroy(dev);
318 }
319 
cpg_mstp_add_clk_domain(struct device_node * np)320 void __init cpg_mstp_add_clk_domain(struct device_node *np)
321 {
322 	struct generic_pm_domain *pd;
323 	u32 ncells;
324 
325 	if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
326 		pr_warn("%pOF lacks #power-domain-cells\n", np);
327 		return;
328 	}
329 
330 	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
331 	if (!pd)
332 		return;
333 
334 	pd->name = np->name;
335 	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
336 		    GENPD_FLAG_ACTIVE_WAKEUP;
337 	pd->attach_dev = cpg_mstp_attach_dev;
338 	pd->detach_dev = cpg_mstp_detach_dev;
339 	pm_genpd_init(pd, &pm_domain_always_on_gov, false);
340 
341 	of_genpd_add_provider_simple(np, pd);
342 }
343