1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020, Martin Botka <martin.botka@somainline.org>
5 * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/bitops.h>
10 #include <linux/err.h>
11 #include <linux/platform_device.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/clk-provider.h>
16 #include <linux/regmap.h>
17 #include <linux/reset-controller.h>
18 #include <linux/clk.h>
19
20
21 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
22
23 #include "common.h"
24 #include "clk-regmap.h"
25 #include "clk-regmap-divider.h"
26 #include "clk-alpha-pll.h"
27 #include "clk-rcg.h"
28 #include "clk-branch.h"
29 #include "reset.h"
30 #include "gdsc.h"
31
32 enum {
33 P_XO,
34 P_DSI0PLL_BYTE,
35 P_DSI0PLL,
36 P_DSI1PLL_BYTE,
37 P_DSI1PLL,
38 P_GPLL0,
39 P_GPLL0_DIV,
40 P_MMPLL0,
41 P_MMPLL10,
42 P_MMPLL3,
43 P_MMPLL4,
44 P_MMPLL5,
45 P_MMPLL6,
46 P_MMPLL7,
47 P_MMPLL8,
48 P_SLEEP_CLK,
49 P_DP_PHY_PLL_LINK_CLK,
50 P_DP_PHY_PLL_VCO_DIV,
51 };
52
53 static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map[] = {
54 { P_XO, 0 },
55 { P_MMPLL0, 1 },
56 { P_MMPLL4, 2 },
57 { P_MMPLL7, 3 },
58 { P_MMPLL8, 4 },
59 { P_GPLL0, 5 },
60 { P_GPLL0_DIV, 6 },
61 };
62
63 /* Voteable PLL */
64 static struct clk_alpha_pll mmpll0 = {
65 .offset = 0xc000,
66 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
67 .clkr = {
68 .enable_reg = 0x1f0,
69 .enable_mask = BIT(0),
70 .hw.init = &(struct clk_init_data){
71 .name = "mmpll0",
72 .parent_data = &(const struct clk_parent_data){
73 .fw_name = "xo",
74 },
75 .num_parents = 1,
76 .ops = &clk_alpha_pll_ops,
77 },
78 },
79 };
80
81 static struct clk_alpha_pll mmpll6 = {
82 .offset = 0xf0,
83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
84 .clkr = {
85 .enable_reg = 0x1f0,
86 .enable_mask = BIT(2),
87 .hw.init = &(struct clk_init_data){
88 .name = "mmpll6",
89 .parent_data = &(const struct clk_parent_data){
90 .fw_name = "xo",
91 },
92 .num_parents = 1,
93 .ops = &clk_alpha_pll_ops,
94 },
95 },
96 };
97
98 /* APSS controlled PLLs */
99 static struct pll_vco vco[] = {
100 { 1000000000, 2000000000, 0 },
101 { 750000000, 1500000000, 1 },
102 { 500000000, 1000000000, 2 },
103 { 250000000, 500000000, 3 },
104 };
105
106 static struct pll_vco mmpll3_vco[] = {
107 { 750000000, 1500000000, 1 },
108 };
109
110 static const struct alpha_pll_config mmpll10_config = {
111 .l = 0x1e,
112 .config_ctl_val = 0x00004289,
113 .main_output_mask = 0x1,
114 };
115
116 static struct clk_alpha_pll mmpll10 = {
117 .offset = 0x190,
118 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
119 .clkr = {
120 .hw.init = &(struct clk_init_data){
121 .name = "mmpll10",
122 .parent_data = &(const struct clk_parent_data){
123 .fw_name = "xo",
124 },
125 .num_parents = 1,
126 .ops = &clk_alpha_pll_ops,
127 },
128 },
129 };
130
131 static const struct alpha_pll_config mmpll3_config = {
132 .l = 0x2e,
133 .config_ctl_val = 0x4001055b,
134 .vco_val = 0x1 << 20,
135 .vco_mask = 0x3 << 20,
136 .main_output_mask = 0x1,
137 };
138
139 static struct clk_alpha_pll mmpll3 = {
140 .offset = 0x0,
141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
142 .vco_table = mmpll3_vco,
143 .num_vco = ARRAY_SIZE(mmpll3_vco),
144 .clkr = {
145 .hw.init = &(struct clk_init_data){
146 .name = "mmpll3",
147 .parent_data = &(const struct clk_parent_data){
148 .fw_name = "xo",
149 },
150 .num_parents = 1,
151 .ops = &clk_alpha_pll_ops,
152 },
153 },
154 };
155
156 static const struct alpha_pll_config mmpll4_config = {
157 .l = 0x28,
158 .config_ctl_val = 0x4001055b,
159 .vco_val = 0x2 << 20,
160 .vco_mask = 0x3 << 20,
161 .main_output_mask = 0x1,
162 };
163
164 static struct clk_alpha_pll mmpll4 = {
165 .offset = 0x50,
166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
167 .vco_table = vco,
168 .num_vco = ARRAY_SIZE(vco),
169 .clkr = {
170 .hw.init = &(struct clk_init_data){
171 .name = "mmpll4",
172 .parent_data = &(const struct clk_parent_data){
173 .fw_name = "xo",
174 },
175 .num_parents = 1,
176 .ops = &clk_alpha_pll_ops,
177 },
178 },
179 };
180
181 static const struct alpha_pll_config mmpll5_config = {
182 .l = 0x2a,
183 .config_ctl_val = 0x4001055b,
184 .alpha_hi = 0xf8,
185 .alpha_en_mask = BIT(24),
186 .vco_val = 0x2 << 20,
187 .vco_mask = 0x3 << 20,
188 .main_output_mask = 0x1,
189 };
190
191 static struct clk_alpha_pll mmpll5 = {
192 .offset = 0xa0,
193 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
194 .vco_table = vco,
195 .num_vco = ARRAY_SIZE(vco),
196 .clkr = {
197 .hw.init = &(struct clk_init_data){
198 .name = "mmpll5",
199 .parent_data = &(const struct clk_parent_data){
200 .fw_name = "xo",
201 },
202 .num_parents = 1,
203 .ops = &clk_alpha_pll_ops,
204 },
205 },
206 };
207
208 static const struct alpha_pll_config mmpll7_config = {
209 .l = 0x32,
210 .config_ctl_val = 0x4001055b,
211 .vco_val = 0x2 << 20,
212 .vco_mask = 0x3 << 20,
213 .main_output_mask = 0x1,
214 };
215
216 static struct clk_alpha_pll mmpll7 = {
217 .offset = 0x140,
218 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
219 .vco_table = vco,
220 .num_vco = ARRAY_SIZE(vco),
221 .clkr = {
222 .hw.init = &(struct clk_init_data){
223 .name = "mmpll7",
224 .parent_data = &(const struct clk_parent_data){
225 .fw_name = "xo",
226 },
227 .num_parents = 1,
228 .ops = &clk_alpha_pll_ops,
229 },
230 },
231 };
232
233 static const struct alpha_pll_config mmpll8_config = {
234 .l = 0x30,
235 .alpha_hi = 0x70,
236 .alpha_en_mask = BIT(24),
237 .config_ctl_val = 0x4001055b,
238 .vco_val = 0x2 << 20,
239 .vco_mask = 0x3 << 20,
240 .main_output_mask = 0x1,
241 };
242
243 static struct clk_alpha_pll mmpll8 = {
244 .offset = 0x1c0,
245 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
246 .vco_table = vco,
247 .num_vco = ARRAY_SIZE(vco),
248 .clkr = {
249 .hw.init = &(struct clk_init_data){
250 .name = "mmpll8",
251 .parent_data = &(const struct clk_parent_data){
252 .fw_name = "xo",
253 },
254 .num_parents = 1,
255 .ops = &clk_alpha_pll_ops,
256 },
257 },
258 };
259
260 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div[] = {
261 { .fw_name = "xo" },
262 { .hw = &mmpll0.clkr.hw },
263 { .hw = &mmpll4.clkr.hw },
264 { .hw = &mmpll7.clkr.hw },
265 { .hw = &mmpll8.clkr.hw },
266 { .fw_name = "gpll0" },
267 { .fw_name = "gpll0_div" },
268 };
269
270 static const struct parent_map mmcc_xo_dsibyte_map[] = {
271 { P_XO, 0 },
272 { P_DSI0PLL_BYTE, 1 },
273 { P_DSI1PLL_BYTE, 2 },
274 };
275
276 static const struct clk_parent_data mmcc_xo_dsibyte[] = {
277 { .fw_name = "xo" },
278 { .fw_name = "dsi0pllbyte" },
279 { .fw_name = "dsi1pllbyte" },
280 };
281
282 static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
283 { P_XO, 0 },
284 { P_MMPLL0, 1 },
285 { P_MMPLL4, 2 },
286 { P_MMPLL7, 3 },
287 { P_MMPLL10, 4 },
288 { P_GPLL0, 5 },
289 { P_GPLL0_DIV, 6 },
290 };
291
292 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
293 { .fw_name = "xo" },
294 { .hw = &mmpll0.clkr.hw },
295 { .hw = &mmpll4.clkr.hw },
296 { .hw = &mmpll7.clkr.hw },
297 { .hw = &mmpll10.clkr.hw },
298 { .fw_name = "gpll0" },
299 { .fw_name = "gpll0_div" },
300 };
301
302 static const struct parent_map mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map[] = {
303 { P_XO, 0 },
304 { P_MMPLL4, 1 },
305 { P_MMPLL7, 2 },
306 { P_MMPLL10, 3 },
307 { P_SLEEP_CLK, 4 },
308 { P_GPLL0, 5 },
309 { P_GPLL0_DIV, 6 },
310 };
311
312 static const struct clk_parent_data mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div[] = {
313 { .fw_name = "xo" },
314 { .hw = &mmpll4.clkr.hw },
315 { .hw = &mmpll7.clkr.hw },
316 { .hw = &mmpll10.clkr.hw },
317 { .fw_name = "sleep_clk" },
318 { .fw_name = "gpll0" },
319 { .fw_name = "gpll0_div" },
320 };
321
322 static const struct parent_map mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map[] = {
323 { P_XO, 0 },
324 { P_MMPLL0, 1 },
325 { P_MMPLL7, 2 },
326 { P_MMPLL10, 3 },
327 { P_SLEEP_CLK, 4 },
328 { P_GPLL0, 5 },
329 { P_GPLL0_DIV, 6 },
330 };
331
332 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div[] = {
333 { .fw_name = "xo" },
334 { .hw = &mmpll0.clkr.hw },
335 { .hw = &mmpll7.clkr.hw },
336 { .hw = &mmpll10.clkr.hw },
337 { .fw_name = "sleep_clk" },
338 { .fw_name = "gpll0" },
339 { .fw_name = "gpll0_div" },
340 };
341
342 static const struct parent_map mmcc_xo_gpll0_gpll0_div_map[] = {
343 { P_XO, 0 },
344 { P_GPLL0, 5 },
345 { P_GPLL0_DIV, 6 },
346 };
347
348 static const struct clk_parent_data mmcc_xo_gpll0_gpll0_div[] = {
349 { .fw_name = "xo" },
350 { .fw_name = "gpll0" },
351 { .fw_name = "gpll0_div" },
352 };
353
354 static const struct parent_map mmcc_xo_dplink_dpvco_map[] = {
355 { P_XO, 0 },
356 { P_DP_PHY_PLL_LINK_CLK, 1 },
357 { P_DP_PHY_PLL_VCO_DIV, 2 },
358 };
359
360 static const struct clk_parent_data mmcc_xo_dplink_dpvco[] = {
361 { .fw_name = "xo" },
362 { .fw_name = "dp_link_2x_clk_divsel_five" },
363 { .fw_name = "dp_vco_divided_clk_src_mux" },
364 };
365
366 static const struct parent_map mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map[] = {
367 { P_XO, 0 },
368 { P_MMPLL0, 1 },
369 { P_MMPLL5, 2 },
370 { P_MMPLL7, 3 },
371 { P_GPLL0, 5 },
372 { P_GPLL0_DIV, 6 },
373 };
374
375 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div[] = {
376 { .fw_name = "xo" },
377 { .hw = &mmpll0.clkr.hw },
378 { .hw = &mmpll5.clkr.hw },
379 { .hw = &mmpll7.clkr.hw },
380 { .fw_name = "gpll0" },
381 { .fw_name = "gpll0_div" },
382 };
383
384 static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
385 { P_XO, 0 },
386 { P_DSI0PLL, 1 },
387 { P_DSI1PLL, 2 },
388 };
389
390 static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
391 { .fw_name = "xo" },
392 { .fw_name = "dsi0pll" },
393 { .fw_name = "dsi1pll" },
394 };
395
396 static const struct parent_map mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map[] = {
397 { P_XO, 0 },
398 { P_MMPLL0, 1 },
399 { P_MMPLL4, 2 },
400 { P_MMPLL7, 3 },
401 { P_MMPLL10, 4 },
402 { P_MMPLL6, 5 },
403 { P_GPLL0, 6 },
404 };
405
406 static const struct clk_parent_data mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0[] = {
407 { .fw_name = "xo" },
408 { .hw = &mmpll0.clkr.hw },
409 { .hw = &mmpll4.clkr.hw },
410 { .hw = &mmpll7.clkr.hw },
411 { .hw = &mmpll10.clkr.hw },
412 { .hw = &mmpll6.clkr.hw },
413 { .fw_name = "gpll0" },
414 };
415
416 static const struct parent_map mmcc_xo_mmpll0_gpll0_gpll0_div_map[] = {
417 { P_XO, 0 },
418 { P_MMPLL0, 1 },
419 { P_GPLL0, 5 },
420 { P_GPLL0_DIV, 6 },
421 };
422
423 static const struct clk_parent_data mmcc_xo_mmpll0_gpll0_gpll0_div[] = {
424 { .fw_name = "xo" },
425 { .hw = &mmpll0.clkr.hw },
426 { .fw_name = "gpll0" },
427 { .fw_name = "gpll0_div" },
428 };
429
430 static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6_map[] = {
431 { P_XO, 0 },
432 { P_MMPLL0, 1 },
433 { P_MMPLL4, 2 },
434 { P_MMPLL7, 3 },
435 { P_MMPLL10, 4 },
436 { P_GPLL0, 5 },
437 { P_MMPLL6, 6 },
438 };
439
440 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6[] = {
441 { .fw_name = "xo" },
442 { .hw = &mmpll0.clkr.hw },
443 { .hw = &mmpll4.clkr.hw },
444 { .hw = &mmpll7.clkr.hw },
445 { .hw = &mmpll10.clkr.hw },
446 { .fw_name = "gpll0" },
447 { .hw = &mmpll6.clkr.hw },
448 };
449
450 static const struct parent_map mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7_map[] = {
451 { P_XO, 0 },
452 { P_MMPLL0, 1 },
453 { P_MMPLL8, 2 },
454 { P_MMPLL3, 3 },
455 { P_MMPLL6, 4 },
456 { P_GPLL0, 5 },
457 { P_MMPLL7, 6 },
458 };
459
460 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7[] = {
461 { .fw_name = "xo" },
462 { .hw = &mmpll0.clkr.hw },
463 { .hw = &mmpll8.clkr.hw },
464 { .hw = &mmpll3.clkr.hw },
465 { .hw = &mmpll6.clkr.hw },
466 { .fw_name = "gpll0" },
467 { .hw = &mmpll7.clkr.hw },
468 };
469
470 static const struct freq_tbl ftbl_ahb_clk_src[] = {
471 F(19200000, P_XO, 1, 0, 0),
472 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
473 F(80800000, P_MMPLL0, 10, 0, 0),
474 { }
475 };
476
477 static struct clk_rcg2 ahb_clk_src = {
478 .cmd_rcgr = 0x5000,
479 .mnd_width = 0,
480 .hid_width = 5,
481 .parent_map = mmcc_xo_mmpll0_gpll0_gpll0_div_map,
482 .freq_tbl = ftbl_ahb_clk_src,
483 .clkr.hw.init = &(struct clk_init_data){
484 .name = "ahb_clk_src",
485 .parent_data = mmcc_xo_mmpll0_gpll0_gpll0_div,
486 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_gpll0_gpll0_div),
487 .ops = &clk_rcg2_ops,
488 },
489 };
490
491 static struct clk_rcg2 byte0_clk_src = {
492 .cmd_rcgr = 0x2120,
493 .mnd_width = 0,
494 .hid_width = 5,
495 .parent_map = mmcc_xo_dsibyte_map,
496 .clkr.hw.init = &(struct clk_init_data){
497 .name = "byte0_clk_src",
498 .parent_data = mmcc_xo_dsibyte,
499 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
500 .ops = &clk_byte2_ops,
501 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
502 },
503 };
504
505 static struct clk_rcg2 byte1_clk_src = {
506 .cmd_rcgr = 0x2140,
507 .mnd_width = 0,
508 .hid_width = 5,
509 .parent_map = mmcc_xo_dsibyte_map,
510 .clkr.hw.init = &(struct clk_init_data){
511 .name = "byte1_clk_src",
512 .parent_data = mmcc_xo_dsibyte,
513 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
514 .ops = &clk_byte2_ops,
515 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
516 },
517 };
518
519 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
520 F(10000, P_XO, 16, 1, 120),
521 F(24000, P_XO, 16, 1, 50),
522 F(6000000, P_GPLL0_DIV, 10, 1, 5),
523 F(12000000, P_GPLL0_DIV, 10, 2, 5),
524 F(13043478, P_GPLL0_DIV, 1, 1, 23),
525 F(24000000, P_GPLL0_DIV, 1, 2, 25),
526 F(50000000, P_GPLL0_DIV, 6, 0, 0),
527 F(100000000, P_GPLL0_DIV, 3, 0, 0),
528 F(200000000, P_GPLL0, 3, 0, 0),
529 { }
530 };
531
532 static struct clk_rcg2 camss_gp0_clk_src = {
533 .cmd_rcgr = 0x3420,
534 .mnd_width = 8,
535 .hid_width = 5,
536 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
537 .freq_tbl = ftbl_camss_gp0_clk_src,
538 .clkr.hw.init = &(struct clk_init_data){
539 .name = "camss_gp0_clk_src",
540 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
541 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
542 .ops = &clk_rcg2_ops,
543 },
544 };
545
546 static struct clk_rcg2 camss_gp1_clk_src = {
547 .cmd_rcgr = 0x3450,
548 .mnd_width = 8,
549 .hid_width = 5,
550 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
551 .freq_tbl = ftbl_camss_gp0_clk_src,
552 .clkr.hw.init = &(struct clk_init_data){
553 .name = "camss_gp1_clk_src",
554 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
555 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
556 .ops = &clk_rcg2_ops,
557 },
558 };
559
560 static const struct freq_tbl ftbl_cci_clk_src[] = {
561 F(37500000, P_GPLL0_DIV, 8, 0, 0),
562 F(50000000, P_GPLL0_DIV, 6, 0, 0),
563 F(100000000, P_GPLL0, 6, 0, 0),
564 { }
565 };
566
567 static struct clk_rcg2 cci_clk_src = {
568 .cmd_rcgr = 0x3300,
569 .mnd_width = 8,
570 .hid_width = 5,
571 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
572 .freq_tbl = ftbl_cci_clk_src,
573 .clkr.hw.init = &(struct clk_init_data){
574 .name = "cci_clk_src",
575 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
576 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
577 .ops = &clk_rcg2_ops,
578 },
579 };
580
581 static const struct freq_tbl ftbl_cpp_clk_src[] = {
582 F(120000000, P_GPLL0, 5, 0, 0),
583 F(256000000, P_MMPLL4, 3, 0, 0),
584 F(384000000, P_MMPLL4, 2, 0, 0),
585 F(480000000, P_MMPLL7, 2, 0, 0),
586 F(540000000, P_MMPLL6, 2, 0, 0),
587 F(576000000, P_MMPLL10, 1, 0, 0),
588 { }
589 };
590
591 static struct clk_rcg2 cpp_clk_src = {
592 .cmd_rcgr = 0x3640,
593 .mnd_width = 0,
594 .hid_width = 5,
595 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6_map,
596 .freq_tbl = ftbl_cpp_clk_src,
597 .clkr.hw.init = &(struct clk_init_data){
598 .name = "cpp_clk_src",
599 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6,
600 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6),
601 .ops = &clk_rcg2_ops,
602 },
603 };
604
605 static const struct freq_tbl ftbl_csi0_clk_src[] = {
606 F(100000000, P_GPLL0_DIV, 3, 0, 0),
607 F(200000000, P_GPLL0, 3, 0, 0),
608 F(310000000, P_MMPLL8, 3, 0, 0),
609 F(404000000, P_MMPLL0, 2, 0, 0),
610 F(465000000, P_MMPLL8, 2, 0, 0),
611 { }
612 };
613
614 static struct clk_rcg2 csi0_clk_src = {
615 .cmd_rcgr = 0x3090,
616 .mnd_width = 0,
617 .hid_width = 5,
618 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
619 .freq_tbl = ftbl_csi0_clk_src,
620 .clkr.hw.init = &(struct clk_init_data){
621 .name = "csi0_clk_src",
622 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
623 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
624 .ops = &clk_rcg2_ops,
625 },
626 };
627
628 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
629 F(100000000, P_GPLL0_DIV, 3, 0, 0),
630 F(200000000, P_GPLL0, 3, 0, 0),
631 F(269333333, P_MMPLL0, 3, 0, 0),
632 { }
633 };
634
635 static struct clk_rcg2 csi0phytimer_clk_src = {
636 .cmd_rcgr = 0x3000,
637 .mnd_width = 0,
638 .hid_width = 5,
639 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
640 .freq_tbl = ftbl_csi0phytimer_clk_src,
641 .clkr.hw.init = &(struct clk_init_data){
642 .name = "csi0phytimer_clk_src",
643 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
644 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
645 .ops = &clk_rcg2_ops,
646 },
647 };
648
649 static struct clk_rcg2 csi1_clk_src = {
650 .cmd_rcgr = 0x3100,
651 .mnd_width = 0,
652 .hid_width = 5,
653 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
654 .freq_tbl = ftbl_csi0_clk_src,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "csi1_clk_src",
657 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
658 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
659 .ops = &clk_rcg2_ops,
660 },
661 };
662
663 static struct clk_rcg2 csi1phytimer_clk_src = {
664 .cmd_rcgr = 0x3030,
665 .mnd_width = 0,
666 .hid_width = 5,
667 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
668 .freq_tbl = ftbl_csi0phytimer_clk_src,
669 .clkr.hw.init = &(struct clk_init_data){
670 .name = "csi1phytimer_clk_src",
671 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
672 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
673 .ops = &clk_rcg2_ops,
674 },
675 };
676
677 static struct clk_rcg2 csi2_clk_src = {
678 .cmd_rcgr = 0x3160,
679 .mnd_width = 0,
680 .hid_width = 5,
681 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
682 .freq_tbl = ftbl_csi0_clk_src,
683 .clkr.hw.init = &(struct clk_init_data){
684 .name = "csi2_clk_src",
685 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
686 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
687 .ops = &clk_rcg2_ops,
688 },
689 };
690
691 static struct clk_rcg2 csi2phytimer_clk_src = {
692 .cmd_rcgr = 0x3060,
693 .mnd_width = 0,
694 .hid_width = 5,
695 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
696 .freq_tbl = ftbl_csi0phytimer_clk_src,
697 .clkr.hw.init = &(struct clk_init_data){
698 .name = "csi2phytimer_clk_src",
699 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
700 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
701 .ops = &clk_rcg2_ops,
702 },
703 };
704
705 static struct clk_rcg2 csi3_clk_src = {
706 .cmd_rcgr = 0x31c0,
707 .mnd_width = 0,
708 .hid_width = 5,
709 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
710 .freq_tbl = ftbl_csi0_clk_src,
711 .clkr.hw.init = &(struct clk_init_data){
712 .name = "csi3_clk_src",
713 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
714 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
715 .ops = &clk_rcg2_ops,
716 },
717 };
718
719 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
720 F(100000000, P_GPLL0_DIV, 3, 0, 0),
721 F(200000000, P_GPLL0, 3, 0, 0),
722 F(269333333, P_MMPLL0, 3, 0, 0),
723 F(320000000, P_MMPLL7, 3, 0, 0),
724 { }
725 };
726
727 static struct clk_rcg2 csiphy_clk_src = {
728 .cmd_rcgr = 0x3800,
729 .mnd_width = 0,
730 .hid_width = 5,
731 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
732 .freq_tbl = ftbl_csiphy_clk_src,
733 .clkr.hw.init = &(struct clk_init_data){
734 .name = "csiphy_clk_src",
735 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
736 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
737 .ops = &clk_rcg2_ops,
738 },
739 };
740
741 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
742 F(19200000, P_XO, 1, 0, 0),
743 { }
744 };
745
746 static struct clk_rcg2 dp_aux_clk_src = {
747 .cmd_rcgr = 0x2260,
748 .mnd_width = 0,
749 .hid_width = 5,
750 .parent_map = mmcc_xo_gpll0_gpll0_div_map,
751 .freq_tbl = ftbl_dp_aux_clk_src,
752 .clkr.hw.init = &(struct clk_init_data){
753 .name = "dp_aux_clk_src",
754 .parent_data = mmcc_xo_gpll0_gpll0_div,
755 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div),
756 .ops = &clk_rcg2_ops,
757 },
758 };
759
760 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
761 F(101250000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
762 F(168750000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
763 F(337500000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
764 { }
765 };
766
767 static struct clk_rcg2 dp_crypto_clk_src = {
768 .cmd_rcgr = 0x2220,
769 .mnd_width = 8,
770 .hid_width = 5,
771 .parent_map = mmcc_xo_dplink_dpvco_map,
772 .freq_tbl = ftbl_dp_crypto_clk_src,
773 .clkr.hw.init = &(struct clk_init_data){
774 .name = "dp_crypto_clk_src",
775 .parent_data = mmcc_xo_dplink_dpvco,
776 .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco),
777 .ops = &clk_rcg2_ops,
778 },
779 };
780
781 static const struct freq_tbl ftbl_dp_gtc_clk_src[] = {
782 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
783 F(60000000, P_GPLL0, 10, 0, 0),
784 { }
785 };
786
787 static struct clk_rcg2 dp_gtc_clk_src = {
788 .cmd_rcgr = 0x2280,
789 .mnd_width = 0,
790 .hid_width = 5,
791 .parent_map = mmcc_xo_gpll0_gpll0_div_map,
792 .freq_tbl = ftbl_dp_gtc_clk_src,
793 .clkr.hw.init = &(struct clk_init_data){
794 .name = "dp_gtc_clk_src",
795 .parent_data = mmcc_xo_gpll0_gpll0_div,
796 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div),
797 .ops = &clk_rcg2_ops,
798 },
799 };
800
801 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
802 F(162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
803 F(270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
804 F(540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
805 { }
806 };
807
808 static struct clk_rcg2 dp_link_clk_src = {
809 .cmd_rcgr = 0x2200,
810 .mnd_width = 0,
811 .hid_width = 5,
812 .parent_map = mmcc_xo_dplink_dpvco_map,
813 .freq_tbl = ftbl_dp_link_clk_src,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "dp_link_clk_src",
816 .parent_data = mmcc_xo_dplink_dpvco,
817 .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco),
818 .ops = &clk_rcg2_ops,
819 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
820 },
821 };
822
823 static struct clk_rcg2 dp_pixel_clk_src = {
824 .cmd_rcgr = 0x2240,
825 .mnd_width = 16,
826 .hid_width = 5,
827 .parent_map = mmcc_xo_dplink_dpvco_map,
828 .clkr.hw.init = &(struct clk_init_data){
829 .name = "dp_pixel_clk_src",
830 .parent_data = mmcc_xo_dplink_dpvco,
831 .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco),
832 .ops = &clk_dp_ops,
833 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
834 },
835 };
836
837 static struct clk_rcg2 esc0_clk_src = {
838 .cmd_rcgr = 0x2160,
839 .mnd_width = 0,
840 .hid_width = 5,
841 .parent_map = mmcc_xo_dsibyte_map,
842 .clkr.hw.init = &(struct clk_init_data){
843 .name = "esc0_clk_src",
844 .parent_data = mmcc_xo_dsibyte,
845 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
846 .ops = &clk_rcg2_ops,
847 },
848 };
849
850 static struct clk_rcg2 esc1_clk_src = {
851 .cmd_rcgr = 0x2180,
852 .mnd_width = 0,
853 .hid_width = 5,
854 .parent_map = mmcc_xo_dsibyte_map,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "esc1_clk_src",
857 .parent_data = mmcc_xo_dsibyte,
858 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
859 .ops = &clk_rcg2_ops,
860 },
861 };
862
863 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
864 F(66666667, P_GPLL0_DIV, 4.5, 0, 0),
865 F(133333333, P_GPLL0, 4.5, 0, 0),
866 F(219428571, P_MMPLL4, 3.5, 0, 0),
867 F(320000000, P_MMPLL7, 3, 0, 0),
868 F(480000000, P_MMPLL7, 2, 0, 0),
869 { }
870 };
871
872 static struct clk_rcg2 jpeg0_clk_src = {
873 .cmd_rcgr = 0x3500,
874 .mnd_width = 0,
875 .hid_width = 5,
876 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
877 .freq_tbl = ftbl_jpeg0_clk_src,
878 .clkr.hw.init = &(struct clk_init_data){
879 .name = "jpeg0_clk_src",
880 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
881 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
882 .ops = &clk_rcg2_ops,
883 },
884 };
885
886 static const struct freq_tbl ftbl_mclk0_clk_src[] = {
887 F(4800000, P_XO, 4, 0, 0),
888 F(6000000, P_GPLL0_DIV, 10, 1, 5),
889 F(8000000, P_GPLL0_DIV, 1, 2, 75),
890 F(9600000, P_XO, 2, 0, 0),
891 F(16666667, P_GPLL0_DIV, 2, 1, 9),
892 F(19200000, P_XO, 1, 0, 0),
893 F(24000000, P_MMPLL10, 1, 1, 24),
894 F(33333333, P_GPLL0_DIV, 1, 1, 9),
895 F(48000000, P_GPLL0, 1, 2, 25),
896 F(66666667, P_GPLL0, 1, 1, 9),
897 { }
898 };
899
900 static struct clk_rcg2 mclk0_clk_src = {
901 .cmd_rcgr = 0x3360,
902 .mnd_width = 8,
903 .hid_width = 5,
904 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
905 .freq_tbl = ftbl_mclk0_clk_src,
906 .clkr.hw.init = &(struct clk_init_data){
907 .name = "mclk0_clk_src",
908 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
909 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
910 .ops = &clk_rcg2_ops,
911 },
912 };
913
914 static struct clk_rcg2 mclk1_clk_src = {
915 .cmd_rcgr = 0x3390,
916 .mnd_width = 8,
917 .hid_width = 5,
918 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
919 .freq_tbl = ftbl_mclk0_clk_src,
920 .clkr.hw.init = &(struct clk_init_data){
921 .name = "mclk1_clk_src",
922 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
923 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
924 .ops = &clk_rcg2_ops,
925 },
926 };
927
928 static struct clk_rcg2 mclk2_clk_src = {
929 .cmd_rcgr = 0x33c0,
930 .mnd_width = 8,
931 .hid_width = 5,
932 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
933 .freq_tbl = ftbl_mclk0_clk_src,
934 .clkr.hw.init = &(struct clk_init_data){
935 .name = "mclk2_clk_src",
936 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
937 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
938 .ops = &clk_rcg2_ops,
939 },
940 };
941
942 static struct clk_rcg2 mclk3_clk_src = {
943 .cmd_rcgr = 0x33f0,
944 .mnd_width = 8,
945 .hid_width = 5,
946 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
947 .freq_tbl = ftbl_mclk0_clk_src,
948 .clkr.hw.init = &(struct clk_init_data){
949 .name = "mclk3_clk_src",
950 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
951 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
952 .ops = &clk_rcg2_ops,
953 },
954 };
955
956 static const struct freq_tbl ftbl_mdp_clk_src[] = {
957 F(100000000, P_GPLL0_DIV, 3, 0, 0),
958 F(150000000, P_GPLL0_DIV, 2, 0, 0),
959 F(171428571, P_GPLL0, 3.5, 0, 0),
960 F(200000000, P_GPLL0, 3, 0, 0),
961 F(275000000, P_MMPLL5, 3, 0, 0),
962 F(300000000, P_GPLL0, 2, 0, 0),
963 F(330000000, P_MMPLL5, 2.5, 0, 0),
964 F(412500000, P_MMPLL5, 2, 0, 0),
965 { }
966 };
967
968 static struct clk_rcg2 mdp_clk_src = {
969 .cmd_rcgr = 0x2040,
970 .mnd_width = 0,
971 .hid_width = 5,
972 .parent_map = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map,
973 .freq_tbl = ftbl_mdp_clk_src,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "mdp_clk_src",
976 .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div,
977 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div),
978 .ops = &clk_rcg2_ops,
979 },
980 };
981
982 static struct clk_rcg2 pclk0_clk_src = {
983 .cmd_rcgr = 0x2000,
984 .mnd_width = 8,
985 .hid_width = 5,
986 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
987 .clkr.hw.init = &(struct clk_init_data){
988 .name = "pclk0_clk_src",
989 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
990 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
991 .ops = &clk_pixel_ops,
992 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
993 },
994 };
995
996 static struct clk_rcg2 pclk1_clk_src = {
997 .cmd_rcgr = 0x2020,
998 .mnd_width = 8,
999 .hid_width = 5,
1000 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
1001 .clkr.hw.init = &(struct clk_init_data){
1002 .name = "pclk1_clk_src",
1003 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
1004 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
1005 .ops = &clk_pixel_ops,
1006 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1007 },
1008 };
1009
1010 static const struct freq_tbl ftbl_rot_clk_src[] = {
1011 F(171428571, P_GPLL0, 3.5, 0, 0),
1012 F(275000000, P_MMPLL5, 3, 0, 0),
1013 F(300000000, P_GPLL0, 2, 0, 0),
1014 F(330000000, P_MMPLL5, 2.5, 0, 0),
1015 F(412500000, P_MMPLL5, 2, 0, 0),
1016 { }
1017 };
1018
1019 static struct clk_rcg2 rot_clk_src = {
1020 .cmd_rcgr = 0x21a0,
1021 .mnd_width = 0,
1022 .hid_width = 5,
1023 .parent_map = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map,
1024 .freq_tbl = ftbl_rot_clk_src,
1025 .clkr.hw.init = &(struct clk_init_data){
1026 .name = "rot_clk_src",
1027 .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div,
1028 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div),
1029 .ops = &clk_rcg2_ops,
1030 },
1031 };
1032
1033 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1034 F(120000000, P_GPLL0, 5, 0, 0),
1035 F(200000000, P_GPLL0, 3, 0, 0),
1036 F(256000000, P_MMPLL4, 3, 0, 0),
1037 F(300000000, P_GPLL0, 2, 0, 0),
1038 F(404000000, P_MMPLL0, 2, 0, 0),
1039 F(480000000, P_MMPLL7, 2, 0, 0),
1040 F(540000000, P_MMPLL6, 2, 0, 0),
1041 F(576000000, P_MMPLL10, 1, 0, 0),
1042 { }
1043 };
1044
1045 static struct clk_rcg2 vfe0_clk_src = {
1046 .cmd_rcgr = 0x3600,
1047 .mnd_width = 0,
1048 .hid_width = 5,
1049 .parent_map = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map,
1050 .freq_tbl = ftbl_vfe0_clk_src,
1051 .clkr.hw.init = &(struct clk_init_data){
1052 .name = "vfe0_clk_src",
1053 .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0,
1054 .num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0),
1055 .ops = &clk_rcg2_ops,
1056 },
1057 };
1058
1059 static struct clk_rcg2 vfe1_clk_src = {
1060 .cmd_rcgr = 0x3620,
1061 .mnd_width = 0,
1062 .hid_width = 5,
1063 .parent_map = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map,
1064 .freq_tbl = ftbl_vfe0_clk_src,
1065 .clkr.hw.init = &(struct clk_init_data){
1066 .name = "vfe1_clk_src",
1067 .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0,
1068 .num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0),
1069 .ops = &clk_rcg2_ops,
1070 },
1071 };
1072
1073 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1074 F(133333333, P_GPLL0, 4.5, 0, 0),
1075 F(269333333, P_MMPLL0, 3, 0, 0),
1076 F(320000000, P_MMPLL7, 3, 0, 0),
1077 F(404000000, P_MMPLL0, 2, 0, 0),
1078 F(441600000, P_MMPLL3, 2, 0, 0),
1079 F(518400000, P_MMPLL3, 2, 0, 0),
1080 { }
1081 };
1082
1083 static struct clk_rcg2 video_core_clk_src = {
1084 .cmd_rcgr = 0x1000,
1085 .mnd_width = 0,
1086 .hid_width = 5,
1087 .parent_map = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7_map,
1088 .freq_tbl = ftbl_video_core_clk_src,
1089 .clkr.hw.init = &(struct clk_init_data){
1090 .name = "video_core_clk_src",
1091 .parent_data = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7,
1092 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7),
1093 .ops = &clk_rcg2_ops,
1094 .flags = CLK_IS_CRITICAL,
1095 },
1096 };
1097
1098 static struct clk_rcg2 vsync_clk_src = {
1099 .cmd_rcgr = 0x2080,
1100 .mnd_width = 0,
1101 .hid_width = 5,
1102 .parent_map = mmcc_xo_gpll0_gpll0_div_map,
1103 .freq_tbl = ftbl_dp_aux_clk_src,
1104 .clkr.hw.init = &(struct clk_init_data){
1105 .name = "vsync_clk_src",
1106 .parent_data = mmcc_xo_gpll0_gpll0_div,
1107 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div),
1108 .ops = &clk_rcg2_ops,
1109 },
1110 };
1111
1112 static struct clk_branch bimc_smmu_ahb_clk = {
1113 .halt_reg = 0xe004,
1114 .halt_check = BRANCH_VOTED,
1115 .hwcg_reg = 0xe004,
1116 .hwcg_bit = 1,
1117 .clkr = {
1118 .enable_reg = 0xe004,
1119 .enable_mask = BIT(0),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "bimc_smmu_ahb_clk",
1122 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1123 .num_parents = 1,
1124 .ops = &clk_branch2_ops,
1125 },
1126 },
1127 };
1128
1129 static struct clk_branch bimc_smmu_axi_clk = {
1130 .halt_reg = 0xe008,
1131 .halt_check = BRANCH_VOTED,
1132 .hwcg_reg = 0xe008,
1133 .hwcg_bit = 1,
1134 .clkr = {
1135 .enable_reg = 0xe008,
1136 .enable_mask = BIT(0),
1137 .hw.init = &(struct clk_init_data){
1138 .name = "bimc_smmu_axi_clk",
1139 .ops = &clk_branch2_ops,
1140 },
1141 },
1142 };
1143
1144 static struct clk_branch camss_ahb_clk = {
1145 .halt_reg = 0x348c,
1146 .halt_check = BRANCH_HALT,
1147 .hwcg_reg = 0x348c,
1148 .hwcg_bit = 1,
1149 .clkr = {
1150 .enable_reg = 0x348c,
1151 .enable_mask = BIT(0),
1152 .hw.init = &(struct clk_init_data){
1153 .name = "camss_ahb_clk",
1154 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1155 .num_parents = 1,
1156 .ops = &clk_branch2_ops,
1157 },
1158 },
1159 };
1160
1161 static struct clk_branch camss_cci_ahb_clk = {
1162 .halt_reg = 0x3348,
1163 .halt_check = BRANCH_HALT,
1164 .clkr = {
1165 .enable_reg = 0x3348,
1166 .enable_mask = BIT(0),
1167 .hw.init = &(struct clk_init_data){
1168 .name = "camss_cci_ahb_clk",
1169 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1170 .num_parents = 1,
1171 .flags = CLK_SET_RATE_PARENT,
1172 .ops = &clk_branch2_ops,
1173 },
1174 },
1175 };
1176
1177 static struct clk_branch camss_cci_clk = {
1178 .halt_reg = 0x3344,
1179 .halt_check = BRANCH_HALT,
1180 .clkr = {
1181 .enable_reg = 0x3344,
1182 .enable_mask = BIT(0),
1183 .hw.init = &(struct clk_init_data){
1184 .name = "camss_cci_clk",
1185 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1186 .num_parents = 1,
1187 .flags = CLK_SET_RATE_PARENT,
1188 .ops = &clk_branch2_ops,
1189 },
1190 },
1191 };
1192
1193 static struct clk_branch camss_cpp_ahb_clk = {
1194 .halt_reg = 0x36b4,
1195 .halt_check = BRANCH_HALT,
1196 .clkr = {
1197 .enable_reg = 0x36b4,
1198 .enable_mask = BIT(0),
1199 .hw.init = &(struct clk_init_data){
1200 .name = "camss_cpp_ahb_clk",
1201 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1202 .num_parents = 1,
1203 .ops = &clk_branch2_ops,
1204 },
1205 },
1206 };
1207
1208 static struct clk_branch camss_cpp_axi_clk = {
1209 .halt_reg = 0x36c4,
1210 .halt_check = BRANCH_HALT,
1211 .clkr = {
1212 .enable_reg = 0x36c4,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "camss_cpp_axi_clk",
1216 .ops = &clk_branch2_ops,
1217 },
1218 },
1219 };
1220
1221 static struct clk_branch camss_cpp_clk = {
1222 .halt_reg = 0x36b0,
1223 .halt_check = BRANCH_HALT,
1224 .clkr = {
1225 .enable_reg = 0x36b0,
1226 .enable_mask = BIT(0),
1227 .hw.init = &(struct clk_init_data){
1228 .name = "camss_cpp_clk",
1229 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
1230 .num_parents = 1,
1231 .flags = CLK_SET_RATE_PARENT,
1232 .ops = &clk_branch2_ops,
1233 },
1234 },
1235 };
1236
1237 static struct clk_branch camss_cpp_vbif_ahb_clk = {
1238 .halt_reg = 0x36c8,
1239 .halt_check = BRANCH_HALT,
1240 .clkr = {
1241 .enable_reg = 0x36c8,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "camss_cpp_vbif_ahb_clk",
1245 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1246 .num_parents = 1,
1247 .ops = &clk_branch2_ops,
1248 },
1249 },
1250 };
1251
1252 static struct clk_branch camss_csi0_ahb_clk = {
1253 .halt_reg = 0x30bc,
1254 .halt_check = BRANCH_HALT,
1255 .clkr = {
1256 .enable_reg = 0x30bc,
1257 .enable_mask = BIT(0),
1258 .hw.init = &(struct clk_init_data){
1259 .name = "camss_csi0_ahb_clk",
1260 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1261 .num_parents = 1,
1262 .ops = &clk_branch2_ops,
1263 },
1264 },
1265 };
1266
1267 static struct clk_branch camss_csi0_clk = {
1268 .halt_reg = 0x30b4,
1269 .halt_check = BRANCH_HALT,
1270 .clkr = {
1271 .enable_reg = 0x30b4,
1272 .enable_mask = BIT(0),
1273 .hw.init = &(struct clk_init_data){
1274 .name = "camss_csi0_clk",
1275 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1276 .num_parents = 1,
1277 .flags = CLK_SET_RATE_PARENT,
1278 .ops = &clk_branch2_ops,
1279 },
1280 },
1281 };
1282
1283 static struct clk_branch camss_csi0phytimer_clk = {
1284 .halt_reg = 0x3024,
1285 .halt_check = BRANCH_HALT,
1286 .clkr = {
1287 .enable_reg = 0x3024,
1288 .enable_mask = BIT(0),
1289 .hw.init = &(struct clk_init_data){
1290 .name = "camss_csi0phytimer_clk",
1291 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1292 .num_parents = 1,
1293 .flags = CLK_SET_RATE_PARENT,
1294 .ops = &clk_branch2_ops,
1295 },
1296 },
1297 };
1298
1299 static struct clk_branch camss_csi0pix_clk = {
1300 .halt_reg = 0x30e4,
1301 .halt_check = BRANCH_HALT,
1302 .clkr = {
1303 .enable_reg = 0x30e4,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(struct clk_init_data){
1306 .name = "camss_csi0pix_clk",
1307 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1308 .num_parents = 1,
1309 .ops = &clk_branch2_ops,
1310 },
1311 },
1312 };
1313
1314 static struct clk_branch camss_csi0rdi_clk = {
1315 .halt_reg = 0x30d4,
1316 .halt_check = BRANCH_HALT,
1317 .clkr = {
1318 .enable_reg = 0x30d4,
1319 .enable_mask = BIT(0),
1320 .hw.init = &(struct clk_init_data){
1321 .name = "camss_csi0rdi_clk",
1322 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1323 .num_parents = 1,
1324 .ops = &clk_branch2_ops,
1325 },
1326 },
1327 };
1328
1329 static struct clk_branch camss_csi1_ahb_clk = {
1330 .halt_reg = 0x3128,
1331 .halt_check = BRANCH_HALT,
1332 .clkr = {
1333 .enable_reg = 0x3128,
1334 .enable_mask = BIT(0),
1335 .hw.init = &(struct clk_init_data){
1336 .name = "camss_csi1_ahb_clk",
1337 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1338 .num_parents = 1,
1339 .ops = &clk_branch2_ops,
1340 },
1341 },
1342 };
1343
1344 static struct clk_branch camss_csi1_clk = {
1345 .halt_reg = 0x3124,
1346 .halt_check = BRANCH_HALT,
1347 .clkr = {
1348 .enable_reg = 0x3124,
1349 .enable_mask = BIT(0),
1350 .hw.init = &(struct clk_init_data){
1351 .name = "camss_csi1_clk",
1352 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1353 .num_parents = 1,
1354 .flags = CLK_SET_RATE_PARENT,
1355 .ops = &clk_branch2_ops,
1356 },
1357 },
1358 };
1359
1360 static struct clk_branch camss_csi1phytimer_clk = {
1361 .halt_reg = 0x3054,
1362 .halt_check = BRANCH_HALT,
1363 .clkr = {
1364 .enable_reg = 0x3054,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "camss_csi1phytimer_clk",
1368 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1369 .num_parents = 1,
1370 .flags = CLK_SET_RATE_PARENT,
1371 .ops = &clk_branch2_ops,
1372 },
1373 },
1374 };
1375
1376 static struct clk_branch camss_csi1pix_clk = {
1377 .halt_reg = 0x3154,
1378 .halt_check = BRANCH_HALT,
1379 .clkr = {
1380 .enable_reg = 0x3154,
1381 .enable_mask = BIT(0),
1382 .hw.init = &(struct clk_init_data){
1383 .name = "camss_csi1pix_clk",
1384 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1385 .num_parents = 1,
1386 .ops = &clk_branch2_ops,
1387 },
1388 },
1389 };
1390
1391 static struct clk_branch camss_csi1rdi_clk = {
1392 .halt_reg = 0x3144,
1393 .halt_check = BRANCH_HALT,
1394 .clkr = {
1395 .enable_reg = 0x3144,
1396 .enable_mask = BIT(0),
1397 .hw.init = &(struct clk_init_data){
1398 .name = "camss_csi1rdi_clk",
1399 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1400 .num_parents = 1,
1401 .ops = &clk_branch2_ops,
1402 },
1403 },
1404 };
1405
1406 static struct clk_branch camss_csi2_ahb_clk = {
1407 .halt_reg = 0x3188,
1408 .halt_check = BRANCH_HALT,
1409 .clkr = {
1410 .enable_reg = 0x3188,
1411 .enable_mask = BIT(0),
1412 .hw.init = &(struct clk_init_data){
1413 .name = "camss_csi2_ahb_clk",
1414 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1415 .num_parents = 1,
1416 .ops = &clk_branch2_ops,
1417 },
1418 },
1419 };
1420
1421 static struct clk_branch camss_csi2_clk = {
1422 .halt_reg = 0x3184,
1423 .halt_check = BRANCH_HALT,
1424 .clkr = {
1425 .enable_reg = 0x3184,
1426 .enable_mask = BIT(0),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "camss_csi2_clk",
1429 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1430 .num_parents = 1,
1431 .flags = CLK_SET_RATE_PARENT,
1432 .ops = &clk_branch2_ops,
1433 },
1434 },
1435 };
1436
1437 static struct clk_branch camss_csi2phytimer_clk = {
1438 .halt_reg = 0x3084,
1439 .halt_check = BRANCH_HALT,
1440 .clkr = {
1441 .enable_reg = 0x3084,
1442 .enable_mask = BIT(0),
1443 .hw.init = &(struct clk_init_data){
1444 .name = "camss_csi2phytimer_clk",
1445 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1446 .num_parents = 1,
1447 .flags = CLK_SET_RATE_PARENT,
1448 .ops = &clk_branch2_ops,
1449 },
1450 },
1451 };
1452
1453 static struct clk_branch camss_csi2pix_clk = {
1454 .halt_reg = 0x31b4,
1455 .halt_check = BRANCH_HALT,
1456 .clkr = {
1457 .enable_reg = 0x31b4,
1458 .enable_mask = BIT(0),
1459 .hw.init = &(struct clk_init_data){
1460 .name = "camss_csi2pix_clk",
1461 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1462 .num_parents = 1,
1463 .ops = &clk_branch2_ops,
1464 },
1465 },
1466 };
1467
1468 static struct clk_branch camss_csi2rdi_clk = {
1469 .halt_reg = 0x31a4,
1470 .halt_check = BRANCH_HALT,
1471 .clkr = {
1472 .enable_reg = 0x31a4,
1473 .enable_mask = BIT(0),
1474 .hw.init = &(struct clk_init_data){
1475 .name = "camss_csi2rdi_clk",
1476 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1477 .num_parents = 1,
1478 .ops = &clk_branch2_ops,
1479 },
1480 },
1481 };
1482
1483 static struct clk_branch camss_csi3_ahb_clk = {
1484 .halt_reg = 0x31e8,
1485 .halt_check = BRANCH_HALT,
1486 .clkr = {
1487 .enable_reg = 0x31e8,
1488 .enable_mask = BIT(0),
1489 .hw.init = &(struct clk_init_data){
1490 .name = "camss_csi3_ahb_clk",
1491 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1492 .num_parents = 1,
1493 .ops = &clk_branch2_ops,
1494 },
1495 },
1496 };
1497
1498 static struct clk_branch camss_csi3_clk = {
1499 .halt_reg = 0x31e4,
1500 .halt_check = BRANCH_HALT,
1501 .clkr = {
1502 .enable_reg = 0x31e4,
1503 .enable_mask = BIT(0),
1504 .hw.init = &(struct clk_init_data){
1505 .name = "camss_csi3_clk",
1506 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1507 .num_parents = 1,
1508 .flags = CLK_SET_RATE_PARENT,
1509 .ops = &clk_branch2_ops,
1510 },
1511 },
1512 };
1513
1514 static struct clk_branch camss_csi3pix_clk = {
1515 .halt_reg = 0x3214,
1516 .halt_check = BRANCH_HALT,
1517 .clkr = {
1518 .enable_reg = 0x3214,
1519 .enable_mask = BIT(0),
1520 .hw.init = &(struct clk_init_data){
1521 .name = "camss_csi3pix_clk",
1522 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1523 .num_parents = 1,
1524 .ops = &clk_branch2_ops,
1525 },
1526 },
1527 };
1528
1529 static struct clk_branch camss_csi3rdi_clk = {
1530 .halt_reg = 0x3204,
1531 .halt_check = BRANCH_HALT,
1532 .clkr = {
1533 .enable_reg = 0x3204,
1534 .enable_mask = BIT(0),
1535 .hw.init = &(struct clk_init_data){
1536 .name = "camss_csi3rdi_clk",
1537 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1538 .num_parents = 1,
1539 .ops = &clk_branch2_ops,
1540 },
1541 },
1542 };
1543
1544 static struct clk_branch camss_csi_vfe0_clk = {
1545 .halt_reg = 0x3704,
1546 .halt_check = BRANCH_HALT,
1547 .clkr = {
1548 .enable_reg = 0x3704,
1549 .enable_mask = BIT(0),
1550 .hw.init = &(struct clk_init_data){
1551 .name = "camss_csi_vfe0_clk",
1552 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1553 .num_parents = 1,
1554 .ops = &clk_branch2_ops,
1555 },
1556 },
1557 };
1558
1559 static struct clk_branch camss_csi_vfe1_clk = {
1560 .halt_reg = 0x3714,
1561 .halt_check = BRANCH_HALT,
1562 .clkr = {
1563 .enable_reg = 0x3714,
1564 .enable_mask = BIT(0),
1565 .hw.init = &(struct clk_init_data){
1566 .name = "camss_csi_vfe1_clk",
1567 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1568 .num_parents = 1,
1569 .ops = &clk_branch2_ops,
1570 },
1571 },
1572 };
1573
1574 static struct clk_branch camss_csiphy0_clk = {
1575 .halt_reg = 0x3740,
1576 .halt_check = BRANCH_HALT,
1577 .clkr = {
1578 .enable_reg = 0x3740,
1579 .enable_mask = BIT(0),
1580 .hw.init = &(struct clk_init_data){
1581 .name = "camss_csiphy0_clk",
1582 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1583 .num_parents = 1,
1584 .flags = CLK_SET_RATE_PARENT,
1585 .ops = &clk_branch2_ops,
1586 },
1587 },
1588 };
1589
1590 static struct clk_branch camss_csiphy1_clk = {
1591 .halt_reg = 0x3744,
1592 .halt_check = BRANCH_HALT,
1593 .clkr = {
1594 .enable_reg = 0x3744,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "camss_csiphy1_clk",
1598 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1599 .num_parents = 1,
1600 .flags = CLK_SET_RATE_PARENT,
1601 .ops = &clk_branch2_ops,
1602 },
1603 },
1604 };
1605
1606 static struct clk_branch camss_csiphy2_clk = {
1607 .halt_reg = 0x3748,
1608 .halt_check = BRANCH_HALT,
1609 .clkr = {
1610 .enable_reg = 0x3748,
1611 .enable_mask = BIT(0),
1612 .hw.init = &(struct clk_init_data){
1613 .name = "camss_csiphy2_clk",
1614 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1615 .num_parents = 1,
1616 .flags = CLK_SET_RATE_PARENT,
1617 .ops = &clk_branch2_ops,
1618 },
1619 },
1620 };
1621
1622
1623 static struct clk_branch camss_cphy_csid0_clk = {
1624 .halt_reg = 0x3730,
1625 .halt_check = BRANCH_HALT,
1626 .clkr = {
1627 .enable_reg = 0x3730,
1628 .enable_mask = BIT(0),
1629 .hw.init = &(struct clk_init_data){
1630 .name = "camss_cphy_csid0_clk",
1631 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy0_clk.clkr.hw },
1632 .num_parents = 1,
1633 .flags = CLK_SET_RATE_PARENT,
1634 .ops = &clk_branch2_ops,
1635 },
1636 },
1637 };
1638
1639 static struct clk_branch camss_cphy_csid1_clk = {
1640 .halt_reg = 0x3734,
1641 .halt_check = BRANCH_HALT,
1642 .clkr = {
1643 .enable_reg = 0x3734,
1644 .enable_mask = BIT(0),
1645 .hw.init = &(struct clk_init_data){
1646 .name = "camss_cphy_csid1_clk",
1647 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy1_clk.clkr.hw },
1648 .num_parents = 1,
1649 .flags = CLK_SET_RATE_PARENT,
1650 .ops = &clk_branch2_ops,
1651 },
1652 },
1653 };
1654
1655 static struct clk_branch camss_cphy_csid2_clk = {
1656 .halt_reg = 0x3738,
1657 .halt_check = BRANCH_HALT,
1658 .clkr = {
1659 .enable_reg = 0x3738,
1660 .enable_mask = BIT(0),
1661 .hw.init = &(struct clk_init_data){
1662 .name = "camss_cphy_csid2_clk",
1663 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy2_clk.clkr.hw },
1664 .num_parents = 1,
1665 .flags = CLK_SET_RATE_PARENT,
1666 .ops = &clk_branch2_ops,
1667 },
1668 },
1669 };
1670
1671 static struct clk_branch camss_cphy_csid3_clk = {
1672 .halt_reg = 0x373c,
1673 .halt_check = BRANCH_HALT,
1674 .clkr = {
1675 .enable_reg = 0x373c,
1676 .enable_mask = BIT(0),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "camss_cphy_csid3_clk",
1679 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1680 .num_parents = 1,
1681 .flags = CLK_SET_RATE_PARENT,
1682 .ops = &clk_branch2_ops,
1683 },
1684 },
1685 };
1686
1687 static struct clk_branch camss_gp0_clk = {
1688 .halt_reg = 0x3444,
1689 .halt_check = BRANCH_HALT,
1690 .clkr = {
1691 .enable_reg = 0x3444,
1692 .enable_mask = BIT(0),
1693 .hw.init = &(struct clk_init_data){
1694 .name = "camss_gp0_clk",
1695 .parent_hws = (const struct clk_hw *[]){ &camss_gp0_clk_src.clkr.hw },
1696 .num_parents = 1,
1697 .flags = CLK_SET_RATE_PARENT,
1698 .ops = &clk_branch2_ops,
1699 },
1700 },
1701 };
1702
1703 static struct clk_branch camss_gp1_clk = {
1704 .halt_reg = 0x3474,
1705 .halt_check = BRANCH_HALT,
1706 .clkr = {
1707 .enable_reg = 0x3474,
1708 .enable_mask = BIT(0),
1709 .hw.init = &(struct clk_init_data){
1710 .name = "camss_gp1_clk",
1711 .parent_hws = (const struct clk_hw *[]){ &camss_gp1_clk_src.clkr.hw },
1712 .num_parents = 1,
1713 .flags = CLK_SET_RATE_PARENT,
1714 .ops = &clk_branch2_ops,
1715 },
1716 },
1717 };
1718
1719 static struct clk_branch camss_ispif_ahb_clk = {
1720 .halt_reg = 0x3224,
1721 .halt_check = BRANCH_HALT,
1722 .clkr = {
1723 .enable_reg = 0x3224,
1724 .enable_mask = BIT(0),
1725 .hw.init = &(struct clk_init_data){
1726 .name = "camss_ispif_ahb_clk",
1727 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1728 .num_parents = 1,
1729 .ops = &clk_branch2_ops,
1730 },
1731 },
1732 };
1733
1734 static struct clk_branch camss_jpeg0_clk = {
1735 .halt_reg = 0x35a8,
1736 .halt_check = BRANCH_HALT,
1737 .clkr = {
1738 .enable_reg = 0x35a8,
1739 .enable_mask = BIT(0),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "camss_jpeg0_clk",
1742 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
1743 .num_parents = 1,
1744 .flags = CLK_SET_RATE_PARENT,
1745 .ops = &clk_branch2_ops,
1746 },
1747 },
1748 };
1749
1750 static struct clk_branch camss_jpeg_ahb_clk = {
1751 .halt_reg = 0x35b4,
1752 .halt_check = BRANCH_HALT,
1753 .clkr = {
1754 .enable_reg = 0x35b4,
1755 .enable_mask = BIT(0),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "camss_jpeg_ahb_clk",
1758 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1759 .num_parents = 1,
1760 .ops = &clk_branch2_ops,
1761 },
1762 },
1763 };
1764
1765 static struct clk_branch camss_jpeg_axi_clk = {
1766 .halt_reg = 0x35b8,
1767 .halt_check = BRANCH_HALT,
1768 .clkr = {
1769 .enable_reg = 0x35b8,
1770 .enable_mask = BIT(0),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "camss_jpeg_axi_clk",
1773 .ops = &clk_branch2_ops,
1774 },
1775 },
1776 };
1777
1778 static struct clk_branch throttle_camss_axi_clk = {
1779 .halt_reg = 0x3c3c,
1780 .halt_check = BRANCH_HALT,
1781 .clkr = {
1782 .enable_reg = 0x3c3c,
1783 .enable_mask = BIT(0),
1784 .hw.init = &(struct clk_init_data){
1785 .name = "throttle_camss_axi_clk",
1786 .ops = &clk_branch2_ops,
1787 },
1788 },
1789 };
1790
1791 static struct clk_branch camss_mclk0_clk = {
1792 .halt_reg = 0x3384,
1793 .halt_check = BRANCH_HALT,
1794 .clkr = {
1795 .enable_reg = 0x3384,
1796 .enable_mask = BIT(0),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "camss_mclk0_clk",
1799 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1800 .num_parents = 1,
1801 .flags = CLK_SET_RATE_PARENT,
1802 .ops = &clk_branch2_ops,
1803 },
1804 },
1805 };
1806
1807 static struct clk_branch camss_mclk1_clk = {
1808 .halt_reg = 0x33b4,
1809 .halt_check = BRANCH_HALT,
1810 .clkr = {
1811 .enable_reg = 0x33b4,
1812 .enable_mask = BIT(0),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "camss_mclk1_clk",
1815 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1816 .num_parents = 1,
1817 .flags = CLK_SET_RATE_PARENT,
1818 .ops = &clk_branch2_ops,
1819 },
1820 },
1821 };
1822
1823 static struct clk_branch camss_mclk2_clk = {
1824 .halt_reg = 0x33e4,
1825 .halt_check = BRANCH_HALT,
1826 .clkr = {
1827 .enable_reg = 0x33e4,
1828 .enable_mask = BIT(0),
1829 .hw.init = &(struct clk_init_data){
1830 .name = "camss_mclk2_clk",
1831 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1832 .num_parents = 1,
1833 .flags = CLK_SET_RATE_PARENT,
1834 .ops = &clk_branch2_ops,
1835 },
1836 },
1837 };
1838
1839 static struct clk_branch camss_mclk3_clk = {
1840 .halt_reg = 0x3414,
1841 .halt_check = BRANCH_HALT,
1842 .clkr = {
1843 .enable_reg = 0x3414,
1844 .enable_mask = BIT(0),
1845 .hw.init = &(struct clk_init_data){
1846 .name = "camss_mclk3_clk",
1847 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1848 .num_parents = 1,
1849 .flags = CLK_SET_RATE_PARENT,
1850 .ops = &clk_branch2_ops,
1851 },
1852 },
1853 };
1854
1855 static struct clk_branch camss_micro_ahb_clk = {
1856 .halt_reg = 0x3494,
1857 .halt_check = BRANCH_HALT,
1858 .clkr = {
1859 .enable_reg = 0x3494,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "camss_micro_ahb_clk",
1863 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1864 .num_parents = 1,
1865 .ops = &clk_branch2_ops,
1866 },
1867 },
1868 };
1869
1870 static struct clk_branch camss_top_ahb_clk = {
1871 .halt_reg = 0x3484,
1872 .halt_check = BRANCH_HALT,
1873 .clkr = {
1874 .enable_reg = 0x3484,
1875 .enable_mask = BIT(0),
1876 .hw.init = &(struct clk_init_data){
1877 .name = "camss_top_ahb_clk",
1878 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1879 .num_parents = 1,
1880 .ops = &clk_branch2_ops,
1881 },
1882 },
1883 };
1884
1885 static struct clk_branch camss_vfe0_ahb_clk = {
1886 .halt_reg = 0x3668,
1887 .halt_check = BRANCH_HALT,
1888 .clkr = {
1889 .enable_reg = 0x3668,
1890 .enable_mask = BIT(0),
1891 .hw.init = &(struct clk_init_data){
1892 .name = "camss_vfe0_ahb_clk",
1893 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1894 .num_parents = 1,
1895 .ops = &clk_branch2_ops,
1896 },
1897 },
1898 };
1899
1900 static struct clk_branch camss_vfe0_clk = {
1901 .halt_reg = 0x36a8,
1902 .halt_check = BRANCH_HALT,
1903 .clkr = {
1904 .enable_reg = 0x36a8,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "camss_vfe0_clk",
1908 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1909 .num_parents = 1,
1910 .flags = CLK_SET_RATE_PARENT,
1911 .ops = &clk_branch2_ops,
1912 },
1913 },
1914 };
1915
1916 static struct clk_branch camss_vfe0_stream_clk = {
1917 .halt_reg = 0x3720,
1918 .halt_check = BRANCH_HALT,
1919 .clkr = {
1920 .enable_reg = 0x3720,
1921 .enable_mask = BIT(0),
1922 .hw.init = &(struct clk_init_data){
1923 .name = "camss_vfe0_stream_clk",
1924 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1925 .num_parents = 1,
1926 .ops = &clk_branch2_ops,
1927 },
1928 },
1929 };
1930
1931 static struct clk_branch camss_vfe1_ahb_clk = {
1932 .halt_reg = 0x3678,
1933 .halt_check = BRANCH_HALT,
1934 .clkr = {
1935 .enable_reg = 0x3678,
1936 .enable_mask = BIT(0),
1937 .hw.init = &(struct clk_init_data){
1938 .name = "camss_vfe1_ahb_clk",
1939 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1940 .num_parents = 1,
1941 .ops = &clk_branch2_ops,
1942 },
1943 },
1944 };
1945
1946 static struct clk_branch camss_vfe1_clk = {
1947 .halt_reg = 0x36ac,
1948 .halt_check = BRANCH_HALT,
1949 .clkr = {
1950 .enable_reg = 0x36ac,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "camss_vfe1_clk",
1954 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1955 .num_parents = 1,
1956 .flags = CLK_SET_RATE_PARENT,
1957 .ops = &clk_branch2_ops,
1958 },
1959 },
1960 };
1961
1962 static struct clk_branch camss_vfe1_stream_clk = {
1963 .halt_reg = 0x3724,
1964 .halt_check = BRANCH_HALT,
1965 .clkr = {
1966 .enable_reg = 0x3724,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "camss_vfe1_stream_clk",
1970 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1971 .num_parents = 1,
1972 .ops = &clk_branch2_ops,
1973 },
1974 },
1975 };
1976
1977 static struct clk_branch camss_vfe_vbif_ahb_clk = {
1978 .halt_reg = 0x36b8,
1979 .halt_check = BRANCH_HALT,
1980 .clkr = {
1981 .enable_reg = 0x36b8,
1982 .enable_mask = BIT(0),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "camss_vfe_vbif_ahb_clk",
1985 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1986 .num_parents = 1,
1987 .ops = &clk_branch2_ops,
1988 },
1989 },
1990 };
1991
1992 static struct clk_branch camss_vfe_vbif_axi_clk = {
1993 .halt_reg = 0x36bc,
1994 .halt_check = BRANCH_HALT,
1995 .clkr = {
1996 .enable_reg = 0x36bc,
1997 .enable_mask = BIT(0),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "camss_vfe_vbif_axi_clk",
2000 .ops = &clk_branch2_ops,
2001 },
2002 },
2003 };
2004
2005 static struct clk_branch csiphy_ahb2crif_clk = {
2006 .halt_reg = 0x374c,
2007 .halt_check = BRANCH_HALT,
2008 .hwcg_reg = 0x374c,
2009 .hwcg_bit = 1,
2010 .clkr = {
2011 .enable_reg = 0x374c,
2012 .enable_mask = BIT(0),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "csiphy_ahb2crif_clk",
2015 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2016 .num_parents = 1,
2017 .ops = &clk_branch2_ops,
2018 },
2019 },
2020 };
2021
2022 static struct clk_branch mdss_ahb_clk = {
2023 .halt_reg = 0x2308,
2024 .halt_check = BRANCH_HALT,
2025 .hwcg_reg = 0x8a004,
2026 .hwcg_bit = 1,
2027 .clkr = {
2028 .enable_reg = 0x2308,
2029 .enable_mask = BIT(0),
2030 .hw.init = &(struct clk_init_data){
2031 .name = "mdss_ahb_clk",
2032 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2033 .flags = CLK_SET_RATE_PARENT,
2034 .num_parents = 1,
2035 .ops = &clk_branch2_ops,
2036 },
2037 },
2038 };
2039
2040 static const struct freq_tbl ftbl_axi_clk_src[] = {
2041 F(75000000, P_GPLL0, 8, 0, 0),
2042 F(171428571, P_GPLL0, 3.5, 0, 0),
2043 F(240000000, P_GPLL0, 2.5, 0, 0),
2044 F(323200000, P_MMPLL0, 2.5, 0, 0),
2045 F(406000000, P_MMPLL0, 2, 0, 0),
2046 { }
2047 };
2048
2049 /* RO to linux */
2050 static struct clk_rcg2 axi_clk_src = {
2051 .cmd_rcgr = 0xd000,
2052 .hid_width = 5,
2053 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
2054 .freq_tbl = ftbl_axi_clk_src,
2055 .clkr.hw.init = &(struct clk_init_data){
2056 .name = "axi_clk_src",
2057 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
2058 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
2059 .ops = &clk_rcg2_ops,
2060 },
2061 };
2062
2063 static struct clk_branch mdss_axi_clk = {
2064 .halt_reg = 0x2310,
2065 .halt_check = BRANCH_HALT,
2066 .clkr = {
2067 .enable_reg = 0x2310,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "mdss_axi_clk",
2071 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2072 .ops = &clk_branch2_ops,
2073 },
2074 },
2075 };
2076
2077 static struct clk_branch throttle_mdss_axi_clk = {
2078 .halt_reg = 0x246c,
2079 .halt_check = BRANCH_HALT,
2080 .hwcg_reg = 0x246c,
2081 .hwcg_bit = 1,
2082 .clkr = {
2083 .enable_reg = 0x246c,
2084 .enable_mask = BIT(0),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "throttle_mdss_axi_clk",
2087 .ops = &clk_branch2_ops,
2088 },
2089 },
2090 };
2091
2092 static struct clk_branch mdss_byte0_clk = {
2093 .halt_reg = 0x233c,
2094 .halt_check = BRANCH_HALT,
2095 .clkr = {
2096 .enable_reg = 0x233c,
2097 .enable_mask = BIT(0),
2098 .hw.init = &(struct clk_init_data){
2099 .name = "mdss_byte0_clk",
2100 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
2101 .num_parents = 1,
2102 .flags = CLK_SET_RATE_PARENT,
2103 .ops = &clk_branch2_ops,
2104 },
2105 },
2106 };
2107
2108 static struct clk_regmap_div mdss_byte0_intf_div_clk = {
2109 .reg = 0x237c,
2110 .shift = 0,
2111 .width = 2,
2112 /*
2113 * NOTE: Op does not work for div-3. Current assumption is that div-3
2114 * is not a recommended setting for this divider.
2115 */
2116 .clkr = {
2117 .hw.init = &(struct clk_init_data){
2118 .name = "mdss_byte0_intf_div_clk",
2119 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
2120 .num_parents = 1,
2121 .ops = &clk_regmap_div_ops,
2122 .flags = CLK_GET_RATE_NOCACHE,
2123 },
2124 },
2125 };
2126
2127 static struct clk_branch mdss_byte0_intf_clk = {
2128 .halt_reg = 0x2374,
2129 .halt_check = BRANCH_HALT,
2130 .clkr = {
2131 .enable_reg = 0x2374,
2132 .enable_mask = BIT(0),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "mdss_byte0_intf_clk",
2135 .parent_hws = (const struct clk_hw *[]){ &mdss_byte0_intf_div_clk.clkr.hw },
2136 .num_parents = 1,
2137 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2138 .ops = &clk_branch2_ops,
2139 },
2140 },
2141 };
2142
2143 static struct clk_branch mdss_byte1_clk = {
2144 .halt_reg = 0x2340,
2145 .halt_check = BRANCH_HALT,
2146 .clkr = {
2147 .enable_reg = 0x2340,
2148 .enable_mask = BIT(0),
2149 .hw.init = &(struct clk_init_data){
2150 .name = "mdss_byte1_clk",
2151 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
2152 .num_parents = 1,
2153 .flags = CLK_SET_RATE_PARENT,
2154 .ops = &clk_branch2_ops,
2155 },
2156 },
2157 };
2158
2159 static struct clk_regmap_div mdss_byte1_intf_div_clk = {
2160 .reg = 0x2380,
2161 .shift = 0,
2162 .width = 2,
2163 /*
2164 * NOTE: Op does not work for div-3. Current assumption is that div-3
2165 * is not a recommended setting for this divider.
2166 */
2167 .clkr = {
2168 .hw.init = &(struct clk_init_data){
2169 .name = "mdss_byte1_intf_div_clk",
2170 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
2171 .num_parents = 1,
2172 .ops = &clk_regmap_div_ops,
2173 .flags = CLK_GET_RATE_NOCACHE,
2174 },
2175 },
2176 };
2177
2178 static struct clk_branch mdss_byte1_intf_clk = {
2179 .halt_reg = 0x2378,
2180 .halt_check = BRANCH_HALT,
2181 .clkr = {
2182 .enable_reg = 0x2378,
2183 .enable_mask = BIT(0),
2184 .hw.init = &(struct clk_init_data){
2185 .name = "mdss_byte1_intf_clk",
2186 .parent_hws = (const struct clk_hw *[]){ &mdss_byte1_intf_div_clk.clkr.hw },
2187 .num_parents = 1,
2188 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2189 .ops = &clk_branch2_ops,
2190 },
2191 },
2192 };
2193
2194 static struct clk_branch mdss_dp_aux_clk = {
2195 .halt_reg = 0x2364,
2196 .halt_check = BRANCH_HALT,
2197 .clkr = {
2198 .enable_reg = 0x2364,
2199 .enable_mask = BIT(0),
2200 .hw.init = &(struct clk_init_data){
2201 .name = "mdss_dp_aux_clk",
2202 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
2203 .num_parents = 1,
2204 .flags = CLK_SET_RATE_PARENT,
2205 .ops = &clk_branch2_ops,
2206 },
2207 },
2208 };
2209
2210 static struct clk_branch mdss_dp_crypto_clk = {
2211 .halt_reg = 0x235c,
2212 .halt_check = BRANCH_HALT,
2213 .clkr = {
2214 .enable_reg = 0x235c,
2215 .enable_mask = BIT(0),
2216 .hw.init = &(struct clk_init_data){
2217 .name = "mdss_dp_crypto_clk",
2218 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
2219 .num_parents = 1,
2220 .flags = CLK_SET_RATE_PARENT,
2221 .ops = &clk_branch2_ops,
2222 },
2223 },
2224 };
2225
2226 static struct clk_branch mdss_dp_gtc_clk = {
2227 .halt_reg = 0x2368,
2228 .halt_check = BRANCH_HALT,
2229 .clkr = {
2230 .enable_reg = 0x2368,
2231 .enable_mask = BIT(0),
2232 .hw.init = &(struct clk_init_data){
2233 .name = "mdss_dp_gtc_clk",
2234 .parent_hws = (const struct clk_hw *[]){ &dp_gtc_clk_src.clkr.hw },
2235 .num_parents = 1,
2236 .flags = CLK_SET_RATE_PARENT,
2237 .ops = &clk_branch2_ops,
2238 },
2239 },
2240 };
2241
2242 static struct clk_branch mdss_dp_link_clk = {
2243 .halt_reg = 0x2354,
2244 .halt_check = BRANCH_HALT,
2245 .clkr = {
2246 .enable_reg = 0x2354,
2247 .enable_mask = BIT(0),
2248 .hw.init = &(struct clk_init_data){
2249 .name = "mdss_dp_link_clk",
2250 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
2251 .num_parents = 1,
2252 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2253 .ops = &clk_branch2_ops,
2254 },
2255 },
2256 };
2257
2258 /* Reset state of MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */
2259 static struct clk_branch mdss_dp_link_intf_clk = {
2260 .halt_reg = 0x2358,
2261 .halt_check = BRANCH_HALT,
2262 .clkr = {
2263 .enable_reg = 0x2358,
2264 .enable_mask = BIT(0),
2265 .hw.init = &(struct clk_init_data){
2266 .name = "mdss_dp_link_intf_clk",
2267 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
2268 .num_parents = 1,
2269 .ops = &clk_branch2_ops,
2270 },
2271 },
2272 };
2273
2274 static struct clk_branch mdss_dp_pixel_clk = {
2275 .halt_reg = 0x2360,
2276 .halt_check = BRANCH_HALT,
2277 .clkr = {
2278 .enable_reg = 0x2360,
2279 .enable_mask = BIT(0),
2280 .hw.init = &(struct clk_init_data){
2281 .name = "mdss_dp_pixel_clk",
2282 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
2283 .num_parents = 1,
2284 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2285 .ops = &clk_branch2_ops,
2286 },
2287 },
2288 };
2289
2290 static struct clk_branch mdss_esc0_clk = {
2291 .halt_reg = 0x2344,
2292 .halt_check = BRANCH_HALT,
2293 .clkr = {
2294 .enable_reg = 0x2344,
2295 .enable_mask = BIT(0),
2296 .hw.init = &(struct clk_init_data){
2297 .name = "mdss_esc0_clk",
2298 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
2299 .num_parents = 1,
2300 .flags = CLK_SET_RATE_PARENT,
2301 .ops = &clk_branch2_ops,
2302 },
2303 },
2304 };
2305
2306 static struct clk_branch mdss_esc1_clk = {
2307 .halt_reg = 0x2348,
2308 .halt_check = BRANCH_HALT,
2309 .clkr = {
2310 .enable_reg = 0x2348,
2311 .enable_mask = BIT(0),
2312 .hw.init = &(struct clk_init_data){
2313 .name = "mdss_esc1_clk",
2314 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
2315 .num_parents = 1,
2316 .flags = CLK_SET_RATE_PARENT,
2317 .ops = &clk_branch2_ops,
2318 },
2319 },
2320 };
2321
2322 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
2323 .halt_reg = 0x230c,
2324 .halt_check = BRANCH_HALT,
2325 .clkr = {
2326 .enable_reg = 0x230c,
2327 .enable_mask = BIT(0),
2328 .hw.init = &(struct clk_init_data){
2329 .name = "mdss_hdmi_dp_ahb_clk",
2330 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2331 .num_parents = 1,
2332 .ops = &clk_branch2_ops,
2333 },
2334 },
2335 };
2336
2337 static struct clk_branch mdss_mdp_clk = {
2338 .halt_reg = 0x231c,
2339 .halt_check = BRANCH_HALT,
2340 .clkr = {
2341 .enable_reg = 0x231c,
2342 .enable_mask = BIT(0),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "mdss_mdp_clk",
2345 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
2346 .num_parents = 1,
2347 .flags = CLK_SET_RATE_PARENT,
2348 .ops = &clk_branch2_ops,
2349 },
2350 },
2351 };
2352
2353 static struct clk_branch mdss_pclk0_clk = {
2354 .halt_reg = 0x2314,
2355 .halt_check = BRANCH_HALT,
2356 .clkr = {
2357 .enable_reg = 0x2314,
2358 .enable_mask = BIT(0),
2359 .hw.init = &(struct clk_init_data){
2360 .name = "mdss_pclk0_clk",
2361 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
2362 .num_parents = 1,
2363 .flags = CLK_SET_RATE_PARENT,
2364 .ops = &clk_branch2_ops,
2365 },
2366 },
2367 };
2368
2369 static struct clk_branch mdss_pclk1_clk = {
2370 .halt_reg = 0x2318,
2371 .halt_check = BRANCH_HALT,
2372 .clkr = {
2373 .enable_reg = 0x2318,
2374 .enable_mask = BIT(0),
2375 .hw.init = &(struct clk_init_data){
2376 .name = "mdss_pclk1_clk",
2377 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
2378 .num_parents = 1,
2379 .flags = CLK_SET_RATE_PARENT,
2380 .ops = &clk_branch2_ops,
2381 },
2382 },
2383 };
2384
2385 static struct clk_branch mdss_rot_clk = {
2386 .halt_reg = 0x2350,
2387 .halt_check = BRANCH_HALT,
2388 .clkr = {
2389 .enable_reg = 0x2350,
2390 .enable_mask = BIT(0),
2391 .hw.init = &(struct clk_init_data){
2392 .name = "mdss_rot_clk",
2393 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
2394 .num_parents = 1,
2395 .flags = CLK_SET_RATE_PARENT,
2396 .ops = &clk_branch2_ops,
2397 },
2398 },
2399 };
2400
2401 static struct clk_branch mdss_vsync_clk = {
2402 .halt_reg = 0x2328,
2403 .halt_check = BRANCH_HALT,
2404 .clkr = {
2405 .enable_reg = 0x2328,
2406 .enable_mask = BIT(0),
2407 .hw.init = &(struct clk_init_data){
2408 .name = "mdss_vsync_clk",
2409 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
2410 .num_parents = 1,
2411 .flags = CLK_SET_RATE_PARENT,
2412 .ops = &clk_branch2_ops,
2413 },
2414 },
2415 };
2416
2417 static struct clk_branch mnoc_ahb_clk = {
2418 .halt_reg = 0x5024,
2419 .halt_check = BRANCH_VOTED,
2420 .clkr = {
2421 .enable_reg = 0x5024,
2422 .enable_mask = BIT(0),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "mnoc_ahb_clk",
2425 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2426 .num_parents = 1,
2427 .flags = CLK_SET_RATE_PARENT,
2428 .ops = &clk_branch2_ops,
2429 },
2430 },
2431 };
2432
2433 static struct clk_branch misc_ahb_clk = {
2434 .halt_reg = 0x328,
2435 .halt_check = BRANCH_HALT,
2436 .hwcg_reg = 0x328,
2437 .hwcg_bit = 1,
2438 .clkr = {
2439 .enable_reg = 0x328,
2440 .enable_mask = BIT(0),
2441 .hw.init = &(struct clk_init_data){
2442 .name = "misc_ahb_clk",
2443 /*
2444 * Dependency to be enabled before the branch is
2445 * enabled.
2446 */
2447 .parent_hws = (const struct clk_hw *[]){ &mnoc_ahb_clk.clkr.hw },
2448 .num_parents = 1,
2449 .ops = &clk_branch2_ops,
2450 },
2451 },
2452 };
2453
2454 static struct clk_branch misc_cxo_clk = {
2455 .halt_reg = 0x324,
2456 .halt_check = BRANCH_HALT,
2457 .clkr = {
2458 .enable_reg = 0x324,
2459 .enable_mask = BIT(0),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "misc_cxo_clk",
2462 .parent_data = &(const struct clk_parent_data){
2463 .fw_name = "xo",
2464 },
2465 .num_parents = 1,
2466 .ops = &clk_branch2_ops,
2467 },
2468 },
2469 };
2470
2471 static struct clk_branch snoc_dvm_axi_clk = {
2472 .halt_reg = 0xe040,
2473 .halt_check = BRANCH_HALT,
2474 .clkr = {
2475 .enable_reg = 0xe040,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "snoc_dvm_axi_clk",
2479 .ops = &clk_branch2_ops,
2480 },
2481 },
2482 };
2483
2484 static struct clk_branch video_ahb_clk = {
2485 .halt_reg = 0x1030,
2486 .halt_check = BRANCH_HALT,
2487 .hwcg_reg = 0x1030,
2488 .hwcg_bit = 1,
2489 .clkr = {
2490 .enable_reg = 0x1030,
2491 .enable_mask = BIT(0),
2492 .hw.init = &(struct clk_init_data){
2493 .name = "video_ahb_clk",
2494 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2495 .num_parents = 1,
2496 .ops = &clk_branch2_ops,
2497 },
2498 },
2499 };
2500
2501 static struct clk_branch video_axi_clk = {
2502 .halt_reg = 0x1034,
2503 .halt_check = BRANCH_HALT,
2504 .clkr = {
2505 .enable_reg = 0x1034,
2506 .enable_mask = BIT(0),
2507 .hw.init = &(struct clk_init_data){
2508 .name = "video_axi_clk",
2509 .ops = &clk_branch2_ops,
2510 },
2511 },
2512 };
2513
2514 static struct clk_branch throttle_video_axi_clk = {
2515 .halt_reg = 0x118c,
2516 .halt_check = BRANCH_HALT,
2517 .hwcg_reg = 0x118c,
2518 .hwcg_bit = 1,
2519 .clkr = {
2520 .enable_reg = 0x118c,
2521 .enable_mask = BIT(0),
2522 .hw.init = &(struct clk_init_data){
2523 .name = "throttle_video_axi_clk",
2524 .ops = &clk_branch2_ops,
2525 },
2526 },
2527 };
2528
2529 static struct clk_branch video_core_clk = {
2530 .halt_reg = 0x1028,
2531 .halt_check = BRANCH_HALT,
2532 .clkr = {
2533 .enable_reg = 0x1028,
2534 .enable_mask = BIT(0),
2535 .hw.init = &(struct clk_init_data){
2536 .name = "video_core_clk",
2537 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
2538 .num_parents = 1,
2539 .flags = CLK_SET_RATE_PARENT,
2540 .ops = &clk_branch2_ops,
2541 },
2542 },
2543 };
2544
2545 static struct clk_branch video_subcore0_clk = {
2546 .halt_reg = 0x1048,
2547 .halt_check = BRANCH_HALT,
2548 .clkr = {
2549 .enable_reg = 0x1048,
2550 .enable_mask = BIT(0),
2551 .hw.init = &(struct clk_init_data){
2552 .name = "video_subcore0_clk",
2553 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
2554 .num_parents = 1,
2555 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2556 .ops = &clk_branch2_ops,
2557 },
2558 },
2559 };
2560
2561 static struct gdsc venus_gdsc = {
2562 .gdscr = 0x1024,
2563 .cxcs = (unsigned int[]){ 0x1028, 0x1034, 0x1048 },
2564 .cxc_count = 3,
2565 .pd = {
2566 .name = "venus",
2567 },
2568 .pwrsts = PWRSTS_OFF_ON,
2569 };
2570
2571 static struct gdsc venus_core0_gdsc = {
2572 .gdscr = 0x1040,
2573 .pd = {
2574 .name = "venus_core0",
2575 },
2576 .parent = &venus_gdsc.pd,
2577 .pwrsts = PWRSTS_OFF_ON,
2578 .flags = HW_CTRL,
2579 };
2580
2581 static struct gdsc mdss_gdsc = {
2582 .gdscr = 0x2304,
2583 .pd = {
2584 .name = "mdss",
2585 },
2586 .cxcs = (unsigned int []){ 0x2040 },
2587 .cxc_count = 1,
2588 .pwrsts = PWRSTS_OFF_ON,
2589 };
2590
2591 static struct gdsc camss_top_gdsc = {
2592 .gdscr = 0x34a0,
2593 .pd = {
2594 .name = "camss_top",
2595 },
2596 .pwrsts = PWRSTS_OFF_ON,
2597 };
2598
2599 static struct gdsc camss_vfe0_gdsc = {
2600 .gdscr = 0x3664,
2601 .pd = {
2602 .name = "camss_vfe0",
2603 },
2604 .parent = &camss_top_gdsc.pd,
2605 .pwrsts = PWRSTS_OFF_ON,
2606 };
2607
2608 static struct gdsc camss_vfe1_gdsc = {
2609 .gdscr = 0x3674,
2610 .pd = {
2611 .name = "camss_vfe1_gdsc",
2612 },
2613 .parent = &camss_top_gdsc.pd,
2614 .pwrsts = PWRSTS_OFF_ON,
2615 };
2616
2617 static struct gdsc camss_cpp_gdsc = {
2618 .gdscr = 0x36d4,
2619 .pd = {
2620 .name = "camss_cpp",
2621 },
2622 .parent = &camss_top_gdsc.pd,
2623 .pwrsts = PWRSTS_OFF_ON,
2624 };
2625
2626 /* This GDSC seems to hang the whole multimedia subsystem.
2627 static struct gdsc bimc_smmu_gdsc = {
2628 .gdscr = 0xe020,
2629 .gds_hw_ctrl = 0xe024,
2630 .pd = {
2631 .name = "bimc_smmu",
2632 },
2633 .pwrsts = PWRSTS_OFF_ON,
2634 .parent = &bimc_smmu_gdsc.pd,
2635 .flags = HW_CTRL,
2636 };
2637 */
2638
2639 static struct clk_regmap *mmcc_660_clocks[] = {
2640 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2641 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2642 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2643 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2644 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2645 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2646 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2647 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2648 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2649 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2650 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2651 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2652 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2653 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2654 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2655 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2656 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2657 [DP_GTC_CLK_SRC] = &dp_gtc_clk_src.clkr,
2658 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2659 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2660 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2661 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2662 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2663 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2664 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2665 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2666 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2667 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2668 [MMPLL0_PLL] = &mmpll0.clkr,
2669 [MMPLL10_PLL] = &mmpll10.clkr,
2670 [MMPLL3_PLL] = &mmpll3.clkr,
2671 [MMPLL4_PLL] = &mmpll4.clkr,
2672 [MMPLL5_PLL] = &mmpll5.clkr,
2673 [MMPLL6_PLL] = &mmpll6.clkr,
2674 [MMPLL7_PLL] = &mmpll7.clkr,
2675 [MMPLL8_PLL] = &mmpll8.clkr,
2676 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2677 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2678 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2679 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2680 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2681 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2682 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2683 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2684 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2685 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2686 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2687 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2688 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2689 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2690 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2691 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2692 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2693 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2694 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2695 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2696 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2697 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2698 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2699 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2700 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2701 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2702 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2703 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2704 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2705 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2706 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2707 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2708 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2709 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2710 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2711 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2712 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2713 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2714 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2715 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2716 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2717 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2718 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2719 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2720 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2721 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2722 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2723 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2724 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2725 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2726 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2727 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2728 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2729 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2730 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2731 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2732 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2733 [CSIPHY_AHB2CRIF_CLK] = &csiphy_ahb2crif_clk.clkr,
2734 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2735 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2736 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2737 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2738 [MDSS_BYTE0_INTF_DIV_CLK] = &mdss_byte0_intf_div_clk.clkr,
2739 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2740 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2741 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2742 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2743 [MDSS_DP_GTC_CLK] = &mdss_dp_gtc_clk.clkr,
2744 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2745 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2746 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2747 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2748 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2749 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2750 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2751 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2752 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2753 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2754 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2755 [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2756 [MISC_CXO_CLK] = &misc_cxo_clk.clkr,
2757 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2758 [SNOC_DVM_AXI_CLK] = &snoc_dvm_axi_clk.clkr,
2759 [THROTTLE_CAMSS_AXI_CLK] = &throttle_camss_axi_clk.clkr,
2760 [THROTTLE_MDSS_AXI_CLK] = &throttle_mdss_axi_clk.clkr,
2761 [THROTTLE_VIDEO_AXI_CLK] = &throttle_video_axi_clk.clkr,
2762 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2763 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2764 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
2765 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2766 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2767 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2768 [ROT_CLK_SRC] = &rot_clk_src.clkr,
2769 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2770 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2771 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2772 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2773 [MDSS_BYTE1_INTF_DIV_CLK] = &mdss_byte1_intf_div_clk.clkr,
2774 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2775 };
2776
2777 static struct gdsc *mmcc_sdm660_gdscs[] = {
2778 [VENUS_GDSC] = &venus_gdsc,
2779 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
2780 [MDSS_GDSC] = &mdss_gdsc,
2781 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2782 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2783 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2784 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2785 };
2786
2787 static const struct qcom_reset_map mmcc_660_resets[] = {
2788 [CAMSS_MICRO_BCR] = { 0x3490 },
2789 };
2790
2791 static const struct regmap_config mmcc_660_regmap_config = {
2792 .reg_bits = 32,
2793 .reg_stride = 4,
2794 .val_bits = 32,
2795 .max_register = 0x40000,
2796 .fast_io = true,
2797 };
2798
2799 static const struct qcom_cc_desc mmcc_660_desc = {
2800 .config = &mmcc_660_regmap_config,
2801 .clks = mmcc_660_clocks,
2802 .num_clks = ARRAY_SIZE(mmcc_660_clocks),
2803 .resets = mmcc_660_resets,
2804 .num_resets = ARRAY_SIZE(mmcc_660_resets),
2805 .gdscs = mmcc_sdm660_gdscs,
2806 .num_gdscs = ARRAY_SIZE(mmcc_sdm660_gdscs),
2807 };
2808
2809 static const struct of_device_id mmcc_660_match_table[] = {
2810 { .compatible = "qcom,mmcc-sdm660" },
2811 { .compatible = "qcom,mmcc-sdm630", .data = (void *)1UL },
2812 { }
2813 };
2814 MODULE_DEVICE_TABLE(of, mmcc_660_match_table);
2815
sdm630_clock_override(void)2816 static void sdm630_clock_override(void)
2817 {
2818 /* SDM630 has only one DSI */
2819 mmcc_660_desc.clks[BYTE1_CLK_SRC] = NULL;
2820 mmcc_660_desc.clks[MDSS_BYTE1_CLK] = NULL;
2821 mmcc_660_desc.clks[MDSS_BYTE1_INTF_DIV_CLK] = NULL;
2822 mmcc_660_desc.clks[MDSS_BYTE1_INTF_CLK] = NULL;
2823 mmcc_660_desc.clks[ESC1_CLK_SRC] = NULL;
2824 mmcc_660_desc.clks[MDSS_ESC1_CLK] = NULL;
2825 mmcc_660_desc.clks[PCLK1_CLK_SRC] = NULL;
2826 mmcc_660_desc.clks[MDSS_PCLK1_CLK] = NULL;
2827 }
2828
mmcc_660_probe(struct platform_device * pdev)2829 static int mmcc_660_probe(struct platform_device *pdev)
2830 {
2831 const struct of_device_id *id;
2832 struct regmap *regmap;
2833 bool is_sdm630;
2834
2835 id = of_match_device(mmcc_660_match_table, &pdev->dev);
2836 if (!id)
2837 return -ENODEV;
2838 is_sdm630 = !!(id->data);
2839
2840 regmap = qcom_cc_map(pdev, &mmcc_660_desc);
2841 if (IS_ERR(regmap))
2842 return PTR_ERR(regmap);
2843
2844 if (is_sdm630)
2845 sdm630_clock_override();
2846
2847 clk_alpha_pll_configure(&mmpll3, regmap, &mmpll3_config);
2848 clk_alpha_pll_configure(&mmpll4, regmap, &mmpll4_config);
2849 clk_alpha_pll_configure(&mmpll5, regmap, &mmpll5_config);
2850 clk_alpha_pll_configure(&mmpll7, regmap, &mmpll7_config);
2851 clk_alpha_pll_configure(&mmpll8, regmap, &mmpll8_config);
2852 clk_alpha_pll_configure(&mmpll10, regmap, &mmpll10_config);
2853
2854 return qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap);
2855 }
2856
2857 static struct platform_driver mmcc_660_driver = {
2858 .probe = mmcc_660_probe,
2859 .driver = {
2860 .name = "mmcc-sdm660",
2861 .of_match_table = mmcc_660_match_table,
2862 },
2863 };
2864 module_platform_driver(mmcc_660_driver);
2865
2866 MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 MMCC driver");
2867 MODULE_LICENSE("GPL v2");
2868