1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022 Collabora Ltd.
4 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
5 */
6
7 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include "clk-mtk.h"
11 #include "clk-pll.h"
12
13 #define REG_REF2USB 0x8
14 #define REG_AP_PLL_CON7 0x1c
15 #define MD1_MTCMOS_OFF BIT(0)
16 #define MD1_MEM_OFF BIT(1)
17 #define MD1_CLK_OFF BIT(4)
18 #define MD1_ISO_OFF BIT(8)
19
20 #define MT6795_PLL_FMAX (3000UL * MHZ)
21 #define MT6795_CON0_EN BIT(0)
22 #define MT6795_CON0_RST_BAR BIT(24)
23
24 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
25 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
26 .id = _id, \
27 .name = _name, \
28 .reg = _reg, \
29 .pwr_reg = _pwr_reg, \
30 .en_mask = MT6795_CON0_EN | _en_mask, \
31 .flags = _flags, \
32 .rst_bar_mask = MT6795_CON0_RST_BAR, \
33 .fmax = MT6795_PLL_FMAX, \
34 .pcwbits = _pcwbits, \
35 .pd_reg = _pd_reg, \
36 .pd_shift = _pd_shift, \
37 .tuner_reg = _tuner_reg, \
38 .pcw_reg = _pcw_reg, \
39 .pcw_shift = _pcw_shift, \
40 .div_table = NULL, \
41 .pll_en_bit = 0, \
42 }
43
44 static const struct mtk_pll_data plls[] = {
45 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
46 21, 0x204, 24, 0x0, 0x204, 0),
47 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
48 21, 0x220, 4, 0x0, 0x224, 0),
49 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
50 7, 0x230, 4, 0x0, 0x234, 14),
51 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),
52 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
53 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
54 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
55 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
56 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
57 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a8, 0x2a4, 0),
58 PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0),
59 };
60
clk_mt6795_apmixed_setup_md1(void __iomem * base)61 static void clk_mt6795_apmixed_setup_md1(void __iomem *base)
62 {
63 void __iomem *reg = base + REG_AP_PLL_CON7;
64
65 /* Turn on MD1 internal clock */
66 writel(readl(reg) & ~MD1_CLK_OFF, reg);
67
68 /* Unlock MD1's MTCMOS power path */
69 writel(readl(reg) & ~MD1_MTCMOS_OFF, reg);
70
71 /* Turn on ISO */
72 writel(readl(reg) & ~MD1_ISO_OFF, reg);
73
74 /* Turn on memory */
75 writel(readl(reg) & ~MD1_MEM_OFF, reg);
76 }
77
78 static const struct of_device_id of_match_clk_mt6795_apmixed[] = {
79 { .compatible = "mediatek,mt6795-apmixedsys" },
80 { /* sentinel */ }
81 };
82
clk_mt6795_apmixed_probe(struct platform_device * pdev)83 static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
84 {
85 struct clk_hw_onecell_data *clk_data;
86 struct device *dev = &pdev->dev;
87 struct device_node *node = dev->of_node;
88 void __iomem *base;
89 struct clk_hw *hw;
90 int ret;
91
92 base = devm_platform_ioremap_resource(pdev, 0);
93 if (IS_ERR(base))
94 return PTR_ERR(base);
95
96 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
97 if (!clk_data)
98 return -ENOMEM;
99
100 ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
101 if (ret)
102 goto free_clk_data;
103
104 hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REG_REF2USB);
105 if (IS_ERR(hw)) {
106 ret = PTR_ERR(hw);
107 dev_err(dev, "Failed to register ref2usb_tx: %d\n", ret);
108 goto unregister_plls;
109 }
110 clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
111
112 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
113 if (ret) {
114 dev_err(dev, "Cannot register clock provider: %d\n", ret);
115 goto unregister_ref2usb;
116 }
117
118 /* Setup MD1 to avoid random crashes */
119 dev_dbg(dev, "Performing initial setup for MD1\n");
120 clk_mt6795_apmixed_setup_md1(base);
121
122 return 0;
123
124 unregister_ref2usb:
125 mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
126 unregister_plls:
127 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
128 free_clk_data:
129 mtk_free_clk_data(clk_data);
130 return ret;
131 }
132
clk_mt6795_apmixed_remove(struct platform_device * pdev)133 static int clk_mt6795_apmixed_remove(struct platform_device *pdev)
134 {
135 struct device_node *node = pdev->dev.of_node;
136 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
137
138 of_clk_del_provider(node);
139 mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
140 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
141 mtk_free_clk_data(clk_data);
142
143 return 0;
144 }
145
146 static struct platform_driver clk_mt6795_apmixed_drv = {
147 .probe = clk_mt6795_apmixed_probe,
148 .remove = clk_mt6795_apmixed_remove,
149 .driver = {
150 .name = "clk-mt6795-apmixed",
151 .of_match_table = of_match_clk_mt6795_apmixed,
152 },
153 };
154 module_platform_driver(clk_mt6795_apmixed_drv);
155
156 MODULE_DESCRIPTION("MediaTek MT6795 apmixed clocks driver");
157 MODULE_LICENSE("GPL");
158