1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
5
6 #include <dt-bindings/clock/at91.h>
7
8 #include "pmc.h"
9
10 static DEFINE_SPINLOCK(mck_lock);
11
12 static const struct clk_master_characteristics mck_characteristics = {
13 .output = { .min = 124000000, .max = 166000000 },
14 .divisors = { 1, 2, 4, 3 },
15 };
16
17 static u8 plla_out[] = { 0 };
18
19 static u16 plla_icpll[] = { 0 };
20
21 static const struct clk_range plla_outputs[] = {
22 { .min = 600000000, .max = 1200000000 },
23 };
24
25 static const struct clk_pll_characteristics plla_characteristics = {
26 .input = { .min = 12000000, .max = 24000000 },
27 .num_output = ARRAY_SIZE(plla_outputs),
28 .output = plla_outputs,
29 .icpll = plla_icpll,
30 .out = plla_out,
31 };
32
33 static const struct clk_pcr_layout sama5d2_pcr_layout = {
34 .offset = 0x10c,
35 .cmd = BIT(12),
36 .gckcss_mask = GENMASK(10, 8),
37 .pid_mask = GENMASK(6, 0),
38 };
39
40 static const struct {
41 char *n;
42 char *p;
43 u8 id;
44 } sama5d2_systemck[] = {
45 { .n = "ddrck", .p = "masterck_div", .id = 2 },
46 { .n = "lcdck", .p = "masterck_div", .id = 3 },
47 { .n = "uhpck", .p = "usbck", .id = 6 },
48 { .n = "udpck", .p = "usbck", .id = 7 },
49 { .n = "pck0", .p = "prog0", .id = 8 },
50 { .n = "pck1", .p = "prog1", .id = 9 },
51 { .n = "pck2", .p = "prog2", .id = 10 },
52 { .n = "iscck", .p = "masterck_div", .id = 18 },
53 };
54
55 static const struct {
56 char *n;
57 u8 id;
58 struct clk_range r;
59 } sama5d2_periph32ck[] = {
60 { .n = "macb0_clk", .id = 5, .r = { .min = 0, .max = 83000000 }, },
61 { .n = "tdes_clk", .id = 11, .r = { .min = 0, .max = 83000000 }, },
62 { .n = "matrix1_clk", .id = 14, },
63 { .n = "hsmc_clk", .id = 17, },
64 { .n = "pioA_clk", .id = 18, .r = { .min = 0, .max = 83000000 }, },
65 { .n = "flx0_clk", .id = 19, .r = { .min = 0, .max = 83000000 }, },
66 { .n = "flx1_clk", .id = 20, .r = { .min = 0, .max = 83000000 }, },
67 { .n = "flx2_clk", .id = 21, .r = { .min = 0, .max = 83000000 }, },
68 { .n = "flx3_clk", .id = 22, .r = { .min = 0, .max = 83000000 }, },
69 { .n = "flx4_clk", .id = 23, .r = { .min = 0, .max = 83000000 }, },
70 { .n = "uart0_clk", .id = 24, .r = { .min = 0, .max = 83000000 }, },
71 { .n = "uart1_clk", .id = 25, .r = { .min = 0, .max = 83000000 }, },
72 { .n = "uart2_clk", .id = 26, .r = { .min = 0, .max = 83000000 }, },
73 { .n = "uart3_clk", .id = 27, .r = { .min = 0, .max = 83000000 }, },
74 { .n = "uart4_clk", .id = 28, .r = { .min = 0, .max = 83000000 }, },
75 { .n = "twi0_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, },
76 { .n = "twi1_clk", .id = 30, .r = { .min = 0, .max = 83000000 }, },
77 { .n = "spi0_clk", .id = 33, .r = { .min = 0, .max = 83000000 }, },
78 { .n = "spi1_clk", .id = 34, .r = { .min = 0, .max = 83000000 }, },
79 { .n = "tcb0_clk", .id = 35, .r = { .min = 0, .max = 83000000 }, },
80 { .n = "tcb1_clk", .id = 36, .r = { .min = 0, .max = 83000000 }, },
81 { .n = "pwm_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
82 { .n = "adc_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, },
83 { .n = "uhphs_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, },
84 { .n = "udphs_clk", .id = 42, .r = { .min = 0, .max = 83000000 }, },
85 { .n = "ssc0_clk", .id = 43, .r = { .min = 0, .max = 83000000 }, },
86 { .n = "ssc1_clk", .id = 44, .r = { .min = 0, .max = 83000000 }, },
87 { .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, },
88 { .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, },
89 { .n = "securam_clk", .id = 51, },
90 { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, },
91 { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, },
92 { .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, },
93 { .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, },
94 { .n = "ptc_clk", .id = 58, .r = { .min = 0, .max = 83000000 }, },
95 { .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, },
96 };
97
98 static const struct {
99 char *n;
100 u8 id;
101 } sama5d2_periphck[] = {
102 { .n = "dma0_clk", .id = 6, },
103 { .n = "dma1_clk", .id = 7, },
104 { .n = "aes_clk", .id = 9, },
105 { .n = "aesb_clk", .id = 10, },
106 { .n = "sha_clk", .id = 12, },
107 { .n = "mpddr_clk", .id = 13, },
108 { .n = "matrix0_clk", .id = 15, },
109 { .n = "sdmmc0_hclk", .id = 31, },
110 { .n = "sdmmc1_hclk", .id = 32, },
111 { .n = "lcdc_clk", .id = 45, },
112 { .n = "isc_clk", .id = 46, },
113 { .n = "qspi0_clk", .id = 52, },
114 { .n = "qspi1_clk", .id = 53, },
115 };
116
117 static const struct {
118 char *n;
119 u8 id;
120 struct clk_range r;
121 int chg_pid;
122 } sama5d2_gck[] = {
123 { .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
124 { .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
125 { .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
126 { .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
127 { .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
128 { .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
129 { .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
130 { .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
131 { .n = "uart3_gclk", .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
132 { .n = "uart4_gclk", .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
133 { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
134 { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
135 { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
136 { .n = "tcb1_gclk", .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
137 { .n = "pwm_gclk", .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
138 { .n = "isc_gclk", .id = 46, .chg_pid = INT_MIN, },
139 { .n = "pdmic_gclk", .id = 48, .chg_pid = INT_MIN, },
140 { .n = "i2s0_gclk", .id = 54, .chg_pid = 5, },
141 { .n = "i2s1_gclk", .id = 55, .chg_pid = 5, },
142 { .n = "can0_gclk", .id = 56, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
143 { .n = "can1_gclk", .id = 57, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
144 { .n = "classd_gclk", .id = 59, .chg_pid = 5, .r = { .min = 0, .max = 100000000 }, },
145 };
146
147 static const struct clk_programmable_layout sama5d2_programmable_layout = {
148 .pres_mask = 0xff,
149 .pres_shift = 4,
150 .css_mask = 0x7,
151 .have_slck_mck = 0,
152 .is_pres_direct = 1,
153 };
154
sama5d2_pmc_setup(struct device_node * np)155 static void __init sama5d2_pmc_setup(struct device_node *np)
156 {
157 struct clk_range range = CLK_RANGE(0, 0);
158 const char *slck_name, *mainxtal_name;
159 struct pmc_data *sama5d2_pmc;
160 const char *parent_names[6];
161 struct regmap *regmap, *regmap_sfr;
162 struct clk_hw *hw;
163 int i;
164 bool bypass;
165
166 i = of_property_match_string(np, "clock-names", "slow_clk");
167 if (i < 0)
168 return;
169
170 slck_name = of_clk_get_parent_name(np, i);
171
172 i = of_property_match_string(np, "clock-names", "main_xtal");
173 if (i < 0)
174 return;
175 mainxtal_name = of_clk_get_parent_name(np, i);
176
177 regmap = device_node_to_regmap(np);
178 if (IS_ERR(regmap))
179 return;
180
181 sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPINCK + 1,
182 nck(sama5d2_systemck),
183 nck(sama5d2_periph32ck),
184 nck(sama5d2_gck), 3);
185 if (!sama5d2_pmc)
186 return;
187
188 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
189 100000000);
190 if (IS_ERR(hw))
191 goto err_free;
192
193 bypass = of_property_read_bool(np, "atmel,osc-bypass");
194
195 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
196 bypass);
197 if (IS_ERR(hw))
198 goto err_free;
199
200 parent_names[0] = "main_rc_osc";
201 parent_names[1] = "main_osc";
202 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
203 if (IS_ERR(hw))
204 goto err_free;
205
206 sama5d2_pmc->chws[PMC_MAIN] = hw;
207
208 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
209 &sama5d3_pll_layout, &plla_characteristics);
210 if (IS_ERR(hw))
211 goto err_free;
212
213 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
214 if (IS_ERR(hw))
215 goto err_free;
216
217 sama5d2_pmc->chws[PMC_PLLACK] = hw;
218
219 hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
220 "mainck");
221 if (IS_ERR(hw))
222 goto err_free;
223
224 hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
225 "audiopll_fracck");
226 if (IS_ERR(hw))
227 goto err_free;
228
229 sama5d2_pmc->chws[PMC_AUDIOPINCK] = hw;
230
231 hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
232 "audiopll_fracck");
233 if (IS_ERR(hw))
234 goto err_free;
235
236 sama5d2_pmc->chws[PMC_AUDIOPLLCK] = hw;
237
238 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
239 if (IS_ERR(regmap_sfr))
240 regmap_sfr = NULL;
241
242 hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
243 if (IS_ERR(hw))
244 goto err_free;
245
246 sama5d2_pmc->chws[PMC_UTMI] = hw;
247
248 parent_names[0] = slck_name;
249 parent_names[1] = "mainck";
250 parent_names[2] = "plladivck";
251 parent_names[3] = "utmick";
252 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
253 parent_names,
254 &at91sam9x5_master_layout,
255 &mck_characteristics, &mck_lock);
256 if (IS_ERR(hw))
257 goto err_free;
258
259 hw = at91_clk_register_master_div(regmap, "masterck_div",
260 "masterck_pres",
261 &at91sam9x5_master_layout,
262 &mck_characteristics, &mck_lock,
263 CLK_SET_RATE_GATE, 0);
264 if (IS_ERR(hw))
265 goto err_free;
266
267 sama5d2_pmc->chws[PMC_MCK] = hw;
268
269 hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div");
270 if (IS_ERR(hw))
271 goto err_free;
272
273 sama5d2_pmc->chws[PMC_MCK2] = hw;
274
275 parent_names[0] = "plladivck";
276 parent_names[1] = "utmick";
277 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
278 if (IS_ERR(hw))
279 goto err_free;
280
281 parent_names[0] = slck_name;
282 parent_names[1] = "mainck";
283 parent_names[2] = "plladivck";
284 parent_names[3] = "utmick";
285 parent_names[4] = "masterck_div";
286 parent_names[5] = "audiopll_pmcck";
287 for (i = 0; i < 3; i++) {
288 char name[6];
289
290 snprintf(name, sizeof(name), "prog%d", i);
291
292 hw = at91_clk_register_programmable(regmap, name,
293 parent_names, 6, i,
294 &sama5d2_programmable_layout,
295 NULL);
296 if (IS_ERR(hw))
297 goto err_free;
298
299 sama5d2_pmc->pchws[i] = hw;
300 }
301
302 for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
303 hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
304 sama5d2_systemck[i].p,
305 sama5d2_systemck[i].id);
306 if (IS_ERR(hw))
307 goto err_free;
308
309 sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw;
310 }
311
312 for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
313 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
314 &sama5d2_pcr_layout,
315 sama5d2_periphck[i].n,
316 "masterck_div",
317 sama5d2_periphck[i].id,
318 &range, INT_MIN);
319 if (IS_ERR(hw))
320 goto err_free;
321
322 sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw;
323 }
324
325 for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
326 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
327 &sama5d2_pcr_layout,
328 sama5d2_periph32ck[i].n,
329 "h32mxck",
330 sama5d2_periph32ck[i].id,
331 &sama5d2_periph32ck[i].r,
332 INT_MIN);
333 if (IS_ERR(hw))
334 goto err_free;
335
336 sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw;
337 }
338
339 parent_names[0] = slck_name;
340 parent_names[1] = "mainck";
341 parent_names[2] = "plladivck";
342 parent_names[3] = "utmick";
343 parent_names[4] = "masterck_div";
344 parent_names[5] = "audiopll_pmcck";
345 for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
346 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
347 &sama5d2_pcr_layout,
348 sama5d2_gck[i].n,
349 parent_names, NULL, 6,
350 sama5d2_gck[i].id,
351 &sama5d2_gck[i].r,
352 sama5d2_gck[i].chg_pid);
353 if (IS_ERR(hw))
354 goto err_free;
355
356 sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
357 }
358
359 if (regmap_sfr) {
360 parent_names[0] = "i2s0_clk";
361 parent_names[1] = "i2s0_gclk";
362 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
363 parent_names, 2, 0);
364 if (IS_ERR(hw))
365 goto err_free;
366
367 sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
368
369 parent_names[0] = "i2s1_clk";
370 parent_names[1] = "i2s1_gclk";
371 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
372 parent_names, 2, 1);
373 if (IS_ERR(hw))
374 goto err_free;
375
376 sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
377 }
378
379 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
380
381 return;
382
383 err_free:
384 kfree(sama5d2_pmc);
385 }
386
387 CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
388